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Update sys. Re-organize the sources.

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This commit is contained in:
sorgelig
2020-05-11 23:17:53 +08:00
parent 0c1cb37dba
commit 5a66d5ec1c
102 changed files with 1996 additions and 1364 deletions
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9
TSConf.sv
View File

@ -188,8 +188,7 @@ pll pll
(
.refclk(CLK_50M),
.outclk_0(clk_sys),
.outclk_1(SDRAM_CLK),
.outclk_2(clk_vid)
.outclk_1(clk_vid)
);
reg ce_28m;
@ -213,6 +212,7 @@ wire [24:0] ps2_mouse;
wire [10:0] ps2_key;
wire forced_scandoubler;
wire [21:0] gamma_bus;
wire [31:0] sd_lba;
wire sd_rd;
@ -249,6 +249,7 @@ hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
.buttons(buttons),
.status(status),
.forced_scandoubler(forced_scandoubler),
.gamma_bus(gamma_bus),
.RTC(RTC),
@ -299,6 +300,7 @@ tsconf tsconf
.SDRAM_nRAS(SDRAM_nRAS),
.SDRAM_CKE(SDRAM_CKE),
.SDRAM_nCS(SDRAM_nCS),
.SDRAM_CLK(SDRAM_CLK),
.VGA_R(R),
.VGA_G(G),
@ -393,10 +395,9 @@ end
wire [1:0] scale = status[2:1];
assign VGA_SL = {scale == 3, scale == 2};
video_mixer video_mixer
video_mixer #(.GAMMA(1)) video_mixer
(
.*,
.clk_sys(clk_vid),
.ce_pix_out(CE_PIXEL),
.scanlines(0),

70
files.qip
View File

@ -1,36 +1,36 @@
set_global_assignment -name QIP_FILE src/t80/T80.qip
set_global_assignment -name VERILOG_FILE src/memory/dma.v
set_global_assignment -name VERILOG_FILE src/memory/arbiter.v
set_global_assignment -name QIP_FILE src/memory/sdram.qip
set_global_assignment -name SYSTEMVERILOG_FILE src/memory/ddram.sv
set_global_assignment -name VERILOG_FILE src/memory/dpram.v
set_global_assignment -name VERILOG_FILE src/common/zsignals.v
set_global_assignment -name VERILOG_FILE src/common/zports.v
set_global_assignment -name VERILOG_FILE src/common/zmem.v
set_global_assignment -name VERILOG_FILE src/common/zmaps.v
set_global_assignment -name VERILOG_FILE src/common/zint.v
set_global_assignment -name VERILOG_FILE src/common/zclock.v
set_global_assignment -name VERILOG_FILE src/rtc/mc146818a.v
set_global_assignment -name VHDL_FILE src/sound/soundrive.vhd
set_global_assignment -name QIP_FILE src/sound/jt12/jt12.qip
set_global_assignment -name SYSTEMVERILOG_FILE src/sound/ym2149.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/sound/ym2203.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/sound/turbosound.sv
set_global_assignment -name VERILOG_FILE src/sound/gs.v
set_global_assignment -name SYSTEMVERILOG_FILE src/sound/saa1099.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/sound/compressor.sv
set_global_assignment -name VERILOG_FILE src/video/video_ts_render.v
set_global_assignment -name VERILOG_FILE src/video/video_ts.v
set_global_assignment -name VERILOG_FILE src/video/video_sync.v
set_global_assignment -name VERILOG_FILE src/video/video_render.v
set_global_assignment -name VERILOG_FILE src/video/video_ports.v
set_global_assignment -name VERILOG_FILE src/video/video_out.v
set_global_assignment -name VERILOG_FILE src/video/video_mode.v
set_global_assignment -name VERILOG_FILE src/video/video_fetch.v
set_global_assignment -name VERILOG_FILE src/video/video_top.v
set_global_assignment -name VHDL_FILE src/keyboard.vhd
set_global_assignment -name VERILOG_FILE src/kempston_mouse.v
set_global_assignment -name VERILOG_FILE src/spi.v
set_global_assignment -name VERILOG_FILE src/clock.v
set_global_assignment -name VERILOG_FILE src/tsconf.v
set_global_assignment -name QIP_FILE rtl/T80/T80.qip
set_global_assignment -name VERILOG_FILE rtl/memory/dma.v
set_global_assignment -name VERILOG_FILE rtl/memory/arbiter.v
set_global_assignment -name VERILOG_FILE rtl/memory/sdram.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/memory/ddram.sv
set_global_assignment -name VERILOG_FILE rtl/memory/dpram.v
set_global_assignment -name VERILOG_FILE rtl/common/zsignals.v
set_global_assignment -name VERILOG_FILE rtl/common/zports.v
set_global_assignment -name VERILOG_FILE rtl/common/zmem.v
set_global_assignment -name VERILOG_FILE rtl/common/zmaps.v
set_global_assignment -name VERILOG_FILE rtl/common/zint.v
set_global_assignment -name VERILOG_FILE rtl/common/zclock.v
set_global_assignment -name VERILOG_FILE rtl/rtc/mc146818a.v
set_global_assignment -name VHDL_FILE rtl/sound/soundrive.vhd
set_global_assignment -name QIP_FILE rtl/sound/jt12/jt12.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/ym2149.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/ym2203.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/turbosound.sv
set_global_assignment -name VERILOG_FILE rtl/sound/gs.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/saa1099.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/compressor.sv
set_global_assignment -name VERILOG_FILE rtl/video/video_ts_render.v
set_global_assignment -name VERILOG_FILE rtl/video/video_ts.v
set_global_assignment -name VERILOG_FILE rtl/video/video_sync.v
set_global_assignment -name VERILOG_FILE rtl/video/video_render.v
set_global_assignment -name VERILOG_FILE rtl/video/video_ports.v
set_global_assignment -name VERILOG_FILE rtl/video/video_out.v
set_global_assignment -name VERILOG_FILE rtl/video/video_mode.v
set_global_assignment -name VERILOG_FILE rtl/video/video_fetch.v
set_global_assignment -name VERILOG_FILE rtl/video/video_top.v
set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
set_global_assignment -name VERILOG_FILE rtl/kempston_mouse.v
set_global_assignment -name VERILOG_FILE rtl/spi.v
set_global_assignment -name VERILOG_FILE rtl/clock.v
set_global_assignment -name VERILOG_FILE rtl/tsconf.v
set_global_assignment -name SYSTEMVERILOG_FILE TSConf.sv

6
rtl/T80/T80.qip Normal file
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@ -0,0 +1,6 @@
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80s.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80pa.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_Reg.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_MCode.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80_ALU.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) T80.vhd ]

7
src/t80/T80.vhd → rtl/T80/T80.vhd
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@ -79,7 +79,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.T80_Pack.all;
entity T80 is
generic(
@ -260,7 +259,7 @@ begin
else DOR(127 downto 112) & DOR(47 downto 0) & DOR(63 downto 48) & DOR(111 downto 64) &
std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC;
mcode : T80_MCode
mcode : work.T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
@ -328,7 +327,7 @@ begin
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
alu : work.T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
@ -920,7 +919,7 @@ begin
end if;
end process;
Regs : T80_Reg
Regs : work.T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,

0
src/t80/T80_ALU.vhd → rtl/T80/T80_ALU.vhd
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1
src/t80/T80_MCode.vhd → rtl/T80/T80_MCode.vhd
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@ -74,7 +74,6 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80_MCode is
generic(

0
src/t80/T80_Reg.vhd → rtl/T80/T80_Reg.vhd
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3
src/t80/T80pa.vhd → rtl/T80/T80pa.vhd
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@ -56,7 +56,6 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80pa is
generic(
@ -108,7 +107,7 @@ begin
BUSAK_n <= BUSAK;
u0 : T80
u0 : work.T80
generic map(
Mode => Mode,
IOWait => 1

26
src/t80/T80s.vhd → rtl/T80/T80s.vhd
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@ -68,7 +68,7 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity T80s is
generic(
@ -78,7 +78,7 @@ entity T80s is
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLK : in std_logic;
CEN : in std_logic := '1';
WAIT_n : in std_logic := '1';
INT_n : in std_logic := '1';
@ -111,7 +111,7 @@ architecture rtl of T80s is
begin
u0 : T80
u0 : work.T80
generic map(
Mode => Mode,
IOWait => IOWait)
@ -129,7 +129,7 @@ begin
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
@ -140,7 +140,7 @@ begin
IntCycle_n => IntCycle_n
);
process (RESET_n, CLK_n)
process (RESET_n, CLK)
begin
if RESET_n = '0' then
RD_n <= '1';
@ -148,42 +148,42 @@ begin
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif rising_edge(CLK_n) then
elsif rising_edge(CLK) then
if CEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
if MCycle = 1 then
if TState = 1 or (TState = 2 and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
if TState = 3 then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
if (TState = 1 or (TState = 2 and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
if TState = 2 and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
if (TState = 1 or (TState = 2 and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
if TState = 2 and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;

0
src/clock.v → rtl/clock.v
View File

0
src/common/zclock.v → rtl/common/zclock.v
View File

0
src/common/zint.v → rtl/common/zint.v
View File

0
src/common/zmaps.v → rtl/common/zmaps.v
View File

0
src/common/zmem.v → rtl/common/zmem.v
View File

0
src/common/zports.v → rtl/common/zports.v
View File

0
src/common/zsignals.v → rtl/common/zsignals.v
View File

0
src/kempston_mouse.v → rtl/kempston_mouse.v
View File

0
src/keyboard.vhd → rtl/keyboard.vhd
View File

0
src/memory/arbiter.v → rtl/memory/arbiter.v
View File

0
src/memory/ddram.sv → rtl/memory/ddram.sv
View File

0
src/memory/dma.v → rtl/memory/dma.v
View File

0
src/memory/dpram.v → rtl/memory/dpram.v
View File

28
src/memory/sdram.v → rtl/memory/sdram.v
View File

@ -24,7 +24,8 @@ module sdram
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
output SDRAM_CKE
output SDRAM_CKE,
output SDRAM_CLK
);
reg [2:0] sdr_cmd;
@ -117,4 +118,29 @@ assign SDRAM_nWE = sdr_cmd[0];
assign SDRAM_DQML = SDRAM_A[11];
assign SDRAM_DQMH = SDRAM_A[12];
altddio_out
#(
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone V"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1)
)
sdramclk_ddr
(
.datain_h(1'b0),
.datain_l(1'b1),
.outclock(clk),
.dataout(SDRAM_CLK),
.aclr(1'b0),
.aset(1'b0),
.oe(1'b1),
.outclocken(1'b1),
.sclr(1'b0),
.sset(1'b0)
);
endmodule

36
sys/pll.qip → rtl/pll.qip
View File

@ -35,17 +35,17 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::ODQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MjIzMzM4Mjk5NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzQzNTk3Mzg0::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
@ -53,23 +53,23 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::ODQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MjIzMzM4Mjk5NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MTQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MzQzNTk3Mzg0::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::OQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::LTQzNTA=::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NTYuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MjM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MjIzMzM4Mjk5NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MjE=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MzQzNTk3Mzg0::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::OQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
@ -259,10 +259,10 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::ODQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::ODQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::LTQzNTcgcHM=::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::NTYuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::NTYuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
@ -317,8 +317,8 @@ set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAM
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTIsMTEsMjU2LDI1NixmYWxzZSx0cnVlLHRydWUsZmFsc2UsNyw3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDcsNyw5LDcscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxMSwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDEsMjAsNDAwMCwxMTc2LjAgTUh6LDIyMzMzODI5OTQsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw1LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzLDMsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsNSw0LDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsMiwyMCw0MDAwLDUwNC4wIE1IeiwzNDM1OTczODQsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"

14
sys/pll.v → rtl/pll.v
View File

@ -2,15 +2,14 @@
// GENERATION: XML
// pll.v
// Generated using ACDS version 17.0 598
// Generated using ACDS version 17.0 602
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire outclk_2 // outclk2.clk
output wire outclk_1 // outclk1.clk
);
pll_0002 pll_inst (
@ -18,7 +17,6 @@ module pll (
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.outclk_2 (outclk_2), // outclk2.clk
.locked () // (terminated)
);
@ -29,7 +27,7 @@ endmodule
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Copyright (C) 1991-2020 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
@ -64,7 +62,7 @@ endmodule
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="3" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
@ -78,11 +76,11 @@ endmodule
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="84.0" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="56.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="-4350" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="180.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />

0
sys/pll/pll_0002.qip → rtl/pll/pll_0002.qip
View File

13
sys/pll/pll_0002.v → rtl/pll/pll_0002.v
View File

@ -13,9 +13,6 @@ module pll_0002(
// interface 'outclk1'
output wire outclk_1,
// interface 'outclk2'
output wire outclk_2,
// interface 'locked'
output wire locked
);
@ -24,14 +21,14 @@ module pll_0002(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(3),
.number_of_clocks(2),
.output_clock_frequency0("84.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("84.000000 MHz"),
.phase_shift1("-4357 ps"),
.output_clock_frequency1("56.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("56.000000 MHz"),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
@ -83,7 +80,7 @@ module pll_0002(
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_2, outclk_1, outclk_0}),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),

0
src/rtc/CMOS.bin → rtl/rtc/CMOS.bin
View File

0
src/rtc/CMOS.mif → rtl/rtc/CMOS.mif
View File

2
src/rtc/mc146818a.v → rtl/rtc/mc146818a.v
View File

@ -236,7 +236,7 @@ always @(posedge CLK) begin
end
// 50 Bytes of General Purpose RAM
dpram #(.DATAWIDTH(8), .ADDRWIDTH(8), .MEM_INIT_FILE("src/rtc/CMOS.mif")) CMOS
dpram #(.DATAWIDTH(8), .ADDRWIDTH(8), .MEM_INIT_FILE("rtl/rtc/CMOS.mif")) CMOS
(
.clock (CLK),
.address_a (A),

0
src/sound/compressor.sv → rtl/sound/compressor.sv
View File

0
src/sound/gs.v → rtl/sound/gs.v
View File

0
src/sound/gs105b.mif → rtl/sound/gs105b.mif
View File

21
rtl/sound/jt12/jt12.qip Normal file
View File

@ -0,0 +1,21 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_acc.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_clksync.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_eg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_exprom.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_kon.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_lfo.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_limitamp.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_mmr.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_mod.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_op.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_opram.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_pg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_phrom.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_reg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh_rst.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sh24.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_sumch.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_syn.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt12_timers.v ]

0
src/sound/jt12/jt12.v → rtl/sound/jt12/jt12.v
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0
src/sound/jt12/jt12_acc.v → rtl/sound/jt12/jt12_acc.v
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0
src/sound/jt12/jt12_clksync.v → rtl/sound/jt12/jt12_clksync.v
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0
src/sound/jt12/jt12_eg.v → rtl/sound/jt12/jt12_eg.v
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0
src/sound/jt12/jt12_exprom.v → rtl/sound/jt12/jt12_exprom.v
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0
src/sound/jt12/jt12_kon.v → rtl/sound/jt12/jt12_kon.v
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0
src/sound/jt12/jt12_lfo.v → rtl/sound/jt12/jt12_lfo.v
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0
src/sound/jt12/jt12_limitamp.v → rtl/sound/jt12/jt12_limitamp.v
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0
src/sound/jt12/jt12_mmr.v → rtl/sound/jt12/jt12_mmr.v
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0
src/sound/jt12/jt12_mmr_sim.vh → rtl/sound/jt12/jt12_mmr_sim.vh
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0
src/sound/jt12/jt12_mod.v → rtl/sound/jt12/jt12_mod.v
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0
src/sound/jt12/jt12_op.v → rtl/sound/jt12/jt12_op.v
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0
src/sound/jt12/jt12_opram.v → rtl/sound/jt12/jt12_opram.v
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0
src/sound/jt12/jt12_pg.v → rtl/sound/jt12/jt12_pg.v
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0
src/sound/jt12/jt12_phrom.v → rtl/sound/jt12/jt12_phrom.v
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0
src/sound/jt12/jt12_reg.v → rtl/sound/jt12/jt12_reg.v
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0
src/sound/jt12/jt12_sh.v → rtl/sound/jt12/jt12_sh.v
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0
src/sound/jt12/jt12_sh24.v → rtl/sound/jt12/jt12_sh24.v
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0
src/sound/jt12/jt12_sh_rst.v → rtl/sound/jt12/jt12_sh_rst.v
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0
src/sound/jt12/jt12_sumch.v → rtl/sound/jt12/jt12_sumch.v
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0
src/sound/jt12/jt12_syn.v → rtl/sound/jt12/jt12_syn.v
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0
src/sound/jt12/jt12_timers.v → rtl/sound/jt12/jt12_timers.v
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0
src/sound/jt12/lut.vh → rtl/sound/jt12/lut.vh
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0
src/sound/saa1099.sv → rtl/sound/saa1099.sv
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0
src/sound/soundrive.vhd → rtl/sound/soundrive.vhd
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0
src/sound/turbosound.sv → rtl/sound/turbosound.sv
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0
src/sound/ym2149.sv → rtl/sound/ym2149.sv
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0
src/sound/ym2203.sv → rtl/sound/ym2203.sv
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0
src/spi.v → rtl/spi.v
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0
src/tsbios.mif → rtl/tsbios.mif
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10
src/tsconf.v → rtl/tsconf.v
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@ -70,6 +70,7 @@ module tsconf
output SDRAM_nRAS,
output SDRAM_nWE,
output SDRAM_CKE,
output SDRAM_CLK,
// VGA
output [7:0] VGA_R,
@ -329,7 +330,7 @@ always @(posedge clk) zclk_r <= zclk;
T80s CPU
(
.RESET_n(~reset),
.CLK_n(clk),
.CLK(clk),
.CEN(~zclk_r & zclk),
.INT_n(cpu_int_n_TS),
.M1_n(cpu_m1_n),
@ -675,7 +676,7 @@ zint TS13
// BIOS
wire [7:0] bios_do_bus;
dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE("src/tsbios.mif")) BIOS
dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE("rtl/tsbios.mif")) BIOS
(
.clock(clk),
.address_a({cpu_addr_20[14:0],cpu_wrbsel}),
@ -710,7 +711,8 @@ sdram SE4
.SDRAM_nCAS(SDRAM_nCAS),
.SDRAM_nRAS(SDRAM_nRAS),
.SDRAM_nWE(SDRAM_nWE),
.SDRAM_CKE(SDRAM_CKE)
.SDRAM_CKE(SDRAM_CKE),
.SDRAM_CLK(SDRAM_CLK)
);
@ -826,7 +828,7 @@ wire [14:0] gs_r;
wire [7:0] gs_do_bus;
wire gs_sel = ~cpu_iorq_n & cpu_m1_n & (cpu_a_bus[7:4] == 'hB && cpu_a_bus[2:0] == 'h3);
gs #("src/sound/gs105b.mif") U15
gs #("rtl/sound/gs105b.mif") U15
(
.RESET(reset),
.CLK(clk),

0
src/video/video_cram.mif → rtl/video/video_cram.mif
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0
src/video/video_fetch.v → rtl/video/video_fetch.v
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0
src/video/video_mode.v → rtl/video/video_mode.v
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2
src/video/video_out.v → rtl/video/video_out.v
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@ -37,7 +37,7 @@ wire [7:0] vdata = tv_hires ? {palsel, plex_sel_in[1] ? vplex[3:0] : vplex[7:4]}
// CRAM
wire [15:0] vpixel;
dpram #(.DATAWIDTH(16), .ADDRWIDTH(8), .MEM_INIT_FILE("src/video/video_cram.mif")) video_cram
dpram #(.DATAWIDTH(16), .ADDRWIDTH(8), .MEM_INIT_FILE("rtl/video/video_cram.mif")) video_cram
(
.clock (clk),
.address_a(cram_addr_in),

0
src/video/video_ports.v → rtl/video/video_ports.v
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0
src/video/video_render.v → rtl/video/video_render.v
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0
src/video/video_sync.v → rtl/video/video_sync.v
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0
src/video/video_top.v → rtl/video/video_top.v
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0
src/video/video_ts.v → rtl/video/video_ts.v
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0
src/video/video_ts_render.v → rtl/video/video_ts_render.v
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2
src/memory/sdram.qip
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@ -1,2 +0,0 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sdram.v ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sdram.sdc ]

12
src/memory/sdram.sdc
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@ -1,12 +0,0 @@
derive_pll_clocks
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|*[1].*|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]

21
src/sound/jt12/jt12.qip
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@ -1,21 +0,0 @@
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_acc.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_clksync.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_eg.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_exprom.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_kon.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_lfo.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_limitamp.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_mmr.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_mod.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_op.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_opram.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_pg.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_phrom.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_reg.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_sh.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_sh_rst.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_sh24.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_sumch.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_syn.v
set_global_assignment -name VERILOG_FILE src/sound/jt12/jt12_timers.v

7
src/t80/T80.qip
View File

@ -1,7 +0,0 @@
set_global_assignment -name VHDL_FILE src/t80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE src/t80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE src/t80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE src/t80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE src/t80/T80.vhd
set_global_assignment -name VHDL_FILE src/t80/T80pa.vhd
set_global_assignment -name VHDL_FILE src/t80/T80s.vhd

236
src/t80/T80_Pack.vhd
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@ -1,236 +0,0 @@
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
Stop : out std_logic;
REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0);
DOR : out std_logic_vector(127 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetWZ : out std_logic_vector(1 downto 0);
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
WZ : in std_logic_vector(15 downto 0);
XY_State : in std_logic_vector(1 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

160
sys/alsa.sv
View File

@ -1,7 +1,7 @@
//============================================================================
//
// ALSA sound support for MiSTer
// (c)2019 Sorgelig
// (c)2019,2020 Alexey Melnikov
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
@ -22,111 +22,135 @@
module alsa
(
input reset,
input clk,
output reg en_out,
input en_in,
input ram_clk,
output reg [28:0] ram_address,
output reg [7:0] ram_burstcount,
input ram_waitrequest,
input [63:0] ram_readdata,
input ram_readdatavalid,
output reg ram_read,
output reg [31:3] ram_address,
input [63:0] ram_data,
output reg ram_req = 0,
input ram_ready,
input spi_ss,
input spi_sck,
input spi_mosi,
output spi_miso,
output reg [15:0] pcm_l,
output reg [15:0] pcm_r
);
reg spi_new = 0;
reg [127:0] spi_data;
reg [60:0] buf_info;
reg [6:0] spicnt = 0;
always @(posedge spi_sck, posedge spi_ss) begin
reg [7:0] mosi;
reg [6:0] spicnt = 0;
reg [95:0] spi_data;
if(spi_ss) spicnt <= 0;
else begin
mosi <= {mosi[6:0],spi_mosi};
spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi;
if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]};
spicnt <= spicnt + 1'd1;
if(&spicnt[2:0]) begin
spi_data[{spicnt[6:3],3'b000} +:8] <= {mosi[6:0],spi_mosi};
spi_new <= &spicnt;
end
end
end
reg [31:0] buf_addr;
reg [31:0] buf_len;
reg [31:0] buf_wptr = 0;
assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}];
always @(posedge ram_clk) begin
reg n1,n2,n3;
reg [127:0] data1,data2;
reg [31:0] spi_out = 0;
always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00};
n1 <= spi_new;
n2 <= n1;
n3 <= n2;
data1 <= spi_data;
reg [31:3] buf_addr;
reg [18:3] buf_len;
reg [18:3] buf_wptr = 0;
always @(posedge clk) begin
reg [60:0] data1,data2;
data1 <= buf_info;
data2 <= data1;
if(~n3 & n2) {buf_wptr,buf_len,buf_addr} <= data2[95:0];
if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2;
end
reg [31:0] buf_rptr = 0;
always @(posedge ram_clk) begin
reg [2:0] hurryup = 0;
reg [18:3] buf_rptr = 0;
always @(posedge clk) begin
reg [18:3] len = 0;
reg [1:0] ready = 0;
reg [63:0] readdata;
reg got_first = 0;
reg ready = 0;
reg ud = 0;
reg [31:0] readdata;
reg [7:0] ce_cnt = 0;
reg [1:0] state = 0;
if(~ram_waitrequest) ram_read <= 0;
if(ram_readdatavalid && ram_burstcount) begin
ram_burstcount <= 0;
ready <= 1;
readdata <= ud ? ram_readdata[63:32] : ram_readdata[31:0];
if(buf_rptr[31:2] >= buf_len[31:2]) buf_rptr <= 0;
if(reset) begin
ready <= 0;
ce_cnt <= 0;
state <= 0;
got_first <= 0;
len <= 0;
end
else begin
if(reset) {ready, got_first, ram_burstcount} <= 0;
else
if(buf_rptr[31:2] != buf_wptr[31:2]) begin
//ramp up
if(len[18:14] && (hurryup < 1)) hurryup <= 1;
if(len[18:16] && (hurryup < 2)) hurryup <= 2;
if(len[18:17] && (hurryup < 4)) hurryup <= 4;
//ramp down
if(!len[18:15] && (hurryup > 2)) hurryup <= 2;
if(!len[18:13] && (hurryup > 1)) hurryup <= 1;
if(!len[18:10]) hurryup <= 0;
if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1;
case(state)
0: if(!ce_sample) begin
if(ready) begin
if(ce_cnt) begin
{readdata[31:0],pcm_r,pcm_l} <= readdata;
ready <= ready - 1'd1;
ce_cnt <= ce_cnt - 1'd1;
end
end
else if(buf_rptr != buf_wptr) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else
if(!ram_burstcount && ~ram_waitrequest && ~ready && en_out == en_in) begin
ram_address <= buf_addr[31:3] + buf_rptr[31:3];
ud <= buf_rptr[2];
ram_burstcount <= 1;
ram_read <= 1;
buf_rptr <= buf_rptr + 4;
else begin
ram_address <= buf_addr + buf_rptr;
ram_req <= ~ram_req;
buf_rptr <= buf_rptr + 1'd1;
len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr);
state <= 1;
end
end
if(ready & ce_48k) begin
{pcm_r,pcm_l} <= readdata;
ready <= 0;
else begin
len <= 0;
ce_cnt <= 0;
hurryup <= 0;
end
end
1: if(ram_ready) begin
ready <= 2;
readdata <= ram_data;
if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len;
state <= 0;
end
endcase
end
if(ce_48k) en_out <= ~en_out;
end
reg ce_48k;
always @(posedge ram_clk) begin
reg [15:0] acc = 0;
localparam F48K = 48000;
localparam F50M = 50000000;
ce_48k <= 0;
acc <= acc + 16'd48;
if(acc >= 50000) begin
acc <= acc - 16'd50000;
ce_48k <= 1;
reg ce_sample;
always @(posedge clk) begin
reg [31:0] acc = 0;
ce_sample <= 0;
acc <= acc + F48K + {hurryup,6'd0};
if(acc >= F50M) begin
acc <= acc - F50M;
ce_sample <= 1;
end
end

406
sys/arcade_video.v Normal file
View File

@ -0,0 +1,406 @@
//============================================================================
//
// Copyright (C) 2017-2020 Sorgelig
//
//============================================================================
//////////////////////////////////////////////////////////
// DW:
// 6 : 2R 2G 2B
// 8 : 3R 3G 2B
// 9 : 3R 3G 3B
// 12 : 4R 4G 4B
// 24 : 8R 8G 8B
module arcade_video #(parameter WIDTH=320, HEIGHT=240, DW=8, GAMMA=1)
(
input clk_video,
input ce_pix,
input[DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output VGA_CLK,
output VGA_CE,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output HDMI_CLK,
output HDMI_CE,
output [7:0] HDMI_R,
output [7:0] HDMI_G,
output [7:0] HDMI_B,
output HDMI_HS,
output HDMI_VS,
output HDMI_DE,
output [1:0] HDMI_SL,
input [2:0] fx,
input forced_scandoubler,
input no_rotate,
input rotate_ccw,
inout [21:0] gamma_bus
);
wire [7:0] R,G,B;
wire CE,HS,VS,HBL,VBL;
wire [DW-1:0] RGB_fix;
wire VGA_HBL, VGA_VBL;
arcade_vga #(DW) vga
(
.clk_video(clk_video),
.ce_pix(ce_pix),
.RGB_in(RGB_in),
.HBlank(HBlank),
.VBlank(VBlank),
.HSync(HSync),
.VSync(VSync),
.RGB_out(RGB_fix),
.VGA_CLK(VGA_CLK),
.VGA_CE(CE),
.VGA_R(R),
.VGA_G(G),
.VGA_B(B),
.VGA_HS(HS),
.VGA_VS(VS),
.VGA_HBL(HBL),
.VGA_VBL(VBL)
);
wire [DW-1:0] RGB_out;
wire rhs,rvs,rhblank,rvblank;
screen_rotate #(WIDTH,HEIGHT,DW,4) rotator
(
.clk(VGA_CLK),
.ce(CE),
.ccw(rotate_ccw),
.video_in(RGB_fix),
.hblank(HBL),
.vblank(VBL),
.ce_out(CE | (~scandoubler & ~gamma_bus[19])),
.video_out(RGB_out),
.hsync(rhs),
.vsync(rvs),
.hblank_out(rhblank),
.vblank_out(rvblank)
);
generate
if(DW == 6) begin
wire [3:0] Rr = {RGB_out[5:4],RGB_out[5:4]};
wire [3:0] Gr = {RGB_out[3:2],RGB_out[3:2]};
wire [3:0] Br = {RGB_out[1:0],RGB_out[1:0]};
end
else if(DW == 8) begin
wire [3:0] Rr = {RGB_out[7:5],RGB_out[7]};
wire [3:0] Gr = {RGB_out[4:2],RGB_out[4]};
wire [3:0] Br = {RGB_out[1:0],RGB_out[1:0]};
end
else if(DW == 9) begin
wire [3:0] Rr = {RGB_out[8:6],RGB_out[8]};
wire [3:0] Gr = {RGB_out[5:3],RGB_out[5]};
wire [3:0] Br = {RGB_out[2:0],RGB_out[2]};
end
else if(DW == 12) begin
wire [3:0] Rr = RGB_out[11:8];
wire [3:0] Gr = RGB_out[7:4];
wire [3:0] Br = RGB_out[3:0];
end
else begin // 24
wire [7:0] Rr = RGB_out[23:16];
wire [7:0] Gr = RGB_out[15:8];
wire [7:0] Br = RGB_out[7:0];
end
endgenerate
assign HDMI_CLK = VGA_CLK;
assign HDMI_SL = sl[1:0];
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
wire scandoubler = fx || forced_scandoubler;
video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
(
.clk_vid(HDMI_CLK),
.ce_pix(CE | (~scandoubler & ~gamma_bus[19] & ~no_rotate)),
.ce_pix_out(HDMI_CE),
.scandoubler(scandoubler),
.hq2x(fx==1),
.gamma_bus(gamma_bus),
.R(no_rotate ? ((DW!=24) ? R[7:4] : R) : Rr),
.G(no_rotate ? ((DW!=24) ? G[7:4] : G) : Gr),
.B(no_rotate ? ((DW!=24) ? B[7:4] : B) : Br),
.HSync (no_rotate ? HS : rhs),
.VSync (no_rotate ? VS : rvs),
.HBlank(no_rotate ? HBL : rhblank),
.VBlank(no_rotate ? VBL : rvblank),
.VGA_R(HDMI_R),
.VGA_G(HDMI_G),
.VGA_B(HDMI_B),
.VGA_VS(HDMI_VS),
.VGA_HS(HDMI_HS),
.VGA_DE(HDMI_DE)
);
assign VGA_CE = no_rotate ? HDMI_CE : CE;
assign VGA_R = no_rotate ? HDMI_R : R;
assign VGA_G = no_rotate ? HDMI_G : G;
assign VGA_B = no_rotate ? HDMI_B : B;
assign VGA_HS = no_rotate ? HDMI_HS : HS;
assign VGA_VS = no_rotate ? HDMI_VS : VS;
assign VGA_DE = no_rotate ? HDMI_DE : ~(HBL | VBL);
endmodule
//////////////////////////////////////////////////////////
module arcade_vga #(parameter DW)
(
input clk_video,
input ce_pix,
input [DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output[DW-1:0] RGB_out,
output VGA_CLK,
output reg VGA_CE,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output reg VGA_HS,
output reg VGA_VS,
output reg VGA_HBL,
output reg VGA_VBL
);
assign VGA_CLK = clk_video;
wire hs_fix,vs_fix;
sync_fix sync_v(VGA_CLK, HSync, hs_fix);
sync_fix sync_h(VGA_CLK, VSync, vs_fix);
reg [DW-1:0] RGB_fix;
always @(posedge VGA_CLK) begin
reg old_ce;
old_ce <= ce_pix;
VGA_CE <= 0;
if(~old_ce & ce_pix) begin
VGA_CE <= 1;
VGA_HS <= hs_fix;
if(~VGA_HS & hs_fix) VGA_VS <= vs_fix;
RGB_fix <= RGB_in;
VGA_HBL <= HBlank;
if(VGA_HBL & ~HBlank) VGA_VBL <= VBlank;
end
end
assign RGB_out = RGB_fix;
generate
if(DW == 6) begin
assign VGA_R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
assign VGA_G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
assign VGA_B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 8) begin
assign VGA_R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
assign VGA_G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
assign VGA_B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 9) begin
assign VGA_R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
assign VGA_G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
assign VGA_B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
end
else if(DW == 12) begin
assign VGA_R = {RGB_fix[11:8],RGB_fix[11:8]};
assign VGA_G = {RGB_fix[7:4],RGB_fix[7:4]};
assign VGA_B = {RGB_fix[3:0],RGB_fix[3:0]};
end
else begin // 24
assign VGA_R = RGB_fix[23:16];
assign VGA_G = RGB_fix[15:8];
assign VGA_B = RGB_fix[7:0];
end
endgenerate
endmodule
//============================================================================
//
// Screen +90/-90 deg. rotation
// Copyright (C) 2017-2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
//
// Output timings are incompatible with any TV/VGA mode.
// The output is supposed to be send to scaler input.
//
module screen_rotate #(parameter WIDTH=320, HEIGHT=240, DEPTH=8, MARGIN=4)
(
input clk,
input ce,
input ccw,
input [DEPTH-1:0] video_in,
input hblank,
input vblank,
input ce_out,
output [DEPTH-1:0] video_out,
output reg hsync,
output reg vsync,
output reg hblank_out,
output reg vblank_out
);
localparam bufsize = WIDTH*HEIGHT;
localparam memsize = bufsize*2;
localparam aw = $clog2(memsize); // resolutions up to ~ 512x256
reg [aw-1:0] addr_in, addr_out;
reg we_in;
reg buff = 0;
(* ramstyle="no_rw_check" *) reg [DEPTH-1:0] ram[memsize];
always @ (posedge clk) if (en_we) ram[addr_in] <= video_in;
always @ (posedge clk) out <= ram[addr_out];
reg [DEPTH-1:0] out;
reg [DEPTH-1:0] vout;
assign video_out = vout;
wire en_we = ce & ~blank & en_x & en_y;
wire en_x = (xpos<WIDTH);
wire en_y = (ypos<HEIGHT);
integer xpos, ypos;
wire blank = hblank | vblank;
always @(posedge clk) begin
reg old_blank, old_vblank;
reg [aw-1:0] addr_row;
if(en_we) begin
addr_in <= ccw ? addr_in-HEIGHT[aw-1:0] : addr_in+HEIGHT[aw-1:0];
xpos <= xpos + 1;
end
old_blank <= blank;
old_vblank <= vblank;
if(~old_blank & blank) begin
xpos <= 0;
ypos <= ypos + 1;
addr_in <= ccw ? addr_row + 1'd1 : addr_row - 1'd1;
addr_row <= ccw ? addr_row + 1'd1 : addr_row - 1'd1;
end
if(~old_vblank & vblank) begin
if(buff) begin
addr_in <= ccw ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
addr_row <= ccw ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
end else begin
addr_in <= ccw ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
addr_row <= ccw ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
end
buff <= ~buff;
ypos <= 0;
xpos <= 0;
end
end
always @(posedge clk) begin
reg old_buff;
reg hs;
reg ced;
integer vbcnt;
integer xposo, yposo, xposd, yposd;
ced <= 0;
if(ce_out) begin
ced <= 1;
xposd <= xposo;
yposd <= yposo;
if(xposo == (HEIGHT + 8)) hsync <= 1;
if(xposo == (HEIGHT + 10)) hsync <= 0;
if((yposo>=MARGIN) && (yposo<WIDTH+MARGIN)) begin
if(xposo < HEIGHT) addr_out <= addr_out + 1'd1;
end
xposo <= xposo + 1;
if(xposo > (HEIGHT + 16)) begin
xposo <= 0;
if(yposo >= (WIDTH+MARGIN+MARGIN)) begin
vblank_out <= 1;
vbcnt <= vbcnt + 1;
if(vbcnt == 10 ) vsync <= 1;
if(vbcnt == 12) vsync <= 0;
end
else yposo <= yposo + 1;
old_buff <= buff;
if(old_buff != buff) begin
addr_out <= buff ? {aw{1'b0}} : bufsize[aw-1:0];
yposo <= 0;
vsync <= 0;
vbcnt <= 0;
vblank_out <= 0;
end
end
end
if(ced) begin
if((yposd<MARGIN) || (yposd>=WIDTH+MARGIN)) begin
vout <= 0;
end else begin
vout <= out;
end
if(xposd == 0) hblank_out <= 0;
if(xposd == HEIGHT) hblank_out <= 1;
end
end
endmodule

27
sys/ascal.vhd
View File

@ -164,9 +164,9 @@ ENTITY ascal IS
-- Framebuffer palette in 8bpp mode
pal_clk : IN std_logic :='0';
pal_dw : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B
pal_dr : OUT unsigned(23 DOWNTO 0) :=x"000000";
pal_a : IN unsigned(7 DOWNTO 0) :=x"00"; -- Colour index
pal_dw : IN unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0
pal_dr : OUT unsigned(47 DOWNTO 0) :=x"000000000000";
pal_a : IN unsigned(6 DOWNTO 0) :="0000000"; -- Colour index/2
pal_wr : IN std_logic :='0';
------------------------------------
@ -283,7 +283,7 @@ ARCHITECTURE rtl OF ascal IS
SUBTYPE uint12 IS natural RANGE 0 TO 4095;
SUBTYPE uint13 IS natural RANGE 0 TO 8191;
TYPE arr_uv24 IS ARRAY (natural RANGE <>) OF unsigned(23 DOWNTO 0);
TYPE arr_uv48 IS ARRAY (natural RANGE <>) OF unsigned(47 DOWNTO 0);
TYPE arr_uv36 IS ARRAY (natural RANGE <>) OF unsigned(35 DOWNTO 0);
TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255;
TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12;
@ -386,7 +386,11 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
SIGNAL o_format : unsigned(5 DOWNTO 0);
SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
SIGNAL pal_mem : arr_uv24(0 TO 255);
SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0);
SIGNAL pal_idx: unsigned(7 DOWNTO 0);
SIGNAL pal_idx_lsb: std_logic;
SIGNAL pal_mem : arr_uv48(0 TO 127);
ATTRIBUTE ramstyle of pal_mem : signal is "no_rw_check";
SIGNAL o_htotal,o_hsstart,o_hsend : uint12;
SIGNAL o_hmin,o_hmax,o_hdisp : uint12;
SIGNAL o_hsize,o_vsize : uint12;
@ -422,6 +426,7 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_wr : unsigned(3 DOWNTO 0);
SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3 : uint12;
SIGNAL o_ihsize,o_ivsize : uint12;
SIGNAL o_ihsize_temp, o_ihsize_temp2 : natural RANGE 0 TO 32767;
SIGNAL o_vfrac,o_hfrac,o_hfrac1,o_hfrac2,o_hfrac3,o_hfrac4 : unsigned(11 DOWNTO 0);
SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1;
@ -1709,8 +1714,9 @@ BEGIN
o_format<=o_fb_format;
END IF;
o_hburst<=(o_ihsize * (to_integer(o_format(2 DOWNTO 0)) - 2) +
N_BURST - 1) / N_BURST;
o_ihsize_temp <= o_ihsize * to_integer(o_format(2 DOWNTO 0) - 2);
o_ihsize_temp2 <= (o_ihsize_temp + N_BURST - 1);
o_hburst <= o_ihsize_temp2 / N_BURST;
IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN
o_obuf0<=buf_next(o_obuf0,o_ibuf0);
@ -2044,9 +2050,10 @@ BEGIN
END IF;
END PROCESS;
o_fb_pal_dr<=
pal_mem(to_integer(shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7)))
WHEN rising_edge(o_clk);
pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7);
pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk);
o_fb_pal_dr_x2 <= pal_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk);
o_fb_pal_dr <= o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0);
END GENERATE GenPal;
GenNoPal:IF NOT PALETTE GENERATE

22
sys/build_id.tcl
View File

@ -1,25 +1,29 @@
# Build TimeStamp Verilog Module
# Jeff Wiencrot - 8/1/2011
# Sorgelig - 02/11/2019
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\""
# Create a Verilog file for output
set outputFileName "build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
set fileData ""
if { [file exists $outputFileName]} {
set outputFile [open $outputFileName "r"]
set fileData [read $outputFile]
close $outputFile
}
if {$buildDate ne $fileData} {
set outputFile [open $outputFileName "w"]
puts -nonewline $outputFile $buildDate
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
post_message "Generated: [pwd]/$outputFileName: $buildDate"
}
}
# Build CDF file

108
sys/ddr_svc.sv Normal file
View File

@ -0,0 +1,108 @@
//
// Copyright (c) 2020 Alexey Melnikov
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ------------------------------------------
//
// 16-bit version
module ddr_svc
(
input clk,
input ram_waitrequest,
output [7:0] ram_burstcnt,
output [28:0] ram_addr,
input [63:0] ram_readdata,
input ram_read_ready,
output reg ram_read,
output [63:0] ram_writedata,
output [7:0] ram_byteenable,
output reg ram_write,
output [7:0] ram_bcnt,
input [31:3] ch0_addr,
input [7:0] ch0_burst,
output [63:0] ch0_data,
input ch0_req,
output ch0_ready,
input [31:3] ch1_addr,
input [7:0] ch1_burst,
output [63:0] ch1_data,
input ch1_req,
output ch1_ready
);
assign ram_burstcnt = ram_burst;
assign ram_byteenable = 8'hFF;
assign ram_addr = ram_address;
assign ram_writedata = 0;
assign ch0_data = ram_q[0];
assign ch1_data = ram_q[1];
assign ch0_ready = ready[0];
assign ch1_ready = ready[1];
reg [7:0] ram_burst;
reg [63:0] ram_q[2];
reg [31:3] ram_address;
reg [1:0] ack = 0;
reg [1:0] ready;
reg state = 0;
reg ch = 0;
always @(posedge clk) begin
ready <= 0;
if(!ram_waitrequest) begin
ram_read <= 0;
ram_write <= 0;
case(state)
0: if(ch0_req != ack[0]) begin
ack[0] <= ch0_req;
ram_address <= ch0_addr;
ram_burst <= ch0_burst;
ram_read <= 1;
ch <= 0;
ram_bcnt <= 8'hFF;
state <= 1;
end
else if(ch1_req != ack[1]) begin
ack[1] <= ch1_req;
ram_address <= ch1_addr;
ram_burst <= ch1_burst;
ram_read <= 1;
ch <= 1;
ram_bcnt <= 8'hFF;
state <= 1;
end
1: begin
if(ram_read_ready) begin
ram_bcnt <= ram_bcnt + 1'd1;
ram_q[ch] <= ram_readdata;
ready[ch] <= 1;
if ((ram_bcnt+2'd2) == ram_burst) state <= 0;
end
end
endcase
end
end
endmodule

86
sys/fbpal.sv
View File

@ -1,86 +0,0 @@
//============================================================================
//
// Framebuffer Palette support for MiSTer
// (c)2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module fbpal
(
input reset,
input en_in,
output reg en_out,
input ram_clk,
output reg [28:0] ram_address,
output reg [7:0] ram_burstcount,
input ram_waitrequest,
input [63:0] ram_readdata,
input ram_readdatavalid,
output reg ram_read,
input [31:0] fb_address,
input pal_en,
output reg [7:0] pal_a,
output reg [23:0] pal_d,
output reg pal_wr
);
reg [31:0] base_addr;
always @(posedge ram_clk) base_addr <= fb_address - 4096;
reg [6:0] buf_rptr = 0;
always @(posedge ram_clk) begin
reg [23:0] odd_d;
if(~pal_a[0] & pal_wr) {pal_a[0], pal_d} <= {1'b1, odd_d};
else pal_wr <= 0;
if(~ram_waitrequest) ram_read <= 0;
if(pal_en & ~reset) begin
if(ram_burstcount) begin
if(ram_readdatavalid) begin
ram_burstcount <= 0;
odd_d <= ram_readdata[55:32];
pal_d <= ram_readdata[23:0];
pal_a <= {buf_rptr, 1'b0};
pal_wr <= 1;
en_out <= en_in;
buf_rptr <= buf_rptr + 1'd1;
end
end
else begin
if(~ram_waitrequest && en_out != en_in) begin
ram_address <= base_addr[31:3] + buf_rptr;
ram_burstcount <= 1;
ram_read <= 1;
end
end
end
else begin
en_out <= en_in;
buf_rptr <= 0;
ram_burstcount <= 0;
end
end
endmodule

122
sys/gamma_corr.sv Normal file
View File

@ -0,0 +1,122 @@
module gamma_corr
(
input clk_sys,
input clk_vid,
input ce_pix,
input gamma_en,
input gamma_wr,
input [9:0] gamma_wr_addr,
input [7:0] gamma_value,
input HSync,
input VSync,
input HBlank,
input VBlank,
input [23:0] RGB_in,
output reg HSync_out,
output reg VSync_out,
output reg HBlank_out,
output reg VBlank_out,
output reg [23:0] RGB_out
);
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve[768];
always @(posedge clk_sys) if (gamma_wr) gamma_curve[gamma_wr_addr] <= gamma_value;
always @(posedge clk_vid) gamma <= gamma_curve[gamma_index];
reg [9:0] gamma_index;
reg [7:0] gamma;
always @(posedge clk_vid) begin
reg [7:0] R_in, G_in, B_in;
reg [7:0] R_gamma, G_gamma;
reg hs,vs,hb,vb;
reg [1:0] ctr = 0;
if(ce_pix) begin
{R_in,G_in,B_in} <= RGB_in;
hs <= HSync; vs <= VSync;
hb <= HBlank; vb <= VBlank;
RGB_out <= gamma_en ? {R_gamma,G_gamma,gamma} : {R_in,G_in,B_in};
HSync_out <= hs; VSync_out <= vs;
HBlank_out <= hb; VBlank_out <= vb;
ctr <= 1;
gamma_index <= {2'b00,RGB_in[23:16]};
end
if (|ctr) ctr <= ctr + 1'd1;
case(ctr)
1: begin gamma_index <= {2'b01,G_in}; end
2: begin R_gamma <= gamma; gamma_index <= {2'b10,B_in}; end
3: begin G_gamma <= gamma; end
endcase
end
endmodule
module gamma_fast
(
input clk_vid,
input ce_pix,
inout [21:0] gamma_bus,
input HSync,
input VSync,
input HBlank,
input VBlank,
input DE,
input [23:0] RGB_in,
output reg HSync_out,
output reg VSync_out,
output reg HBlank_out,
output reg VBlank_out,
output reg DE_out,
output reg [23:0] RGB_out
);
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_r[256];
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_g[256];
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_b[256];
assign gamma_bus[21] = 1;
wire clk_sys = gamma_bus[20];
wire gamma_en = gamma_bus[19];
wire gamma_wr = gamma_bus[18];
wire [9:0] gamma_wr_addr = gamma_bus[17:8];
wire [7:0] gamma_value = gamma_bus[7:0];
always @(posedge clk_sys) if (gamma_wr) begin
case(gamma_wr_addr[9:8])
0: gamma_curve_r[gamma_wr_addr[7:0]] <= gamma_value;
1: gamma_curve_g[gamma_wr_addr[7:0]] <= gamma_value;
2: gamma_curve_b[gamma_wr_addr[7:0]] <= gamma_value;
endcase
end
reg [7:0] gamma_index_r,gamma_index_g,gamma_index_b;
always @(posedge clk_vid) begin
reg [7:0] R_in, G_in, B_in;
reg [7:0] R_gamma, G_gamma;
reg hs,vs,hb,vb,de;
if(ce_pix) begin
{gamma_index_r,gamma_index_g,gamma_index_b} <= RGB_in;
hs <= HSync; vs <= VSync;
hb <= HBlank; vb <= VBlank;
de <= DE;
RGB_out <= gamma_en ? {gamma_curve_r[gamma_index_r],gamma_curve_g[gamma_index_g],gamma_curve_b[gamma_index_b]}
: {gamma_index_r,gamma_index_g,gamma_index_b};
HSync_out <= hs; VSync_out <= vs;
HBlank_out <= hb; VBlank_out <= vb;
DE_out <= de;
end
end
endmodule

476
sys/hps_io.v
View File

@ -2,7 +2,7 @@
// hps_io.v
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017-2019 Alexey Melnikov
// Copyright (c) 2017-2020 Alexey Melnikov
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
@ -18,14 +18,11 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
// altera message_off 10665
//
// Use buffer to access SD card. It's time-critical part.
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = CLK_SYS/(PS2DIV*2)
//
// WIDE=1 for 16 bit file I/O
// VDNUM 1-4
module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
@ -36,12 +33,15 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// buttons up to 32
output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
output reg [31:0] joystick_2,
output reg [31:0] joystick_3,
output reg [31:0] joystick_4,
output reg [31:0] joystick_5,
// analog -127..+127, Y: [15:8], X: [7:0]
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output reg [15:0] joystick_analog_2,
@ -49,14 +49,34 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
output reg [15:0] joystick_analog_4,
output reg [15:0] joystick_analog_5,
// paddle 0..255
output reg [7:0] paddle_0,
output reg [7:0] paddle_1,
output reg [7:0] paddle_2,
output reg [7:0] paddle_3,
output reg [7:0] paddle_4,
output reg [7:0] paddle_5,
// spinner [7:0] -128..+127, [8] - toggle with every update
output reg [8:0] spinner_0,
output reg [8:0] spinner_1,
output reg [8:0] spinner_2,
output reg [8:0] spinner_3,
output reg [8:0] spinner_4,
output reg [8:0] spinner_5,
output [1:0] buttons,
output forced_scandoubler,
output direct_video,
output reg [31:0] status,
input [31:0] status_in,
output reg [63:0] status,
input [63:0] status_in,
input status_set,
input [15:0] status_menumask,
input info_req,
input [7:0] info,
//toggle to force notify of video mode change
input new_vmode,
@ -126,31 +146,42 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0,
output reg [15:0] ps2_mouse_ext = 0 // 15:8 - reserved(additional buttons), 7:0 - wheel movements
output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
inout [21:0] gamma_bus,
// for core-specific extensions
inout [35:0] EXT_BUS
);
assign EXT_BUS[31:16] = HPS_BUS[31:16];
assign EXT_BUS[35:33] = HPS_BUS[35:33];
localparam MAX_W = $clog2((512 > (STRLEN+1)) ? 512 : (STRLEN+1))-1;
localparam DW = (WIDE) ? 15 : 7;
localparam AW = (WIDE) ? 7 : 8;
localparam VD = VDNUM-1;
wire io_wait = ioctl_wait;
wire io_enable= |HPS_BUS[35:34];
wire io_strobe= HPS_BUS[33];
wire io_enable= HPS_BUS[34];
wire fp_enable= HPS_BUS[35];
wire io_wide = (WIDE) ? 1'b1 : 1'b0;
wire [15:0] io_din = HPS_BUS[31:16];
reg [15:0] io_dout;
assign HPS_BUS[37] = io_wait;
assign HPS_BUS[37] = ioctl_wait;
assign HPS_BUS[36] = clk_sys;
assign HPS_BUS[32] = io_wide;
assign HPS_BUS[15:0] = io_dout;
assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : io_dout;
reg [7:0] cfg;
reg [15:0] cfg;
assign buttons = cfg[1:0];
//cfg[2] - vga_scaler handled in sys_top
//cfg[3] - csync handled in sys_top
assign forced_scandoubler = cfg[4];
//cfg[5] - ypbpr handled in sys_top
assign direct_video = cfg[10];
// command byte read by the io controller
wire [15:0] sd_cmd =
@ -169,129 +200,51 @@ wire [15:0] sd_cmd =
sd_rd[0]
};
///////////////// calc video parameters //////////////////
/////////////////////////////////////////////////////////
wire clk_100 = HPS_BUS[43];
wire clk_vid = HPS_BUS[42];
wire ce_pix = HPS_BUS[41];
wire de = HPS_BUS[40];
wire hs = HPS_BUS[39];
wire vs = HPS_BUS[38];
wire vs_hdmi = HPS_BUS[44];
wire f1 = HPS_BUS[45];
reg [31:0] vid_hcnt = 0;
reg [31:0] vid_vcnt = 0;
reg [7:0] vid_nres = 0;
reg [1:0] vid_int = 0;
integer hcnt;
always @(posedge clk_vid) begin
integer vcnt;
reg old_vs= 0, old_de = 0, old_vmode = 0;
reg [3:0] resto = 0;
reg calch = 0;
if(ce_pix) begin
old_vs <= vs;
old_de <= de;
if(~vs & ~old_de & de) vcnt <= vcnt + 1;
if(calch & de) hcnt <= hcnt + 1;
if(old_de & ~de) calch <= 0;
if(old_vs & ~vs) begin
vid_int <= {vid_int[0],f1};
if(~f1) begin
if(hcnt && vcnt) begin
old_vmode <= new_vmode;
//report new resolution after timeout
if(resto) resto <= resto + 1'd1;
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) resto <= 1;
if(&resto) vid_nres <= vid_nres + 1'd1;
vid_hcnt <= hcnt;
vid_vcnt <= vcnt;
end
vcnt <= 0;
hcnt <= 0;
calch <= 1;
end
end
end
end
reg [31:0] vid_htime = 0;
reg [31:0] vid_vtime = 0;
reg [31:0] vid_pix = 0;
always @(posedge clk_100) begin
integer vtime, htime, hcnt;
reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
reg calch = 0;
old_vs <= vs;
old_hs <= hs;
old_vs2 <= old_vs;
old_hs2 <= old_hs;
vtime <= vtime + 1'd1;
htime <= htime + 1'd1;
if(~old_vs2 & old_vs) begin
vid_pix <= hcnt;
vid_vtime <= vtime;
vtime <= 0;
hcnt <= 0;
end
if(old_vs2 & ~old_vs) calch <= 1;
if(~old_hs2 & old_hs) begin
vid_htime <= htime;
htime <= 0;
end
old_de <= de;
old_de2 <= old_de;
if(calch & old_de) hcnt <= hcnt + 1;
if(old_de2 & ~old_de) calch <= 0;
end
reg [31:0] vid_vtime_hdmi;
always @(posedge clk_100) begin
integer vtime;
reg old_vs, old_vs2;
old_vs <= vs_hdmi;
old_vs2 <= old_vs;
vtime <= vtime + 1'd1;
if(~old_vs2 & old_vs) begin
vid_vtime_hdmi <= vtime;
vtime <= 0;
end
end
wire [15:0] vc_dout;
video_calc video_calc
(
.clk_100(HPS_BUS[43]),
.clk_vid(HPS_BUS[42]),
.clk_sys(clk_sys),
.ce_pix(HPS_BUS[41]),
.de(HPS_BUS[40]),
.hs(HPS_BUS[39]),
.vs(HPS_BUS[38]),
.vs_hdmi(HPS_BUS[44]),
.f1(HPS_BUS[45]),
.new_vmode(new_vmode),
.par_num(byte_cnt[3:0]),
.dout(vc_dout)
);
/////////////////////////////////////////////////////////
assign gamma_bus[20:0] = {clk_sys, gamma_en, gamma_wr, gamma_wr_addr, gamma_value};
reg gamma_en;
reg gamma_wr;
reg [9:0] gamma_wr_addr;
reg [7:0] gamma_value;
reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
reg [MAX_W:0] byte_cnt;
always@(posedge clk_sys) begin
reg [15:0] cmd;
reg [9:0] byte_cnt; // counts bytes
reg [2:0] b_wr;
reg [2:0] stick_idx;
reg [3:0] stick_idx;
reg [3:0] pdsp_idx;
reg ps2skip = 0;
reg [3:0] stflg = 0;
reg [31:0] status_req;
reg [63:0] status_req;
reg old_status_set = 0;
reg old_info = 0;
reg [7:0] info_n = 0;
old_status_set <= status_set;
if(~old_status_set & status_set) begin
@ -299,12 +252,17 @@ always@(posedge clk_sys) begin
status_req <= status_in;
end
old_info <= info_req;
if(~old_info & info_req) info_n <= info;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
if(PS2DIV) {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
gamma_wr <= 0;
if(~io_enable) begin
if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5 && !ps2skip) begin
@ -321,8 +279,8 @@ always@(posedge clk_sys) begin
sd_ack_conf <= 0;
io_dout <= 0;
ps2skip <= 0;
end else begin
if(io_strobe) begin
end
else if(io_strobe) begin
io_dout <= 0;
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
@ -337,6 +295,8 @@ always@(posedge clk_sys) begin
'h29: io_dout <= {4'hA, stflg};
'h2B: io_dout <= 1;
'h2F: io_dout <= 1;
'h32: io_dout <= gamma_bus[21];
'h36: begin io_dout <= info_n; info_n <= 0; end
endcase
sd_buff_addr <= 0;
@ -346,7 +306,7 @@ always@(posedge clk_sys) begin
case(cmd)
// buttons and switches
'h01: cfg <= io_din[7:0];
'h01: cfg <= io_din;
'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
@ -361,13 +321,13 @@ always@(posedge clk_sys) begin
mouse_we <= 1;
end
if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) begin
case(byte_cnt)
if(~&io_din[15:8] && ~ps2skip && !byte_cnt[MAX_W:2]) begin
case(byte_cnt[1:0])
1: ps2_mouse[7:0] <= io_din[7:0];
2: ps2_mouse[15:8] <= io_din[7:0];
3: ps2_mouse[23:16] <= io_din[7:0];
endcase
case(byte_cnt)
case(byte_cnt[1:0])
1: ps2_mouse_ext[7:0] <= {io_din[14], io_din[14:8]};
2: ps2_mouse_ext[11:8] <= io_din[11:8];
3: ps2_mouse_ext[15:12]<= io_din[11:8];
@ -389,12 +349,14 @@ always@(posedge clk_sys) begin
'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
// reading sd card status
'h16: case(byte_cnt)
'h16: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: io_dout <= sd_cmd;
2: io_dout <= sd_lba[15:0];
3: io_dout <= sd_lba[31:16];
4: io_dout <= sd_req_type;
endcase
end
// send SD config IO -> FPGA
// flag that download begins
@ -415,8 +377,9 @@ always@(posedge clk_sys) begin
end
// joystick analog
'h1a: case(byte_cnt)
1: stick_idx <= io_din[2:0]; // first byte is joystick index
'h1a: if(!byte_cnt[MAX_W:2]) begin
case(byte_cnt[1:0])
1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index
2: case(stick_idx)
0: joystick_analog_0 <= io_din;
1: joystick_analog_1 <= io_din;
@ -424,8 +387,23 @@ always@(posedge clk_sys) begin
3: joystick_analog_3 <= io_din;
4: joystick_analog_4 <= io_din;
5: joystick_analog_5 <= io_din;
15: case(pdsp_idx)
0: paddle_0 <= io_din[7:0];
1: paddle_1 <= io_din[7:0];
2: paddle_2 <= io_din[7:0];
3: paddle_3 <= io_din[7:0];
4: paddle_4 <= io_din[7:0];
5: paddle_5 <= io_din[7:0];
8: spinner_0 <= {~spinner_0[8],io_din[7:0]};
9: spinner_1 <= {~spinner_1[8],io_din[7:0]};
10: spinner_2 <= {~spinner_2[8],io_din[7:0]};
11: spinner_3 <= {~spinner_3[8],io_din[7:0]};
12: spinner_4 <= {~spinner_4[8],io_din[7:0]};
13: spinner_5 <= {~spinner_5[8],io_din[7:0]};
endcase
endcase
endcase
end
// notify image selection
'h1c: begin
@ -436,9 +414,15 @@ always@(posedge clk_sys) begin
// send image info
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
// status, 32bit version
'h1e: if(byte_cnt==1) status[15:0] <= io_din;
else if(byte_cnt==2) status[31:16] <= io_din;
// status, 64bit version
'h1e: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: status[15:00] <= io_din;
2: status[31:16] <= io_din;
3: status[47:32] <= io_din;
4: status[63:48] <= io_din;
endcase
end
// reading keyboard LED status
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
@ -460,21 +444,7 @@ always@(posedge clk_sys) begin
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//Video res.
'h23: case(byte_cnt)
1: io_dout <= {|vid_int, vid_nres};
2: io_dout <= vid_hcnt[15:0];
3: io_dout <= vid_hcnt[31:16];
4: io_dout <= vid_vcnt[15:0];
5: io_dout <= vid_vcnt[31:16];
6: io_dout <= vid_htime[15:0];
7: io_dout <= vid_htime[31:16];
8: io_dout <= vid_vtime[15:0];
9: io_dout <= vid_vtime[31:16];
10: io_dout <= vid_pix[15:0];
11: io_dout <= vid_pix[31:16];
12: io_dout <= vid_vtime_hdmi[15:0];
13: io_dout <= vid_vtime_hdmi[31:16];
endcase
'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
//RTC
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
@ -483,18 +453,29 @@ always@(posedge clk_sys) begin
'h28: io_dout <= uart_mode;
//status set
'h29: case(byte_cnt)
1: io_dout <= status_req[15:0];
'h29: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: io_dout <= status_req[15:00];
2: io_dout <= status_req[31:16];
3: io_dout <= status_req[47:32];
4: io_dout <= status_req[63:48];
endcase
end
//menu mask
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
//sdram size set
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
endcase
// Gamma
'h32: gamma_en <= io_din[0];
'h33: begin
gamma_wr_addr <= {(byte_cnt[1:0]-1'b1),io_din[15:8]};
{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
if (byte_cnt[1:0] == 3) byte_cnt <= 1;
end
endcase
end
end
end
@ -504,7 +485,7 @@ end
generate
if(PS2DIV) begin
reg clk_ps2;
always @(negedge clk_sys) begin
always @(posedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
@ -584,7 +565,7 @@ always@(posedge clk_sys) begin
ioctl_wr <= wr;
wr <= 0;
if(~io_enable) has_cmd <= 0;
if(~fp_enable) has_cmd <= 0;
else begin
if(io_strobe) begin
@ -777,89 +758,138 @@ end
endmodule
//
// Phase shift helper module for better 64MB/128MB modules support.
//
// Copyright (c) 2019 Alexey Melnikov
//
module phase_shift #(parameter M32MB=0, M64MB=0, M128MB=0)
///////////////// calc video parameters //////////////////
module video_calc
(
input reset,
input clk_100,
input clk_vid,
input clk_sys,
input clk,
input pll_locked,
input ce_pix,
input de,
input hs,
input vs,
input vs_hdmi,
input f1,
input new_vmode,
output reg phase_en,
output reg updn,
input phase_done,
input [15:0] sdram_sz,
output reg ready
input [3:0] par_num,
output reg [15:0] dout
);
localparam ph32 = ($signed(M32MB ) >= 0) ? M32MB : (0 - M32MB);
localparam ph64 = ($signed(M64MB ) >= 0) ? M64MB : (0 - M64MB);
localparam ph128 = ($signed(M128MB) >= 0) ? M128MB : (0 - M128MB);
localparam up32 = ($signed(M32MB ) >= 0) ? 1'b1 : 1'b0;
localparam up64 = ($signed(M64MB ) >= 0) ? 1'b1 : 1'b0;
localparam up128 = ($signed(M128MB) >= 0) ? 1'b1 : 1'b0;
always @(posedge clk, posedge reset) begin
reg [2:0] state = 0;
reg [7:0] cnt;
reg [8:0] ph;
if(reset) begin
state <= 0;
ready <= 0;
end
else begin
case(state)
0: begin
ready <= 0;
if(pll_locked) state <= state + 1'd1;
end
1: if(sdram_sz[15]) begin
cnt <= 0;
if(sdram_sz[14]) ph <= sdram_sz[8:0];
else begin
case(sdram_sz[1:0])
0: ph <= 0;
1: ph <= {up32[0],ph32[7:0]};
2: ph <= {up64[0],ph64[7:0]};
3: ph <= {up128[0],ph128[7:0]};
always @(posedge clk_sys) begin
case(par_num)
1: dout <= {|vid_int, vid_nres};
2: dout <= vid_hcnt[15:0];
3: dout <= vid_hcnt[31:16];
4: dout <= vid_vcnt[15:0];
5: dout <= vid_vcnt[31:16];
6: dout <= vid_htime[15:0];
7: dout <= vid_htime[31:16];
8: dout <= vid_vtime[15:0];
9: dout <= vid_vtime[31:16];
10: dout <= vid_pix[15:0];
11: dout <= vid_pix[31:16];
12: dout <= vid_vtime_hdmi[15:0];
13: dout <= vid_vtime_hdmi[31:16];
default dout <= 0;
endcase
end
reg [31:0] vid_hcnt = 0;
reg [31:0] vid_vcnt = 0;
reg [7:0] vid_nres = 0;
reg [1:0] vid_int = 0;
always @(posedge clk_vid) begin
integer hcnt;
integer vcnt;
reg old_vs= 0, old_de = 0, old_vmode = 0;
reg [3:0] resto = 0;
reg calch = 0;
if(ce_pix) begin
old_vs <= vs;
old_de <= de;
if(~vs & ~old_de & de) vcnt <= vcnt + 1;
if(calch & de) hcnt <= hcnt + 1;
if(old_de & ~de) calch <= 0;
if(old_vs & ~vs) begin
vid_int <= {vid_int[0],f1};
if(~f1) begin
if(hcnt && vcnt) begin
old_vmode <= new_vmode;
//report new resolution after timeout
if(resto) resto <= resto + 1'd1;
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) resto <= 1;
if(&resto) vid_nres <= vid_nres + 1'd1;
vid_hcnt <= hcnt;
vid_vcnt <= vcnt;
end
state <= state + 1'd1;
vcnt <= 0;
hcnt <= 0;
calch <= 1;
end
2: if(ph[7:0]) begin
ph[7:0] <= ph[7:0] - 1'd1;
updn <= ph[8];
state <= state + 1'd1;
end
else begin
state <= 6;
end
3: begin
phase_en <= 1;
state <= state + 1'd1;
end
reg [31:0] vid_htime = 0;
reg [31:0] vid_vtime = 0;
reg [31:0] vid_pix = 0;
always @(posedge clk_100) begin
integer vtime, htime, hcnt;
reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2;
reg calch = 0;
old_vs <= vs;
old_hs <= hs;
old_vs2 <= old_vs;
old_hs2 <= old_hs;
vtime <= vtime + 1'd1;
htime <= htime + 1'd1;
if(~old_vs2 & old_vs) begin
vid_pix <= hcnt;
vid_vtime <= vtime;
vtime <= 0;
hcnt <= 0;
end
4: if(~phase_done) begin
phase_en <= 0;
state <= state + 1'd1;
if(old_vs2 & ~old_vs) calch <= 1;
if(~old_hs2 & old_hs) begin
vid_htime <= htime;
htime <= 0;
end
5: if(phase_done) begin
cnt <= cnt + 1'd1;
if(cnt == ph[7:0]) state <= state + 1'd1;
else state <= 3;
end
6: begin
ready <= 1;
if(!sdram_sz[15]) state <= 0;
end
endcase
old_de <= de;
old_de2 <= old_de;
if(calch & old_de) hcnt <= hcnt + 1;
if(old_de2 & ~old_de) calch <= 0;
end
reg [31:0] vid_vtime_hdmi;
always @(posedge clk_100) begin
integer vtime;
reg old_vs, old_vs2;
old_vs <= vs_hdmi;
old_vs2 <= old_vs;
vtime <= vtime + 1'd1;
if(~old_vs2 & old_vs) begin
vid_vtime_hdmi <= vtime;
vtime <= 0;
end
end

210
sys/hq2x.sv
View File

@ -8,9 +8,7 @@
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
// altera message_off 10030
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
@ -34,7 +32,9 @@ localparam AWIDTH = $clog2(LENGTH)-1;
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
localparam DWIDTH1 = DWIDTH+1;
wire [5:0] hqTable[256] = '{
(* romstyle = "MLAB" *) reg [5:0] hqTable[256];
initial begin
hqTable = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
@ -51,7 +51,10 @@ wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
};
end
wire [5:0] hqrule = hqTable[nextpatt];
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
reg [23:0] A, B, D, F, G, H;
@ -70,7 +73,7 @@ wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
wire [23:0] blend_result_pre;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result_pre);
Blend blender(clk, ce_in, disable_hq2x ? 6'd0 : hqrule, Curr0, X, B, D, F, H, blend_result_pre);
wire [DWIDTH:0] Curr20tmp;
wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
@ -146,12 +149,28 @@ reg [AWIDTH:0] offs;
always @(posedge clk) begin
reg old_reset_line;
reg old_reset_frame;
reg [3:0] wrdata_finished;
reg [AWIDTH+1:0] waddr;
wrout_en <= 0;
wrin_en <= 0;
if(ce_in) begin
// blend_result has been delayed by 4 cycles
case(cyc)
0: wrdata[DWIDTH:0] <= blend_result;
1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
endcase
wrdata_finished <= wrdata_finished << 1;
if(wrdata_finished[3]) begin
wrout_en <= 1;
wrout_addr <= waddr;
end
if(~&offs) begin
if (cyc == 1) begin
Prev2 <= Curr20;
@ -162,17 +181,10 @@ always @(posedge clk) begin
wrin_en <= 1;
end
case({cyc[1],^cyc})
0: wrdata[DWIDTH:0] <= blend_result;
1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
2: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
3: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
endcase
if(cyc==3) begin
offs <= offs + 1'd1;
wrout_addr <= {offs, curbuf};
wrout_en <= 1;
waddr <= {offs, curbuf};
wrdata_finished[0] <= 1;
end
end
@ -225,13 +237,14 @@ module hq2x_in #(parameter LENGTH, parameter DWIDTH)
input wren
);
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
@ -241,10 +254,10 @@ module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output logic [DWIDTH:0] q
output reg [DWIDTH:0] q
);
logic [DWIDTH:0] ram[0:NUMWORDS-1];
reg [DWIDTH:0] ram[0:NUMWORDS-1];
always_ff@(posedge clock) begin
if(wren) ram[wraddress] <= data;
@ -266,8 +279,7 @@ module DiffCheck
wire [7:0] g = rgb1[15:9] - rgb2[15:9];
wire [7:0] b = rgb1[23:17] - rgb2[23:17];
wire [8:0] t = $signed(r) + $signed(b);
wire [8:0] gx = {g[7], g};
wire [9:0] y = $signed(t) + $signed(gx);
wire [9:0] y = $signed(t) + $signed({g[7], g});
wire [8:0] u = $signed(r) - $signed(b);
wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
@ -275,48 +287,19 @@ module DiffCheck
wire y_inside = (y < 10'h60 || y >= 10'h3a0);
// if u is inside (-16, 16)
wire u_inside = (u < 9'h10 || u >= 9'h1f0);
wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0);
// if v is inside (-24, 24)
wire v_inside = (v < 10'h18 || v >= 10'h3e8);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [7:0] A,
input [7:0] B,
input [7:0] C,
output [7:0] O
);
function [10:0] mul8x3;
input [7:0] op1;
input [2:0] op2;
begin
mul8x3 = 11'd0;
if(op2[0]) mul8x3 = mul8x3 + op1;
if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [10:0] Amul = mul8x3(A, Op[7:5]);
wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0});
wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0});
wire [10:0] At = Amul;
wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [11:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[11:4];
endmodule
module Blend
(
input clk,
input clk_en,
input [5:0] rule,
input disable_hq2x,
input [23:0] E,
input [23:0] A,
input [23:0] B,
@ -326,66 +309,63 @@ module Blend
output [23:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4
localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4
localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = {11{1'bx}};
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
reg [23:0] a,b,d,e,h,f;
reg [3:0] bl_rule;
reg [1:0] df_rule;
always @(posedge clk) if (clk_en) begin
{bl_rule,df_rule} <= rule;
a <= A; b <= B; d <= D; e <= E; f <= F; h <= H;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [23:0] Input1 = E;
wire [23:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire is_diff;
DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff);
reg [23:0] i10,i20,i30;
reg [6:0] op0;
always @(posedge clk) if (clk_en) begin
i10 <= e;
case({!is_diff, bl_rule})
1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0};
2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0};
3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0};
4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b};
5,21: {op0, i20, i30} <= {BLEND2, a, b};
6,22: {op0, i20, i30} <= {BLEND2, a, d};
25,29: {op0, i20, i30} <= {BLEND5, d, b};
26: {op0, i20, i30} <= {BLEND6, d, b};
28: {op0, i20, i30} <= {BLEND4, d, b};
30: {op0, i20, i30} <= {BLEND3, b, d};
31: {op0, i20, i30} <= {BLEND3, d, b};
default: {op0, i20, i30} <= {BLEND1, e, 24'd0};
endcase
end
reg [23:0] i1,i2,i3;
reg [6:0] op;
always @(posedge clk) if (clk_en) begin
op <= op0; i1 <= i10; i2 <= i20; i3 <= i30;
end
function [34:0] mul24x3;
input [23:0] op1;
input [2:0] op2;
begin
mul24x3 = 0;
if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]};
if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0};
if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00};
end
endfunction
wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]});
always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]};
wire [23:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]);
InnerBlend inner_blend2(op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]);
InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]);
endmodule

123
sys/osd.v
View File

@ -22,27 +22,29 @@ module osd
);
parameter OSD_COLOR = 3'd4;
parameter OSD_X_OFFSET = 12'd0;
parameter OSD_Y_OFFSET = 12'd0;
localparam OSD_WIDTH = 12'd256;
localparam OSD_HEIGHT = 12'd64;
`ifdef OSD_HEADER
localparam OSD_HDR = 12'd32;
localparam OSD_HDR = 12'd24;
`else
localparam OSD_HDR = 12'd0;
`endif
reg osd_enable;
reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096];
(* ramstyle="no_rw_check" *) reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096];
reg info = 0;
reg [8:0] infoh;
reg [8:0] infow;
reg [11:0] infox;
reg [21:0] infox;
reg [21:0] infoy;
reg [21:0] hrheight;
reg [21:0] osd_h;
reg [21:0] osd_t;
reg [21:0] osd_w;
reg [1:0] rot = 0;
always@(posedge clk_sys) begin
reg [12:0] bcnt;
@ -51,7 +53,9 @@ always@(posedge clk_sys) begin
reg old_strobe;
reg highres = 0;
hrheight <= info ? infoh : ((OSD_HEIGHT<<highres)+OSD_HDR);
osd_t <= rot[0] ? OSD_WIDTH : (OSD_HEIGHT<<1);
osd_h <= rot[0] ? (info ? infow : OSD_WIDTH) : info ? infoh : (OSD_HEIGHT<<highres);
osd_w <= rot[0] ? (info ? infoh : (OSD_HEIGHT<<highres)) : (info ? infow : OSD_WIDTH);
old_strobe <= io_strobe;
@ -83,6 +87,7 @@ always@(posedge clk_sys) begin
if(bcnt == 1) infoy <= io_din[11:0];
if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
if(bcnt == 4) rot <= io_din[1:0];
end
// command 0x20: OSDCMDWRITE
@ -95,22 +100,22 @@ always@(posedge clk_sys) begin
end
(* direct_enable *) reg ce_pix;
always @(negedge clk_video) begin
integer cnt = 0;
integer pixsz, pixcnt;
always @(posedge clk_video) begin
reg [21:0] cnt = 0;
reg [21:0] pixsz, pixcnt;
reg deD;
cnt <= cnt + 1;
cnt <= cnt + 1'd1;
deD <= de_in;
pixcnt <= pixcnt + 1;
pixcnt <= pixcnt + 1'd1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(~deD && de_in) cnt <= 0;
if(deD && ~de_in) begin
pixsz <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
pixsz <= (((cnt+1'b1) >> (9-rot[0])) > 1) ? (((cnt+1'b1) >> (9-rot[0])) - 1'd1) : 22'd0;
pixcnt <= 0;
end
end
@ -118,26 +123,39 @@ end
reg [2:0] osd_de;
reg osd_pixel;
reg [21:0] v_cnt;
reg v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4;
reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5;
reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5;
reg v_cnt_below320, v_cnt_below640, v_cnt_below960;
reg [21:0] v_osd_start_320, v_osd_start_640, v_osd_start_960, v_osd_start_other;
wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
// pipeline the comparisons a bit
always @(posedge clk_video) if(ce_pix) begin
v_cnt_below320 <= v_cnt < 320;
v_cnt_below640 <= v_cnt < 640;
v_cnt_below960 <= v_cnt < 960;
v_osd_start_320 <= ((v_cnt-hrheight)>>1) + OSD_Y_OFFSET;
v_osd_start_640 <= ((v_cnt-(hrheight<<1))>>1) + OSD_Y_OFFSET;
v_osd_start_960 <= ((v_cnt-(hrheight + (hrheight<<1)))>>1) + OSD_Y_OFFSET;
v_osd_start_other <= ((v_cnt-(hrheight<<2))>>1) + OSD_Y_OFFSET;
v_cnt_h <= v_cnt < osd_t;
v_cnt_1 <= v_cnt < 320;
v_cnt_2 <= v_cnt < 640;
v_cnt_3 <= v_cnt < 960;
v_cnt_4 <= v_cnt < 1280;
v_osd_start_h <= (v_cnt-(osd_h_hdr>>1))>>1;
v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1;
v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1;
v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1;
v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1;
v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1;
v_info_start_h <= rot[0] ? infox : infoy;
v_info_start_1 <= rot[0] ? infox : infoy;
v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1);
v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1));
v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2);
v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2));
end
always @(posedge clk_video) begin
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg [2:0] osd_div;
reg [2:0] multiscan;
reg [7:0] osd_byte;
reg [23:0] h_cnt;
reg [21:0] dsp_width;
@ -145,9 +163,11 @@ always @(posedge clk_video) begin
reg [21:0] h_osd_start;
reg [21:0] v_osd_start;
reg [21:0] osd_hcnt;
reg [21:0] osd_hcnt2;
reg osd_de1,osd_de2;
reg [1:0] osd_en;
reg f1;
reg half;
if(ce_pix) begin
@ -155,12 +175,19 @@ always @(posedge clk_video) begin
if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
if(~&osd_hcnt2) osd_hcnt2 <= osd_hcnt2 + 1'd1;
if (h_cnt == h_osd_start) begin
osd_de[0] <= osd_en[1] && hrheight && (info ? (osd_vcnt < hrheight) :
(!osd_vcnt[11:7] || (osd_vcnt[11] && osd_vcnt[7] && (osd_vcnt[6:0] >= 4) && (osd_vcnt[6:0] < 19))));
osd_de[0] <= osd_en[1] && osd_h && (
osd_vcnt[11] ? (osd_vcnt[7] && (osd_vcnt[6:0] >= 4) && (osd_vcnt[6:0] < 19)) :
(info && (rot == 3)) ? !osd_vcnt[21:8] :
(osd_vcnt < osd_h)
);
osd_hcnt <= 0;
osd_hcnt2 <= 0;
if(info && rot == 1) osd_hcnt2 <= 22'd128-infoh;
end
if (osd_hcnt+1 == (info ? infow : OSD_WIDTH)) osd_de[0] <= 0;
if (osd_hcnt+1 == osd_w) osd_de[0] <= 0;
// falling edge of de
if(!de_in && deD) dsp_width <= h_cnt[21:0];
@ -169,7 +196,7 @@ always @(posedge clk_video) begin
if(de_in && !deD) begin
h_cnt <= 0;
v_cnt <= v_cnt + 1'd1;
h_osd_start <= info ? infox : (((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET - 2'd2);
h_osd_start <= info ? (rot[0] ? infoy : infox) : (((dsp_width - osd_w)>>1) - 2'd2);
if(h_cnt > {dsp_width, 2'b00}) begin
v_cnt <= 1;
@ -179,21 +206,31 @@ always @(posedge clk_video) begin
osd_en <= (osd_en << 1) | osd_enable;
if(~osd_enable) osd_en <= 0;
if(v_cnt_below320) begin
half <= 0;
if(v_cnt_h) begin
multiscan <= 0;
v_osd_start <= info ? infoy : v_osd_start_320;
v_osd_start <= info ? v_info_start_h : v_osd_start_h;
half <= 1;
end
else if(v_cnt_below640) begin
else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin
multiscan <= 0;
v_osd_start <= info ? v_info_start_1 : v_osd_start_1;
end
else if(rot[0] ? v_cnt_3 : v_cnt_2) begin
multiscan <= 1;
v_osd_start <= info ? (infoy<<1) : v_osd_start_640;
v_osd_start <= info ? v_info_start_2 : v_osd_start_2;
end
else if(v_cnt_below960) begin
else if(rot[0] ? v_cnt_4 : v_cnt_3) begin
multiscan <= 2;
v_osd_start <= info ? (infoy + (infoy << 1)) : v_osd_start_960;
v_osd_start <= info ? v_info_start_3 : v_osd_start_3;
end
else if(rot[0] | v_cnt_4) begin
multiscan <= 3;
v_osd_start <= info ? v_info_start_4 : v_osd_start_4;
end
else begin
multiscan <= 3;
v_osd_start <= info ? (infoy<<2) : v_osd_start_other;
multiscan <= 4;
v_osd_start <= info ? v_info_start_5 : v_osd_start_5;
end
end
end
@ -201,14 +238,18 @@ always @(posedge clk_video) begin
osd_div <= osd_div + 1'd1;
if(osd_div == multiscan) begin
osd_div <= 0;
if(~osd_vcnt[10]) osd_vcnt <= osd_vcnt + 1'd1;
if(~osd_vcnt[10]) osd_vcnt <= osd_vcnt + 1'd1 + half;
if(osd_vcnt == 'b100010011111 && ~info) osd_vcnt <= 0;
end
if(v_osd_start == v_cnt) {osd_div, osd_vcnt} <= OSD_HDR ? {~info, 3'b000, ~info, 7'b0000000} : 22'd0;
if(v_osd_start == v_cnt) begin
{osd_div,osd_vcnt} <= 0;
if(info && rot == 3) osd_vcnt <= 22'd256-infow;
else if(OSD_HDR && !rot) osd_vcnt <= {~info, 3'b000, ~info, 7'b0000000};
end
end
osd_byte <= osd_buffer[{osd_vcnt[7:3], osd_hcnt[7:0]}];
osd_pixel <= osd_byte[osd_vcnt[2:0]];
osd_byte <= osd_buffer[rot[0] ? ({osd_hcnt2[6:3], osd_vcnt[7:0]} ^ { {4{~rot[1]}}, {8{rot[1]}} }) : {osd_vcnt[7:3], osd_hcnt[7:0]}];
osd_pixel <= osd_byte[rot[0] ? ((osd_hcnt2[2:0]-1'd1) ^ {3{~rot[1]}}) : osd_vcnt[2:0]];
osd_de[2:1] <= osd_de[1:0];
end
end

10
sys/pll.13.qip
View File

@ -4,9 +4,13 @@ set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"]
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1"

4
sys/pll/pll_0002_q13.qip
View File

@ -1,4 +0,0 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

6
sys/pll_hdmi.13.qip
View File

@ -6,7 +6,11 @@ set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"

4
sys/pll_hdmi/pll_hdmi_0002_q13.qip
View File

@ -1,4 +0,0 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

2
sys/pll_q17.qip
View File

@ -1,3 +1,3 @@
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]

12
sys/scandoubler.v
View File

@ -22,7 +22,7 @@
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input clk_vid,
input ce_pix,
output ce_pix_out,
@ -59,7 +59,7 @@ wire [7:0] pc_in = pix_in_cnt + 1'b1;
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
reg ce_x4i, ce_x1i;
always @(negedge clk_sys) begin
always @(posedge clk_vid) begin
reg old_ce, valid, hs;
if(~&pix_len) pix_len <= pl;
@ -94,7 +94,7 @@ end
reg req_line_reset;
reg [DWIDTH:0] r_d, g_d, b_d;
always @(posedge clk_sys) begin
always @(posedge clk_vid) begin
if(ce_x1i) begin
req_line_reset <= hb_in;
r_d <= r_in;
@ -105,7 +105,7 @@ end
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.clk(clk_vid),
.ce_in(ce_x4i),
.inputpixel({b_d,g_d,r_d}),
@ -124,7 +124,7 @@ reg [7:0] pix_out_cnt = 0;
wire [7:0] pc_out = pix_out_cnt + 1'b1;
reg ce_x4o, ce_x2o;
always @(negedge clk_sys) begin
always @(posedge clk_vid) begin
reg hs;
if(~&pix_out_cnt) pix_out_cnt <= pc_out;
@ -148,7 +148,7 @@ reg [1:0] sd_line;
reg [3:0] vbo;
reg [3:0] vso;
reg [8:0] hbo;
always @(posedge clk_sys) begin
always @(posedge clk_vid) begin
reg [31:0] hcnt;
reg [30:0] sd_hcnt;

4
sys/sys.qip
View File

@ -3,12 +3,13 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fbpal.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
@ -20,6 +21,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) l
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]

46
sys/sys.tcl
View File

@ -99,12 +99,9 @@ set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
@ -132,41 +129,17 @@ set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
@ -245,7 +218,6 @@ set_location_assignment PIN_W20 -to SW[3]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
set_location_assignment FRACTIONALPLL_X89_Y1_N0 -to emu:emu|pll:pll|pll_0002:pll_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"

7
sys/sys_dual_sdram.tcl
View File

@ -42,12 +42,9 @@ set_location_assignment PIN_AE17 -to SDRAM2_A[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_n*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_*
set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1"

30
sys/sys_top.sdc
View File

@ -6,11 +6,6 @@ create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
derive_pll_clocks
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
-name HDMI_CLK [get_ports HDMI_TX_CLK]
derive_clock_uncertainty
# Decouple different clock groups (to simplify routing)
@ -22,9 +17,6 @@ set_clock_groups -exclusive \
-group [get_clocks { FPGA_CLK2_50 }] \
-group [get_clocks { FPGA_CLK3_50 }]
set_output_delay -max -clock HDMI_CLK 4.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK 3.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
@ -34,4 +26,26 @@ set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
set_false_path -to {cfg[*]}
set_false_path -from {cfg[*]}
set_false_path -from {VSET[*]}
set_false_path -to {wcalc[*] hcalc[*]}
set_false_path -to {width[*] height[*]}
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
set_false_path -to {*_osd|v_cnt*}
set_false_path -to {*_osd|v_osd_start*}
set_false_path -to {*_osd|v_info_start*}
set_false_path -to {*_osd|h_osd_start*}
set_false_path -from {*_osd|v_osd_start*}
set_false_path -from {*_osd|v_info_start*}
set_false_path -from {*_osd|h_osd_start*}
set_false_path -from {*_osd|rot*}
set_false_path -from {*_osd|dsp_width*}
set_false_path -to {*_osd|half}
set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}

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