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https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
339 lines
6.9 KiB
Verilog
339 lines
6.9 KiB
Verilog
module jt12_syn(
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input rst,
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input clk, // cpu_clk/6 ~ 1.3MHz
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input [7:0] din,
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input [1:0] addr,
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input write,
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input limiter_en,
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output busy,
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output flag_A,
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output flag_B,
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output irq_n,
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// combined output
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output signed [11:0] snd_right,
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output signed [11:0] snd_left,
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output snd_sample,
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// multiplexed output
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output signed [8:0] mux_right,
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output signed [8:0] mux_left,
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output mux_sample
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);
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// Timers
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wire [9:0] value_A;
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wire [7:0] value_B;
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wire load_A, load_B;
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wire enable_irq_A, enable_irq_B;
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wire clr_flag_A, clr_flag_B;
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wire overflow_A;
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wire fast_timers;
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wire zero; // Single-clock pulse at the begginig of s1_enters
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// LFO
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wire [2:0] lfo_freq;
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wire lfo_en;
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// Operators
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wire amsen_VII;
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wire [ 2:0] dt1_II;
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wire [ 3:0] mul_V;
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wire [ 6:0] tl_VII;
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wire [4:0] keycode_III;
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wire [ 4:0] ar_II;
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wire [ 4:0] d1r_II;
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wire [ 4:0] d2r_II;
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wire [ 3:0] rr_II;
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wire [ 3:0] d1l;
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wire [ 1:0] ks_III;
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// SSG operation
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wire ssg_en_II;
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wire [2:0] ssg_eg_II;
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// envelope operation
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wire keyon_II;
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wire [9:0] eg_IX;
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wire pg_rst_III;
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// Channel
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wire [10:0] fnum_I;
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wire [ 2:0] block_I;
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wire [ 1:0] rl;
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wire [ 2:0] fb_II;
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wire [ 2:0] alg;
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wire [ 2:0] pms;
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wire [ 1:0] ams_VII;
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// PCM
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wire pcm_en;
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wire [ 8:0] pcm;
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// Test
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wire pg_stop, eg_stop;
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wire ch6op;
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// Operator
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wire use_internal_x, use_internal_y;
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wire use_prevprev1, use_prev2, use_prev1;
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wire [ 9:0] phase_VIII;
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wire s1_enters, s2_enters, s3_enters, s4_enters;
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wire rst_int;
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// LFO
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wire [6:0] lfo_mod;
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wire lfo_rst;
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`ifdef TEST_SUPPORT
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// Test bits
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wire test_eg, test_op0;
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`endif
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jt12_mmr u_mmr(
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.rst ( rst ),
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.clk ( clk ),
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.din ( din ),
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.write ( write ),
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.addr ( addr ),
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.busy ( busy ),
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.ch6op ( ch6op ),
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// LFO
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.lfo_freq ( lfo_freq ),
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.lfo_en ( lfo_en ),
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// Timers
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.value_A ( value_A ),
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.value_B ( value_B ),
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.load_A ( load_A ),
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.load_B ( load_B ),
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.enable_irq_A ( enable_irq_A ),
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.enable_irq_B ( enable_irq_B ),
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.clr_flag_A ( clr_flag_A ),
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.clr_flag_B ( clr_flag_B ),
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.flag_A ( flag_A ),
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.overflow_A ( overflow_A ),
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.fast_timers( fast_timers ),
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// PCM
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.pcm ( pcm ),
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.pcm_en ( pcm_en ),
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`ifdef TEST_SUPPORT
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// Test
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.test_eg ( test_eg ),
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.test_op0 ( test_op0 ),
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`endif
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// Operator
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.use_prevprev1 ( use_prevprev1 ),
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.use_internal_x ( use_internal_x ),
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.use_internal_y ( use_internal_y ),
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.use_prev2 ( use_prev2 ),
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.use_prev1 ( use_prev1 ),
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// PG
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.fnum_I ( fnum_I ),
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.block_I ( block_I ),
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.pg_stop ( pg_stop ),
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// EG
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.rl ( rl ),
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.fb_II ( fb_II ),
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.alg ( alg ),
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.pms ( pms ),
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.ams_VII ( ams_VII ),
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.amsen_VII ( amsen_VII ),
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.dt1_II ( dt1_II ),
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.mul_V ( mul_V ),
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.tl_VII ( tl_VII ),
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.ar_II ( ar_II ),
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.d1r_II ( d1r_II ),
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.d2r_II ( d2r_II ),
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.rr_II ( rr_II ),
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.d1l ( d1l ),
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.ks_III ( ks_III ),
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.eg_stop ( eg_stop ),
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// SSG operation
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.ssg_en_II ( ssg_en_II ),
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.ssg_eg_II ( ssg_eg_II ),
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.keyon_II ( keyon_II ),
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// Operator
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.zero ( zero ),
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.s1_enters ( s1_enters ),
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.s2_enters ( s2_enters ),
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.s3_enters ( s3_enters ),
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.s4_enters ( s4_enters )
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);
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jt12_timers u_timers(
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.clk ( clk ),
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.rst ( rst ),
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.clk_en ( zero ),
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.fast_timers( fast_timers ), // fix this to work well with clock enable signals
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.value_A ( value_A ),
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.value_B ( value_B ),
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.load_A ( load_A ),
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.load_B ( load_B ),
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.enable_irq_A( enable_irq_B ),
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.enable_irq_B( enable_irq_A ),
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.clr_flag_A ( clr_flag_A ),
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.clr_flag_B ( clr_flag_B ),
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.flag_A ( flag_A ),
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.flag_B ( flag_B ),
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.overflow_A ( overflow_A ),
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.irq_n ( irq_n )
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);
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jt12_lfo u_lfo(
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.rst ( rst ),
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.clk ( clk ),
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.zero ( zero ),
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.lfo_rst ( 1'b0 ),
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.lfo_en ( lfo_en ),
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.lfo_freq ( lfo_freq ),
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.lfo_mod ( lfo_mod )
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);
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`ifndef TIMERONLY
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jt12_pg u_pg(
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.clk ( clk ),
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.rst ( rst ),
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// Channel frequency
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.fnum_I ( fnum_I ),
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.block_I ( block_I ),
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// Operator multiplying
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.mul_V ( mul_V ),
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// Operator detuning
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.dt1_II ( dt1_II ), // same as JT51's DT1
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// phase operation
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.pg_rst_III ( pg_rst_III ),
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.zero ( zero ),
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.pg_stop ( pg_stop ),
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.keycode_III( keycode_III ),
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.phase_VIII ( phase_VIII )
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);
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jt12_eg u_eg(
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`ifdef TEST_SUPPORT
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.test_eg ( test_eg ),
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`endif
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.rst ( rst ),
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.clk ( clk ),
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.zero ( zero ),
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.eg_stop ( eg_stop ),
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// envelope configuration
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.keycode_III ( keycode_III ),
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.arate_II ( ar_II ), // attack rate
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.rate1_II ( d1r_II ), // decay rate
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.rate2_II ( d2r_II ), // sustain rate
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.rrate_II ( rr_II ), // release rate
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.d1l ( d1l ), // sustain level
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.ks_III ( ks_III ), // key scale
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// SSG operation
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.ssg_en_II ( ssg_en_II ),
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.ssg_eg_II ( ssg_eg_II ),
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// envelope operation
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.keyon_II ( keyon_II ),
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// envelope number
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.am ( lfo_mod ),
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.tl_VII ( tl_VII ),
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.ams_VII ( ams_VII ),
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.amsen_VII ( amsen_VII ),
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.eg_IX ( eg_IX ),
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.pg_rst_III ( pg_rst_III )
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);
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wire [8:0] op_result;
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jt12_op u_op(
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.rst ( rst ),
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.clk ( clk ),
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.pg_phase_VIII ( phase_VIII ),
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.eg_atten_IX ( eg_IX ),
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.fb_II ( fb_II ),
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.test_214 ( 1'b0 ),
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.s1_enters ( s1_enters ),
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.s2_enters ( s2_enters ),
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.s3_enters ( s3_enters ),
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.s4_enters ( s4_enters ),
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.use_prevprev1 ( use_prevprev1 ),
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.use_internal_x ( use_internal_x),
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.use_internal_y ( use_internal_y),
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.use_prev2 ( use_prev2 ),
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.use_prev1 ( use_prev1 ),
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.zero ( zero ),
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.op_result ( op_result )
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);
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jt12_acc u_acc(
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.rst ( rst ),
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.clk ( clk ),
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.op_result ( op_result ),
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.rl ( rl ),
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.limiter_en ( limiter_en),
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// note that the order changes to deal
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// with the operator pipeline delay
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.s1_enters ( s2_enters ),
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.s2_enters ( s1_enters ),
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.s3_enters ( s4_enters ),
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.s4_enters ( s3_enters ),
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.ch6op ( ch6op ),
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.pcm_en ( pcm_en ), // only enabled for channel 6
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.pcm ( pcm ),
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.alg ( alg ),
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// combined output
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.left ( snd_left ),
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.right ( snd_right ),
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.sample ( snd_sample),
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// muxed output
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.mux_left ( mux_left ),
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.mux_right ( mux_right ),
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.mux_sample ( mux_sample)
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);
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`ifdef SIMULATION
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reg [4:0] sep24_cnt;
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wire [9:0] eg_ch0s1, eg_ch1s1, eg_ch2s1, eg_ch3s1, eg_ch4s1, eg_ch5s1,
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eg_ch0s2, eg_ch1s2, eg_ch2s2, eg_ch3s2, eg_ch4s2, eg_ch5s2,
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eg_ch0s3, eg_ch1s3, eg_ch2s3, eg_ch3s3, eg_ch4s3, eg_ch5s3,
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eg_ch0s4, eg_ch1s4, eg_ch2s4, eg_ch3s4, eg_ch4s4, eg_ch5s4;
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always @(posedge clk)
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sep24_cnt <= !zero ? sep24_cnt+1'b1 : 5'd0;
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sep24 #( .width(10), .pos0(5'd0)) egsep
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(
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.clk ( clk ),
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.mixed ( eg_IX ),
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.mask ( 10'd0 ),
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.cnt ( sep24_cnt ),
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.ch0s1 (eg_ch0s1),
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.ch1s1 (eg_ch1s1),
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.ch2s1 (eg_ch2s1),
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.ch3s1 (eg_ch3s1),
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.ch4s1 (eg_ch4s1),
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.ch5s1 (eg_ch5s1),
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.ch0s2 (eg_ch0s2),
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.ch1s2 (eg_ch1s2),
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.ch2s2 (eg_ch2s2),
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.ch3s2 (eg_ch3s2),
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.ch4s2 (eg_ch4s2),
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.ch5s2 (eg_ch5s2),
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.ch0s3 (eg_ch0s3),
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.ch1s3 (eg_ch1s3),
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.ch2s3 (eg_ch2s3),
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.ch3s3 (eg_ch3s3),
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.ch4s3 (eg_ch4s3),
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.ch5s3 (eg_ch5s3),
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.ch0s4 (eg_ch0s4),
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.ch1s4 (eg_ch1s4),
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.ch2s4 (eg_ch2s4),
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.ch3s4 (eg_ch3s4),
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.ch4s4 (eg_ch4s4),
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.ch5s4 (eg_ch5s4)
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);
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`endif
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`endif
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endmodule
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