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78 lines
3.3 KiB
Verilog
78 lines
3.3 KiB
Verilog
`timescale 1ns / 1ps
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/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-1-2017
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*/
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// altera message_off 10030
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module jt12_phrom
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(
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input [4:0] addr,
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input clk,
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output reg [45:0] ph
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);
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reg [45:0] sinetable[31:0];
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initial
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begin
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sinetable[5'd0 ] <= 46'b0001100000100100010001000010101010101001010010;
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sinetable[5'd1 ] <= 46'b0001100000110100000100000010010001001101000001;
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sinetable[5'd2 ] <= 46'b0001100000110100000100110010001011001101100000;
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sinetable[5'd3 ] <= 46'b0001110000010000000000110010110001001101110010;
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sinetable[5'd4 ] <= 46'b0001110000010000001100000010111010001101101001;
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sinetable[5'd5 ] <= 46'b0001110000010100001001100010000000101101111010;
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sinetable[5'd6 ] <= 46'b0001110000010100001101100010010011001101011010;
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sinetable[5'd7 ] <= 46'b0001110000011100000101010010111000101111111100;
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sinetable[5'd8 ] <= 46'b0001110000111000000001110010101110001101110111;
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sinetable[5'd9 ] <= 46'b0001110000111000010100111000011101011010100110;
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sinetable[5'd10] <= 46'b0001110000111100011000011000111100001001111010;
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sinetable[5'd11] <= 46'b0001110000111100011100111001101011001001110111;
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sinetable[5'd12] <= 46'b0100100001010000010001011001001000111010110111;
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sinetable[5'd13] <= 46'b0100100001010100010001001001110001111100101010;
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sinetable[5'd14] <= 46'b0100100001010100010101101101111110100101000110;
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sinetable[5'd15] <= 46'b0100100011100000001000011001010110101101111001;
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sinetable[5'd16] <= 46'b0100100011100100001000101011100101001011101111;
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sinetable[5'd17] <= 46'b0100100011101100000111011010000001011010110001;
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sinetable[5'd18] <= 46'b0100110011001000000111101010000010111010111111;
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sinetable[5'd19] <= 46'b0100110011001100001011011110101110110110000001;
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sinetable[5'd20] <= 46'b0100110011101000011010111011001010001101110001;
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sinetable[5'd21] <= 46'b0100110011101101011010110101111001010100001111;
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sinetable[5'd22] <= 46'b0111000010000001010111000101010101010110010111;
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sinetable[5'd23] <= 46'b0111000010000101010111110111110101010010111011;
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sinetable[5'd24] <= 46'b0111000010110101101000101100001000010000011001;
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sinetable[5'd25] <= 46'b0111010010011001100100011110100100010010010010;
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sinetable[5'd26] <= 46'b0111010010111010100101100101000000110100100011;
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sinetable[5'd27] <= 46'b1010000010011010101101011101100001110010011010;
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sinetable[5'd28] <= 46'b1010000010111111111100100111010100010000111001;
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sinetable[5'd29] <= 46'b1010010111110100110010001100111001010110100000;
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sinetable[5'd30] <= 46'b1011010111010011111011011110000100110010100001;
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sinetable[5'd31] <= 46'b1110011011110001111011100111100001110110100111;
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end
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always @ (posedge clk)
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ph <= sinetable[addr];
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endmodule
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