mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 23:01:37 +03:00
470 lines
13 KiB
Verilog
470 lines
13 KiB
Verilog
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// PentEvo project (c) NedoPC 2008-2010
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module zports
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(
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input clk,
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input [7:0] din,
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output reg [7:0] dout,
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output dataout,
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input [15:0] a,
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input rst, // system reset
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input opfetch,
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input rd,
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input wr,
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input rdwr,
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input iorq,
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input iorq_s,
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input iord,
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input iord_s,
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input iowr,
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input iowr_s,
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input iordwr,
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input iordwr_s,
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output porthit, // when internal port hit occurs, this is 1, else 0; used for iorq1_n iorq2_n on zxbus
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output external_port, // asserts for AY and VG93 accesses
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output zborder_wr,
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output border_wr,
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output zvpage_wr,
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output vpage_wr,
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output vconf_wr,
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output gx_offsl_wr,
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output gx_offsh_wr,
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output gy_offsl_wr,
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output gy_offsh_wr,
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output t0x_offsl_wr,
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output t0x_offsh_wr,
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output t0y_offsl_wr,
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output t0y_offsh_wr,
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output t1x_offsl_wr,
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output t1x_offsh_wr,
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output t1y_offsl_wr,
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output t1y_offsh_wr,
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output tsconf_wr,
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output palsel_wr,
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output tmpage_wr,
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output t0gpage_wr,
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output t1gpage_wr,
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output sgpage_wr,
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output hint_beg_wr ,
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output vint_begl_wr,
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output vint_begh_wr,
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output [31:0] xt_page,
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output reg [4:0] fmaddr,
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input regs_we,
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output reg [7:0] sysconf,
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output reg [7:0] memconf,
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output reg [3:0] cacheconf,
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output reg [7:0] fddvirt,
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output [8:0] dmaport_wr,
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input dma_act,
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output reg [1:0] dmawpdev,
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output reg [7:0] intmask,
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input dos,
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input vdos,
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output vdos_on,
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output vdos_off,
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output ay_bdir,
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output ay_bc1,
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output covox_wr,
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output beeper_wr,
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input tape_read,
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input [4:0] keys_in, // keys (port FE)
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input [7:0] mus_in, // mouse (xxDF)
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input [5:0] kj_in,
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input vg_intrq,
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input vg_drq, // from vg93 module - drq + irq read
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output vg_cs_n,
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output vg_wrFF,
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output [1:0] drive_sel, // disk drive selection
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// SPI
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output sdcs_n,
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output sd_start,
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output [7:0] sd_datain,
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input [7:0] sd_dataout,
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// WAIT-ports related
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output reg [7:0] wait_addr,
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output wait_start_gluclock, // begin wait from some ports
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output wait_start_comport, //
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output reg [7:0] wait_write,
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input [7:0] wait_read
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);
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assign sdcs_n = spi_cs_n[0];
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localparam FDR_VER = 1'b0;
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localparam VDAC_VER = 3'h3;
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localparam PORTFE = 8'hFE;
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localparam PORTFD = 8'hFD;
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localparam PORTXT = 8'hAF;
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localparam PORTF7 = 8'hF7;
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localparam COVOX = 8'hFB;
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localparam VGCOM = 8'h1F;
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localparam VGTRK = 8'h3F;
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localparam VGSEC = 8'h5F;
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localparam VGDAT = 8'h7F;
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localparam VGSYS = 8'hFF;
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localparam KJOY = 8'h1F;
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localparam KMOUSE = 8'hDF;
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localparam SDCFG = 8'h77;
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localparam SDDAT = 8'h57;
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localparam COMPORT = 8'hEF; // F8EF..FFEF - rs232 ports
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wire [7:0] loa = a[7:0];
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wire [7:0] hoa = regs_we ? a[7:0] : a[15:8];
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assign porthit = ((loa==PORTFE) || (loa==PORTXT) || (loa==PORTFD) || (loa==COVOX))
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|| ((loa==PORTF7) && !dos)
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|| ((vg_port || vgsys_port) && (dos || open_vg))
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|| ((loa==KJOY) && !dos && !open_vg)
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|| (loa==KMOUSE)
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|| (((loa==SDCFG) || (loa==SDDAT)) && (!dos || vdos))
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|| (loa==COMPORT);
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wire vg_port = (loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT);
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wire vgsys_port = (loa==VGSYS);
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assign external_port = ((loa==PORTFD) && a[15]) // AY
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|| (((loa==VGCOM) || (loa==VGTRK) || (loa==VGSEC) || (loa==VGDAT)) && (dos || open_vg));
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assign dataout = porthit && iord && (~external_port);
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reg iowr_reg;
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reg iord_reg;
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reg port_wr;
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reg port_rd;
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always @(posedge clk) begin
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iowr_reg <= iowr;
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port_wr <= (!iowr_reg && iowr);
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iord_reg <= iord;
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port_rd <= (!iord_reg && iord);
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end
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// reading ports
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always @(*) begin
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case (loa)
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PORTFE:
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dout = {1'b1, tape_read, 1'b0, keys_in};
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PORTXT:
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begin
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case (hoa)
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XSTAT:
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dout = {1'b0, pwr_up_reg, FDR_VER, 2'b0, VDAC_VER};
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DMASTAT:
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dout = {dma_act, 7'b0};
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RAMPAGE + 8'd2, RAMPAGE + 8'd3:
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dout = rampage[hoa[1:0]];
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default:
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dout = 8'hFF;
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endcase
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end
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VGSYS:
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dout = {vg_intrq, vg_drq, 6'b111111};
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KJOY:
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dout = {2'b00, kj_in};
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KMOUSE:
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dout = mus_in;
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SDCFG:
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dout = 8'h00; // always SD inserted, SD is in R/W mode
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SDDAT:
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dout = sd_dataout;
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PORTF7:
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begin
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if (!a[14] && (a[8] ^ dos) && gluclock_on) dout = wait_read; // $BFF7 - data i/o
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else dout = 8'hFF; // any other $xxF7 port
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end
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COMPORT:
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dout = wait_read; // $F8EF..$FFEF
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default:
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dout = 8'hFF;
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endcase
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end
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// power-up
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// This bit is loaded as 1 while FPGA is configured
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// and automatically reset to 0 after STATUS port reading
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reg pwr_up_reg;
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reg pwr_up = 1;
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always @(posedge clk) begin
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if (iord_s & (loa == PORTXT) & (hoa == XSTAT)) begin
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pwr_up_reg <= pwr_up;
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pwr_up <= 1'b0;
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end
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end
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// writing ports
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//#nnAF
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localparam VCONF = 8'h00;
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localparam VPAGE = 8'h01;
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localparam GXOFFSL = 8'h02;
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localparam GXOFFSH = 8'h03;
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localparam GYOFFSL = 8'h04;
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localparam GYOFFSH = 8'h05;
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localparam TSCONF = 8'h06;
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localparam PALSEL = 8'h07;
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localparam XBORDER = 8'h0F;
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localparam T0XOFFSL = 8'h40;
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localparam T0XOFFSH = 8'h41;
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localparam T0YOFFSL = 8'h42;
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localparam T0YOFFSH = 8'h43;
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localparam T1XOFFSL = 8'h44;
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localparam T1XOFFSH = 8'h45;
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localparam T1YOFFSL = 8'h46;
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localparam T1YOFFSH = 8'h47;
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localparam RAMPAGE = 8'h10; // this covers #10-#13
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localparam FMADDR = 8'h15;
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localparam TMPAGE = 8'h16;
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localparam T0GPAGE = 8'h17;
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localparam T1GPAGE = 8'h18;
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localparam SGPAGE = 8'h19;
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localparam DMASADDRL = 8'h1A;
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localparam DMASADDRH = 8'h1B;
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localparam DMASADDRX = 8'h1C;
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localparam DMADADDRL = 8'h1D;
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localparam DMADADDRH = 8'h1E;
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localparam DMADADDRX = 8'h1F;
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localparam SYSCONF = 8'h20;
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localparam MEMCONF = 8'h21;
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localparam HSINT = 8'h22;
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localparam VSINTL = 8'h23;
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localparam VSINTH = 8'h24;
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localparam DMAWPD = 8'h25;
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localparam DMALEN = 8'h26;
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localparam DMACTRL = 8'h27;
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localparam DMANUM = 8'h28;
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localparam FDDVIRT = 8'h29;
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localparam INTMASK = 8'h2A;
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localparam CACHECONF = 8'h2B;
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localparam DMAWPA = 8'h2D;
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localparam XSTAT = 8'h00;
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localparam DMASTAT = 8'h27;
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assign dmaport_wr[0] = portxt_wr && (hoa == DMASADDRL);
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assign dmaport_wr[1] = portxt_wr && (hoa == DMASADDRH);
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assign dmaport_wr[2] = portxt_wr && (hoa == DMASADDRX);
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assign dmaport_wr[3] = portxt_wr && (hoa == DMADADDRL);
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assign dmaport_wr[4] = portxt_wr && (hoa == DMADADDRH);
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assign dmaport_wr[5] = portxt_wr && (hoa == DMADADDRX);
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assign dmaport_wr[6] = portxt_wr && (hoa == DMALEN);
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assign dmaport_wr[7] = portxt_wr && (hoa == DMACTRL);
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assign dmaport_wr[8] = portxt_wr && (hoa == DMANUM);
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assign zborder_wr = portfe_wr;
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assign border_wr = (portxt_wr && (hoa == XBORDER));
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assign zvpage_wr = p7ffd_wr;
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assign vpage_wr = (portxt_wr && (hoa == VPAGE ));
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assign vconf_wr = (portxt_wr && (hoa == VCONF ));
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assign gx_offsl_wr = (portxt_wr && (hoa == GXOFFSL));
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assign gx_offsh_wr = (portxt_wr && (hoa == GXOFFSH));
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assign gy_offsl_wr = (portxt_wr && (hoa == GYOFFSL));
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assign gy_offsh_wr = (portxt_wr && (hoa == GYOFFSH));
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assign t0x_offsl_wr = (portxt_wr && (hoa == T0XOFFSL));
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assign t0x_offsh_wr = (portxt_wr && (hoa == T0XOFFSH));
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assign t0y_offsl_wr = (portxt_wr && (hoa == T0YOFFSL));
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assign t0y_offsh_wr = (portxt_wr && (hoa == T0YOFFSH));
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assign t1x_offsl_wr = (portxt_wr && (hoa == T1XOFFSL));
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assign t1x_offsh_wr = (portxt_wr && (hoa == T1XOFFSH));
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assign t1y_offsl_wr = (portxt_wr && (hoa == T1YOFFSL));
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assign t1y_offsh_wr = (portxt_wr && (hoa == T1YOFFSH));
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assign tsconf_wr = (portxt_wr && (hoa == TSCONF));
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assign palsel_wr = (portxt_wr && (hoa == PALSEL));
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assign tmpage_wr = (portxt_wr && (hoa == TMPAGE));
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assign t0gpage_wr = (portxt_wr && (hoa == T0GPAGE));
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assign t1gpage_wr = (portxt_wr && (hoa == T1GPAGE));
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assign sgpage_wr = (portxt_wr && (hoa == SGPAGE));
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assign hint_beg_wr = (portxt_wr && (hoa == HSINT ));
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assign vint_begl_wr = (portxt_wr && (hoa == VSINTL));
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assign vint_begh_wr = (portxt_wr && (hoa == VSINTH));
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assign beeper_wr = portfe_wr;
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wire portfe_wr = (loa==PORTFE) && iowr_s;
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assign covox_wr = (loa==COVOX) && iowr_s;
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wire portxt_wr = ((loa==PORTXT) && iowr_s) || regs_we;
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reg [7:0] rampage[0:3];
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assign xt_page = {rampage[3], rampage[2], rampage[1], rampage[0]};
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wire lock128 = lock128_3 ? 1'b0 : (lock128_2 ? m1_lock128 : memconf[6]);
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wire lock128_2 = memconf[7:6] == 2'b10; // mode 2
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wire lock128_3 = memconf[7:6] == 2'b11; // mode 3
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reg m1_lock128;
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always @(posedge clk) if (opfetch) m1_lock128 <= !(din[7] ^ din[6]);
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always @(posedge clk) begin
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if (rst) begin
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fmaddr[4] <= 1'b0;
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intmask <= 8'b1;
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fddvirt <= 8'b0;
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sysconf <= 8'h00; // 3.5 MHz
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memconf <= 8'h04; // no map
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cacheconf <= 4'h0; // no cache
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rampage[0]<= 8'h00;
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rampage[1]<= 8'h05;
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rampage[2]<= 8'h02;
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rampage[3]<= 8'h00;
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end
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else if (p7ffd_wr) begin
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memconf[0] <= din[4];
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rampage[3] <= {2'b0, lock128_3 ? {din[5], din[7:6]} : ({1'b0, lock128 ? 2'b0 : din[7:6]}), din[2:0]};
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end
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else if (portxt_wr) begin
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if (hoa[7:2] == RAMPAGE[7:2]) rampage[hoa[1:0]] <= din;
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if (hoa == FMADDR) fmaddr <= din[4:0];
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if (hoa == SYSCONF) begin
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sysconf <= din;
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cacheconf <= {4{din[2]}};
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end
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if (hoa == DMAWPD) dmawpdev <= din[1:0];
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if (hoa == CACHECONF) cacheconf <= din[3:0];
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if (hoa == MEMCONF) memconf <= din;
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if (hoa == FDDVIRT) fddvirt <= din;
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if (hoa == INTMASK) intmask <= din;
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end
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end
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// 7FFD port
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wire p7ffd_wr = !a[15] && (loa==PORTFD) && iowr_s && !lock48;
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reg lock48;
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always @(posedge clk) begin
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if (rst) lock48 <= 1'b0;
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else if (p7ffd_wr && !lock128_3) lock48 <= din[5];
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end
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// AY control
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wire ay_hit = (loa==PORTFD) & a[15];
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assign ay_bc1 = ay_hit & a[14] & iordwr;
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assign ay_bdir = ay_hit & iowr;
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// VG93
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wire [3:0] fddvrt = fddvirt[3:0];
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wire virt_vg = fddvrt[drive_sel_raw];
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wire open_vg = fddvirt[7];
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assign drive_sel = {drive_sel_raw[1], drive_sel_raw[0]};
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wire vg_wen = (dos || open_vg) && !vdos && !virt_vg;
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assign vg_cs_n = !(iordwr && vg_port && vg_wen);
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assign vg_wrFF = iowr_s && vgsys_port && vg_wen;
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wire vg_wrDS = iowr_s && vgsys_port && (dos || open_vg);
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assign vdos_on = iordwr_s && (vg_port || vgsys_port) && dos && !vdos && virt_vg;
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assign vdos_off = iordwr_s && vg_port && vdos;
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// write drive number
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reg [1:0] drive_sel_raw;
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always @(posedge clk) if (vg_wrDS) drive_sel_raw <= din[1:0];
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// SD card (Z-controller compatible)
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wire sdcfg_wr;
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wire sddat_wr;
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wire sddat_rd;
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reg [1:0] spi_cs_n;
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assign sdcfg_wr = ((loa==SDCFG) && iowr_s && (!dos || vdos));
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assign sddat_wr = ((loa==SDDAT) && iowr_s && (!dos || vdos));
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assign sddat_rd = ((loa==SDDAT) && iord_s);
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// SDCFG write - sdcs_n control
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always @(posedge clk) begin
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if (rst) spi_cs_n <= 2'b11;
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else if (sdcfg_wr) spi_cs_n <= {~din[2], din[1]};
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end
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// start signal for SPI module with resyncing to fclk
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assign sd_start = sddat_wr || sddat_rd;
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// data for SPI module
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assign sd_datain = wr ? din : 8'hFF;
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// xxF7
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wire portf7_wr = ((loa==PORTF7) && (a[8]==1'b1) && port_wr && (!dos || vdos));
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wire portf7_rd = ((loa==PORTF7) && (a[8]==1'b1) && port_rd && (!dos || vdos));
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// EFF7 port
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reg [7:0] peff7;
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always @(posedge clk) begin
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if (rst) peff7 <= 8'h00;
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else if (!a[12] && portf7_wr && !dos) peff7 <= din; // #EEF7 in dos is not accessible
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end
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// gluclock ports
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wire gluclock_on = peff7[7] || dos; // in dos mode EEF7 is not accessible, gluclock access is ON in dos mode.
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// comports
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wire comport_wr = ((loa == COMPORT) && port_wr);
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wire comport_rd = ((loa == COMPORT) && port_rd);
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// write to wait registers
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always @(posedge clk) begin
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// gluclocks
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if (gluclock_on && portf7_wr) begin
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if (!a[14]) wait_write <= din; // $BFF7 - data reg
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if (!a[13]) wait_addr <= din; // $DFF7 - addr reg
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end
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// com ports
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if (comport_wr) wait_write <= din; // $xxEF
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if (comport_wr || comport_rd) wait_addr <= a[15:8];
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if ((loa==PORTXT) && (hoa == DMAWPA)) wait_addr <= din;
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end
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// wait from wait registers
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// ACHTUNG!!!! here portxx_wr are ON Z80 CLOCK! logic must change when moving to clk strobes
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assign wait_start_gluclock = (gluclock_on && !a[14] && (portf7_rd || portf7_wr)); // $BFF7 - gluclock r/w
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assign wait_start_comport = (comport_rd || comport_wr);
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endmodule
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