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69 lines
1.5 KiB
Verilog
69 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-1-2017
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*/
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module jt12_kon(
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input rst,
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input clk,
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input [3:0] keyon_op,
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input [2:0] keyon_ch,
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input [1:0] cur_op,
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input [2:0] cur_ch,
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input up_keyon,
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input csm,
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input flag_A,
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input overflow_A,
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output reg keyon_II
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);
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//reg csm_copy;
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reg din;
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wire drop;
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reg [3:0] cur_op_hot;
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always @(posedge clk)
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keyon_II <= (csm&&cur_ch==2'd2&&overflow_A) || drop;
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always @(*) begin
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case( cur_op )
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2'd0: cur_op_hot <= 4'b0001; // S1
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2'd1: cur_op_hot <= 4'b0100; // S3
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2'd2: cur_op_hot <= 4'b0010; // S2
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2'd3: cur_op_hot <= 4'b1000; // S4
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endcase
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din <= keyon_ch==cur_ch && up_keyon ? |(keyon_op&cur_op_hot) : drop;
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end
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jt12_sh_rst #(.width(1),.stages(24)) u_konch(
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.clk ( clk ),
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// .rst ( rst ),
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.din ( din ),
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.drop ( drop )
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);
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endmodule
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