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69 lines
1.4 KiB
Verilog
69 lines
1.4 KiB
Verilog
/* This file is part of jt12.
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jt12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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jt12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with jt12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 25-2-2017
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*/
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`timescale 1ns / 1ps
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/*
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tab size 4
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*/
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module jt12_lfo(
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input rst,
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input clk,
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input zero,
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input lfo_rst,
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input lfo_en,
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input [2:0] lfo_freq,
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output reg [6:0] lfo_mod
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);
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reg [6:0] cnt, limit;
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always @(*)
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case( lfo_freq )
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3'd0: limit <= 7'd108;
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3'd1: limit <= 7'd78;
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3'd2: limit <= 7'd71;
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3'd3: limit <= 7'd67;
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3'd4: limit <= 7'd62;
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3'd5: limit <= 7'd44;
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3'd6: limit <= 7'd8;
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3'd7: limit <= 7'd5;
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endcase
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always @(posedge clk) begin
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if( rst || !lfo_en )
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{ lfo_mod, cnt } <= 14'd0;
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else begin
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if(zero) begin
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if( cnt == limit ) begin
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cnt <= 7'd0;
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lfo_mod <= lfo_mod + 1'b1;
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end
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else
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cnt <= cnt + 1'b1;
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end
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end
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end
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endmodule
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