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123 lines
3.3 KiB
Verilog
123 lines
3.3 KiB
Verilog
`timescale 1ns / 1ps
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/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-1-2017
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*/
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module jt12_mod(
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input s1_enters,
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input s2_enters,
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input s3_enters,
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input s4_enters,
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input [2:0] alg_I,
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output reg use_prevprev1,
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output reg use_internal_x,
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output reg use_internal_y,
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output reg use_prev2,
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output reg use_prev1
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);
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reg [7:0] alg_hot;
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always @(*) begin
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case( alg_I )
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3'd0: alg_hot <= 8'h1; // D0
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3'd1: alg_hot <= 8'h2; // D1
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3'd2: alg_hot <= 8'h4; // D2
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3'd3: alg_hot <= 8'h8; // D3
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3'd4: alg_hot <= 8'h10; // D4
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3'd5: alg_hot <= 8'h20; // D5
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3'd6: alg_hot <= 8'h40; // D6
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3'd7: alg_hot <= 8'h80; // D7
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endcase
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end
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always @(*) begin
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use_prevprev1 <= s1_enters | (s3_enters&alg_hot[5]);
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use_prev2 <= (s3_enters&(|alg_hot[2:0])) | (s4_enters&alg_hot[3]);
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use_internal_x <= s4_enters & alg_hot[2];
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use_internal_y <= s4_enters & (|{alg_hot[4:3],alg_hot[1:0]});
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use_prev1 <= s1_enters | (s3_enters&alg_hot[1]) |
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(s2_enters&(|{alg_hot[6:3],alg_hot[0]}) )|
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(s4_enters&(|{alg_hot[5],alg_hot[2]}));
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end
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/*
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always @(*) begin
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use_prevprev1 <= s1_enters || (s3_enters&&(alg_I==3'd5));
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use_prev2 <= (s3_enters&&(alg_I<=3'd2)) || (s4_enters&&(alg_I==3'd3));
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use_internal_x <= s4_enters && (alg_I==3'd2);
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use_internal_y <= s4_enters && (alg_I<=3'd4 && alg_I!=3'd2);
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use_prev1 <= s1_enters || (s3_enters&&(alg_I==3'd1)) ||
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(s2_enters&&(alg_I==3'd0 ||
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alg_I==3'd3 || alg_I==3'd4 ||
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alg_I==3'd5 || alg_I==3'd6)) ||
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(s4_enters&&(alg_I==3'd2 || alg_I==3'd5));
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end
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always @(*) begin
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case( {s1_enters, s3_enters, s2_enters, s4_enters} ) // synthesis parallel_case
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4'b1000: begin // S1
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use_prevprev1 <= 1'b1;
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use_prev2 <= 1'b0;
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use_internal_x<= 1'b0;
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use_internal_y<= 1'b0;
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use_prev1 <= 1'b1;
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end
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4'b0100: begin // S3
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use_prevprev1 <= alg_I==3'd5;
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use_prev2 <= (alg_I<=3'd2);
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use_internal_x<= 1'b0;
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use_internal_y<= 1'b0;
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use_prev1 <= alg_I==3'd1;
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end
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4'b0010: begin // S2
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use_prevprev1 <= 1'b0;
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use_prev2 <= 1'b0;
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use_internal_x<= 1'b0;
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use_prev1 <= (alg_I==3'd0 ||
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alg_I==3'd3 || alg_I==3'd4 ||
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alg_I==3'd5 || alg_I==3'd6 );
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use_internal_y<= 1'b0;
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end
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4'b0001: begin // S4
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use_prevprev1 <= 1'b0;
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use_prev2 <= ( alg_I==3'd3 );
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use_internal_x <= alg_I==3'd2;
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use_prev1 <= (alg_I==3'd2 || alg_I==3'd5);
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use_internal_y <= ( alg_I<=3'd4 && alg_I!=3'd2);
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end
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default:begin
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use_prevprev1 <= 1'bx;
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use_prev2 <= 1'bx;
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use_internal_x<= 1'bx;
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use_prev1 <= 1'bx;
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use_internal_y<= 1'bx;
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end
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endcase
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end
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*/
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endmodule
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