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80 lines
2.0 KiB
Verilog
80 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 27-1-2017
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*/
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module jt12_opram
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(
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input [4:0] wr_addr,
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input [4:0] rd_addr,
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input clk,
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input [43:0] data,
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output reg [43:0] q
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);
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reg [43:0] ram[31:0];
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initial
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begin
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ram[0] = { ~7'd0, 37'd0 };
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ram[1] = { ~7'd0, 37'd0 };
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ram[2] = { ~7'd0, 37'd0 };
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ram[3] = { ~7'd0, 37'd0 };
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ram[4] = { ~7'd0, 37'd0 };
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ram[5] = { ~7'd0, 37'd0 };
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ram[6] = { ~7'd0, 37'd0 };
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ram[7] = { ~7'd0, 37'd0 };
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ram[8] = { ~7'd0, 37'd0 };
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ram[9] = { ~7'd0, 37'd0 };
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ram[10] = { ~7'd0, 37'd0 };
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ram[11] = { ~7'd0, 37'd0 };
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ram[12] = { ~7'd0, 37'd0 };
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ram[13] = { ~7'd0, 37'd0 };
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ram[14] = { ~7'd0, 37'd0 };
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ram[15] = { ~7'd0, 37'd0 };
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ram[16] = { ~7'd0, 37'd0 };
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ram[17] = { ~7'd0, 37'd0 };
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ram[18] = { ~7'd0, 37'd0 };
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ram[19] = { ~7'd0, 37'd0 };
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ram[20] = { ~7'd0, 37'd0 };
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ram[21] = { ~7'd0, 37'd0 };
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ram[22] = { ~7'd0, 37'd0 };
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ram[23] = { ~7'd0, 37'd0 };
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ram[24] = { ~7'd0, 37'd0 };
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ram[25] = { ~7'd0, 37'd0 };
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ram[26] = { ~7'd0, 37'd0 };
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ram[27] = { ~7'd0, 37'd0 };
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ram[28] = { ~7'd0, 37'd0 };
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ram[29] = { ~7'd0, 37'd0 };
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ram[30] = { ~7'd0, 37'd0 };
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ram[31] = { ~7'd0, 37'd0 };
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end
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always @ (posedge clk) begin
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q <= ram[rd_addr];
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ram[wr_addr] <= data;
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end
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endmodule
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