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38 lines
1.0 KiB
Verilog
38 lines
1.0 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 1-31-2017
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*/
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`timescale 1ns / 1ps
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module jt12_sumch
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(
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input [4:0] chin,
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output reg [4:0] chout
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);
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reg [2:0] aux;
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always @(*) begin
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aux <= chin[2:0] + 3'd1;
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chout[2:0] <= aux[1:0]==2'b11 ? aux+3'd1 : aux;
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chout[4:3] <= chin[2:0]==3'd6 ? chin[4:3]+2'd1 : chin[4:3];
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end
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endmodule
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