mirror of
https://github.com/UzixLS/TSConf_MiST.git
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138 lines
3.7 KiB
Systemverilog
138 lines
3.7 KiB
Systemverilog
//============================================================================
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// Turbosound-FM
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//
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// Copyright (C) 2018 Ilia Sharin
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// Copyright (C) 2018 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module turbosound
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(
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input RESET, // Chip RESET (set all Registers to '0', active high)
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input CLK, // Global clock
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input CE_CPU, // CPU Clock enable
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input CE_YM, // YM2203 Master Clock enable x2 (due to YM2612 model!)
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input BDIR, // Bus Direction (0 - read , 1 - write)
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input BC, // Bus control
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input [7:0] DI, // Data In
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output [7:0] DO, // Data Out
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output [11:0] CHANNEL_L, // Output channel L
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output [11:0] CHANNEL_R, // Output channel R
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output ACTIVE
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);
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// AY1 selected by default
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reg ay_select = 1;
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reg stat_sel = 1;
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reg fm_ena = 0;
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always_ff @(posedge CLK or posedge RESET) begin
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if (RESET) begin
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ay_select <= 1;
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stat_sel <= 1;
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fm_ena <= 0;
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end
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else if (BDIR & BC & &DI[7:3]) begin
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ay_select <= DI[0];
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stat_sel <= DI[1];
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fm_ena <= ~DI[2];
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end
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end
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wire [7:0] psg_ch_a_0;
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wire [7:0] psg_ch_b_0;
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wire [7:0] psg_ch_c_0;
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wire [10:0] opn_0;
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wire [7:0] DO_0;
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wire WE_0 = ~ay_select & BDIR;
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wire ay0_playing;
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ym2203 ym2203_0
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(
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.RESET(RESET),
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.CLK(CLK),
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.CE_CPU(CE_CPU),
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.CE_YM(CE_YM),
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.A0(WE_0 ? ~BC : stat_sel),
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.WE(WE_0),
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.DI(DI),
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.DO(DO_0),
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.CHANNEL_A(psg_ch_a_0),
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.CHANNEL_B(psg_ch_b_0),
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.CHANNEL_C(psg_ch_c_0),
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.CHANNEL_FM(opn_0),
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.PSG_ACTIVE(ay0_playing),
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.FM_ENA(fm_ena)
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);
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wire [7:0] psg_ch_a_1;
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wire [7:0] psg_ch_b_1;
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wire [7:0] psg_ch_c_1;
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wire [10:0] opn_1;
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wire [7:0] DO_1;
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wire WE_1 = ay_select & BDIR;
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wire ay1_playing;
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ym2203 ym2203_1
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(
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.RESET(RESET),
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.CLK(CLK),
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.CE_CPU(CE_CPU),
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.CE_YM(CE_YM),
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.A0(WE_1 ? ~BC : stat_sel),
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.WE(WE_1),
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.DI(DI),
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.DO(DO_1),
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.CHANNEL_A(psg_ch_a_1),
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.CHANNEL_B(psg_ch_b_1),
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.CHANNEL_C(psg_ch_c_1),
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.CHANNEL_FM(opn_1),
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.PSG_ACTIVE(ay1_playing),
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.FM_ENA(fm_ena)
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);
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assign DO = ay_select ? DO_1 : DO_0;
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assign ACTIVE = ay0_playing | ay1_playing | fm_ena;
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// Mix channel signals from both AY/YM chips (extending to 9 bits width to prevent clipping)
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wire [8:0] sum_ch_a = { 1'b0, psg_ch_a_1 } + { 1'b0, psg_ch_a_0 };
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wire [8:0] sum_ch_b = { 1'b0, psg_ch_b_1 } + { 1'b0, psg_ch_b_0 };
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wire [8:0] sum_ch_c = { 1'b0, psg_ch_c_1 } + { 1'b0, psg_ch_c_0 };
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// Control output channels (Only AY_1 plays if not in TurboSound mode)
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wire [7:0] psg_a = ~ay0_playing ? psg_ch_a_1 : sum_ch_a[8:1];
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wire [7:0] psg_b = ~ay0_playing ? psg_ch_b_1 : sum_ch_b[8:1];
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wire [7:0] psg_c = ~ay0_playing ? psg_ch_c_1 : sum_ch_c[8:1];
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wire signed [11:0] psg_l = {3'b000, psg_a, 1'd0} + {4'b0000, psg_b};
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wire signed [11:0] psg_r = {3'b000, psg_c, 1'd0} + {4'b0000, psg_b};
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wire signed [11:0] opn_s = {{2{opn_0[10]}}, opn_0[10:1]} + {{2{opn_1[10]}}, opn_1[10:1]};
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assign CHANNEL_L = fm_ena ? opn_s + psg_l : psg_l;
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assign CHANNEL_R = fm_ena ? opn_s + psg_r : psg_r;
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endmodule
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