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https://github.com/UzixLS/TSConf_MiST.git
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371 lines
8.7 KiB
Verilog
371 lines
8.7 KiB
Verilog
/* This file is part of JT12.
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JT12 is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 14-2-2017
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*/
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`timescale 1ns / 1ps
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module jt12_mmr(
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input rst,
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input clk,
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input [7:0] din,
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input write,
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input [1:0] addr,
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output reg busy,
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output ch6op,
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// LFO
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output reg [2:0] lfo_freq,
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output reg lfo_en,
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// Timers
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output reg [9:0] value_A,
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output reg [7:0] value_B,
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output reg load_A,
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output reg load_B,
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output reg enable_irq_A,
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output reg enable_irq_B,
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output reg clr_flag_A,
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output reg clr_flag_B,
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output reg fast_timers,
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input flag_A,
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input overflow_A,
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// PCM
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output reg [8:0] pcm,
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output reg pcm_en,
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`ifdef TEST_SUPPORT
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// Test
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output reg test_eg,
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output reg test_op0,
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`endif
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// Operator
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output use_prevprev1,
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output use_internal_x,
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output use_internal_y,
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output use_prev2,
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output use_prev1,
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// PG
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output [10:0] fnum_I,
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output [ 2:0] block_I,
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output reg pg_stop,
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// REG
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output [ 1:0] rl,
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output [ 2:0] fb_II,
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output [ 2:0] alg,
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output [ 2:0] pms,
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output [ 1:0] ams_VII,
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output amsen_VII,
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output [ 2:0] dt1_II,
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output [ 3:0] mul_V,
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output [ 6:0] tl_VII,
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output reg eg_stop,
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output [ 4:0] ar_II,
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output [ 4:0] d1r_II,
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output [ 4:0] d2r_II,
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output [ 3:0] rr_II,
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output [ 3:0] d1l,
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output [ 1:0] ks_III,
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// SSG operation
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output ssg_en_II,
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output [2:0] ssg_eg_II,
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output keyon_II,
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// output [ 1:0] cur_op,
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// Operator
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output zero,
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output s1_enters,
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output s2_enters,
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output s3_enters,
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output s4_enters
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);
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reg [7:0] selected_register;
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//reg sch; // 0 => CH1~CH3 only available. 1=>CH4~CH6
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/*
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reg irq_zero_en, irq_brdy_en, irq_eos_en,
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irq_tb_en, irq_ta_en;
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*/
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reg up_clr;
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reg up_alg;
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reg up_block;
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reg up_fnumlo;
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reg up_pms;
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reg up_dt1;
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reg up_tl;
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reg up_ks_ar;
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reg up_amen_d1r;
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reg up_d2r;
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reg up_d1l;
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reg up_ssgeg;
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reg up_keyon;
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wire busy_reg;
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parameter REG_TEST = 8'h01,
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REG_TEST2 = 8'h02,
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REG_TESTYM = 8'h21,
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REG_LFO = 8'h22,
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REG_CLKA1 = 8'h24,
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REG_CLKA2 = 8'h25,
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REG_CLKB = 8'h26,
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REG_TIMER = 8'h27,
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REG_KON = 8'h28,
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REG_IRQMASK = 8'h29,
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REG_PCM = 8'h2A,
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REG_PCM_EN = 8'h2B,
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REG_DACTEST = 8'h2C,
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REG_CLK_N6 = 8'h2D,
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REG_CLK_N3 = 8'h2E,
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REG_CLK_N2 = 8'h2F;
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reg csm, effect;
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reg [ 2:0] block_ch3op2, block_ch3op3, block_ch3op1;
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reg [10:0] fnum_ch3op2, fnum_ch3op3, fnum_ch3op1;
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reg [ 5:0] latch_ch3op2, latch_ch3op3, latch_ch3op1;
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reg [2:0] up_ch;
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reg [1:0] up_op;
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`include "jt12_mmr_sim.vh"
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always @(posedge clk) begin : memory_mapped_registers
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reg old_write;
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old_write <= write;
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if( rst ) begin
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selected_register <= 8'h0;
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busy <= 1'b0;
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up_ch <= 3'd0;
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up_op <= 2'd0;
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{ up_keyon, up_alg, up_block, up_fnumlo,
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up_pms, up_dt1, up_tl, up_ks_ar,
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up_amen_d1r,up_d2r, up_d1l, up_ssgeg } <= 12'd0;
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`ifdef TEST_SUPPORT
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{ test_eg, test_op0 } <= 2'd0;
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`endif
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// IRQ Mask
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/*{ irq_zero_en, irq_brdy_en, irq_eos_en,
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irq_tb_en, irq_ta_en } = 5'h1f; */
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// timers
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{ value_A, value_B } <= 18'd0;
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{ clr_flag_B, clr_flag_A,
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enable_irq_B, enable_irq_A, load_B, load_A } <= 6'd0;
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up_clr <= 1'b0;
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fast_timers <= 1'b0;
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// LFO
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lfo_freq <= 3'd0;
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lfo_en <= 1'b0;
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csm <= 1'b0;
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effect <= 1'b0;
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// PCM
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pcm <= 9'h0;
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pcm_en <= 1'b0;
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// sch <= 1'b0;
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// Original test features
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eg_stop <= 1'b0;
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pg_stop <= 1'b0;
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`ifdef SIMULATION
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mmr_dump <= 1'b0;
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`endif
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end else begin
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// WRITE IN REGISTERS
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if( old_write ^ write ) begin
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busy <= 1'b1;
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if( !addr[0] ) begin
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selected_register <= din;
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up_ch <= {addr[1], din[1:0]};
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up_op <= din[3:2]; // 0=S1,1=S3,2=S2,3=S4
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end else begin
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// Global registers
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if( selected_register < 8'h30 ) begin
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case( selected_register)
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// registros especiales
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//REG_TEST: lfo_rst <= 1'b1; // regardless of din
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`ifdef TEST_SUPPORT
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REG_TEST2: { mmr_dump, test_op0, test_eg } <= din[2:0];
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`endif
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REG_TESTYM: begin
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eg_stop <= din[5];
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pg_stop <= din[3];
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fast_timers <= din[2];
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end
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REG_KON: up_keyon <= 1'b1;
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REG_CLKA1: value_A[9:2]<= din;
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REG_CLKA2: value_A[1:0]<= din[1:0];
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REG_CLKB: value_B <= din;
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REG_TIMER: begin
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effect <= |din[7:6];
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csm <= din[7:6] == 2'b10;
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{ clr_flag_B, clr_flag_A,
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enable_irq_B, enable_irq_A,
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load_B, load_A } <= din[5:0];
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end
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REG_LFO: { lfo_en, lfo_freq } <= din[3:0];
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REG_DACTEST:pcm[0] <= din[3];
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REG_PCM: pcm[8:1]<= din;
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REG_PCM_EN: pcm_en <= din[7];
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endcase
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end
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else if( selected_register[1:0]!=2'b11 ) begin
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// channel registers
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if( selected_register >= 8'hA0 ) begin
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case( selected_register )
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8'hA0, 8'hA1, 8'hA2: up_fnumlo <= 1'b1;
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8'hA4, 8'hA5, 8'hA6: up_block <= 1'b1;
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// CH3 special registers
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8'hA9: { block_ch3op1, fnum_ch3op1 } <= { latch_ch3op1, din };
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8'hA8: { block_ch3op3, fnum_ch3op3 } <= { latch_ch3op3, din };
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8'hAA: { block_ch3op2, fnum_ch3op2 } <= { latch_ch3op2, din };
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8'hAD: latch_ch3op1 <= din[5:0];
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8'hAC: latch_ch3op3 <= din[5:0];
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8'hAE: latch_ch3op2 <= din[5:0];
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// FB + Algorithm
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8'hB0, 8'hB1, 8'hB2: up_alg <= 1'b1;
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8'hB4, 8'hB5, 8'hB6: up_pms <= 1'b1;
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endcase
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end
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else
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// operator registers
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begin
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case( selected_register[7:4] )
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4'h3: up_dt1 <= 1'b1;
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4'h4: up_tl <= 1'b1;
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4'h5: up_ks_ar <= 1'b1;
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4'h6: up_amen_d1r <= 1'b1;
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4'h7: up_d2r <= 1'b1;
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4'h8: up_d1l <= 1'b1;
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4'h9: up_ssgeg <= 1'b1;
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endcase
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end
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end
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end
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end
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else begin /* clear once-only bits */
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// csm <= 1'b0;
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// lfo_rst <= 1'b0;
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{ clr_flag_B, clr_flag_A, load_B, load_A } <= 4'd0;
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`ifdef SIMULATION
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mmr_dump <= 1'b0;
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`endif
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up_keyon <= 1'b0;
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if( |{ up_keyon, up_alg, up_block, up_fnumlo,
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up_pms, up_dt1, up_tl, up_ks_ar,
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up_amen_d1r,up_d2r, up_d1l, up_ssgeg } == 1'b0 )
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busy <= 0;
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else
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busy <= 1'b1;
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if( busy_reg ) begin
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up_clr <= 1'b1;
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end
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else begin
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up_clr <= 1'b0;
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if( up_clr )
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{ up_alg, up_block, up_fnumlo,
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up_pms, up_dt1, up_tl, up_ks_ar,
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up_amen_d1r,up_d2r, up_d1l, up_ssgeg } <= 11'd0;
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end
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end
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end
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end
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jt12_reg u_reg(
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.rst ( rst ),
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.clk ( clk ), // P1
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.din ( din ),
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.up_keyon ( up_keyon ),
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.up_alg ( up_alg ),
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.up_block ( up_block ),
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.up_fnumlo ( up_fnumlo ),
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.up_pms ( up_pms ),
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.up_dt1 ( up_dt1 ),
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.up_tl ( up_tl ),
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.up_ks_ar ( up_ks_ar ),
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.up_amen_d1r(up_amen_d1r),
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.up_d2r ( up_d2r ),
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.up_d1l ( up_d1l ),
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.up_ssgeg ( up_ssgeg ),
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.op ( up_op ), // operator to update
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.ch ( up_ch ), // channel to update
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.csm ( csm ),
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.flag_A ( flag_A ),
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.overflow_A ( overflow_A),
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.busy ( busy_reg ),
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.ch6op ( ch6op ),
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// CH3 Effect-mode operation
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.effect ( effect ), // allows independent freq. for CH 3
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.fnum_ch3op2( fnum_ch3op2 ),
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.fnum_ch3op3( fnum_ch3op3 ),
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.fnum_ch3op1( fnum_ch3op1 ),
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.block_ch3op2( block_ch3op2 ),
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.block_ch3op3( block_ch3op3 ),
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.block_ch3op1( block_ch3op1 ),
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// Operator
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.use_prevprev1(use_prevprev1),
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.use_internal_x(use_internal_x),
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.use_internal_y(use_internal_y),
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.use_prev2 ( use_prev2 ),
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.use_prev1 ( use_prev1 ),
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// PG
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.fnum_I ( fnum_I ),
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.block_I ( block_I ),
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.mul_V ( mul_V ),
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.dt1_II ( dt1_II ),
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// EG
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.ar_II (ar_II ), // attack rate
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.d1r_II (d1r_II ), // decay rate
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.d2r_II (d2r_II ), // sustain rate
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.rr_II (rr_II ), // release rate
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.d1l (d1l ), // sustain level
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.ks_III (ks_III ), // key scale
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// SSG operation
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.ssg_en_II ( ssg_en_II ),
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.ssg_eg_II ( ssg_eg_II ),
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// envelope number
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.tl_VII (tl_VII ),
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.pms (pms ),
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.ams_VII (ams_VII ),
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.amsen_VII (amsen_VII ),
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// channel configuration
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.rl ( rl ),
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.fb_II ( fb_II ),
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.alg ( alg ),
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.keyon_II ( keyon_II ),
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//.cur_op ( cur_op ),
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.zero ( zero ),
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.s1_enters ( s1_enters ),
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.s2_enters ( s2_enters ),
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.s3_enters ( s3_enters ),
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.s4_enters ( s4_enters )
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);
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endmodule
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