mirror of
https://github.com/UzixLS/zx-sizif-xxs.git
synced 2025-07-18 23:01:40 +03:00
replace composite video output implementation
New one is borrowed from Speccy 2010 project. It's have a much, much better output quality in price of increased FPGA resources usage.
This commit is contained in:
UzixLS
@ -1,149 +0,0 @@
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// Based on Joerg Wolfram's code //
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module chroma_gen #(
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parameter CLK_FREQ
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) (
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input cg_clock, // input clock
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input cg_enable, // colour enable
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input cg_hsync, // hor. sync
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input cg_pnsel, // system (pal/ntsc)
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input [2:0] cg_rgb, // rgb input
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output reg [2:0] cg_out // chroma out
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);
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localparam CARRIER_WIDTH =
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(CLK_FREQ == 14_000_000)? 17 :
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(CLK_FREQ == 14_318_180)? 17 :
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(CLK_FREQ == 16_000_000)? 14 :
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(CLK_FREQ == 17_734_475)? 3 :
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(CLK_FREQ == 20_000_000)? 14 :
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(CLK_FREQ == 24_000_000)? 17 :
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(CLK_FREQ == 25_000_000)? 16 :
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(CLK_FREQ == 28_000_000)? 18 :
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(CLK_FREQ == 28_375_000)? 16 :
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(CLK_FREQ == 28_636_360)? 18 :
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(CLK_FREQ == 32_000_000)? 15 :
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(CLK_FREQ == 35_468_950)? 3 :
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(CLK_FREQ == 40_000_000)? 15 :
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0;
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localparam PAL_CARRIER =
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(CLK_FREQ == 14_000_000)? 83018 : // 20.776 error
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(CLK_FREQ == 14_318_180)? 81173 : // 11.72 error
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(CLK_FREQ == 16_000_000)? 9080 : // 25 error
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(CLK_FREQ == 17_734_475)? 4 : // 0 error
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(CLK_FREQ == 20_000_000)? 7264 : // 25 error
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(CLK_FREQ == 24_000_000)? 48427 : // 5.51 error
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(CLK_FREQ == 25_000_000)? 23245 : // 13.14 error
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(CLK_FREQ == 28_000_000)? 83018 : // 20.78 error
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(CLK_FREQ == 28_375_000)? 20480 : // 25 error
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(CLK_FREQ == 28_636_360)? 81173 : // 11.76 error
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(CLK_FREQ == 32_000_000)? 9080 : // 25 error
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(CLK_FREQ == 35_468_950)? 2 : // 0 error
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(CLK_FREQ == 40_000_000)? 7264 : // 25 error
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0;
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localparam NTSC_CARRIER =
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(CLK_FREQ == 14_000_000)? 67025 : // 23.82 error
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(CLK_FREQ == 14_318_180)? 65536 : // 0 errror
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(CLK_FREQ == 16_000_000)? 7331 : // 44.84 error
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(CLK_FREQ == 17_734_475)? 4 : // 0 error (NTSC4.43)
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(CLK_FREQ == 20_000_000)? 5865 : // 166.91 error
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(CLK_FREQ == 24_000_000)? 39098 : // 16.19 error
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(CLK_FREQ == 25_000_000)? 18767 : // 23.82 error
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(CLK_FREQ == 28_000_000)? 67025 : // 23.82 error
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(CLK_FREQ == 28_375_000)? 16535 : // 19.1 error
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(CLK_FREQ == 28_636_360)? 65536 : // 0 error
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(CLK_FREQ == 32_000_000)? 7331 : // 44.84 error
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(CLK_FREQ == 35_468_950)? 2 : // 0 error (NTSC4.43)
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(CLK_FREQ == 40_000_000)? 5865 : // 166.91 error
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0;
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// localparam PAL_CARRIER = 64'd17_734_475 * (1<<(CARRIER_WIDTH-1)) / CLK_FREQ;
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// localparam NTSC_CARRIER = 64'd14_318_180 * (1<<(CARRIER_WIDTH-1)) / CLK_FREQ;
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reg [CARRIER_WIDTH:0] carrier;
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wire [31:0] carrier_next;
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reg [3:0] burst_cnt;
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wire burst;
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reg oddeven;
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reg [3:0] phase;
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reg [3:0] scarrier;
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wire cenable;
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// DDS for PAL-carrier
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assign carrier_next = (cg_pnsel == 1'b0)?
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(carrier + PAL_CARRIER) :
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(carrier + NTSC_CARRIER) ;
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always @(posedge cg_clock) begin
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carrier <= carrier_next[CARRIER_WIDTH:0];
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end
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// burst generator
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always @(posedge carrier[CARRIER_WIDTH] or negedge cg_hsync) begin
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if (cg_hsync == 1'b0)
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burst_cnt <= 4'b0100;
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else if (burst_cnt != 4'b0000)
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burst_cnt <= burst_cnt + 1'b1;
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end
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assign burst = burst_cnt[3];
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// odd/even line
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always @(posedge cg_hsync) begin
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if (cg_pnsel == 1'b0)
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oddeven <= ~oddeven;
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else
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oddeven <= 1'b0;
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end
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// carrier phase
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always @* begin
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if (burst == 1'b1) begin
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if ((oddeven == 1'b0) && (cg_pnsel == 1'b0))
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phase <= 4'b0110; // burst phase 135 deg
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else
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phase <= 4'b1010; // burst phase -135 deg
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end
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else if (oddeven == 1'b0) begin
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case (cg_rgb)
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3'b001: phase <= 4'b0000; // blue phase
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3'b010: phase <= 4'b0101; // red phase
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3'b011: phase <= 4'b0011; // magenta phase
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3'b100: phase <= 4'b1011; // green phase
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3'b101: phase <= 4'b1101; // cyan phase
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3'b110: phase <= 4'b0111; // yellow phase
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default: phase <= 4'b0000; // dummy function
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endcase
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end
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else begin
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case (cg_rgb)
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3'b001: phase <= 4'b0000; // blue phase
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3'b010: phase <= 4'b1011; // red phase
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3'b011: phase <= 4'b1101; // magenta phase
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3'b100: phase <= 4'b0101; // green phase
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3'b101: phase <= 4'b0011; // cyan phase
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3'b110: phase <= 4'b1001; // yellow phase
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default: phase <= 4'b0000; // dummy function
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endcase
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end
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end
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// modulated carrier
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always @*
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scarrier <= carrier[CARRIER_WIDTH:CARRIER_WIDTH-3] + phase;
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// colour enable
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assign cenable =
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cg_enable == 1'b1 &&
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cg_rgb != 3'b000 &&
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cg_rgb != 3'b111;
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// chroma signal
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always @(posedge cg_clock) begin
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cg_out[2] <= cenable;
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cg_out[1] <= burst;
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cg_out[0] <= scarrier[3];
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end
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endmodule
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@ -7,9 +7,9 @@ module screen(
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input machine_t machine,
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input [2:0] border,
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output reg [2:0] r,
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output reg [2:0] g,
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output reg [1:0] b,
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output reg [5:0] r,
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output reg [5:0] g,
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output reg [5:0] b,
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output reg vsync,
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output reg hsync,
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output reg csync,
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@ -287,14 +287,20 @@ always @(posedge clk28) begin
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if (blank)
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{g, r, b} = 0;
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else if (up_en) begin
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g = pixel? up_ink0[7:5] : up_paper0[7:5];
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r = pixel? up_ink0[4:2] : up_paper0[4:2];
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b = pixel? up_ink0[1:0] : up_paper0[1:0];
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g[5:3] = pixel? up_ink0[7:5] : up_paper0[7:5];
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r[5:3] = pixel? up_ink0[4:2] : up_paper0[4:2];
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b[5:4] = pixel? up_ink0[1:0] : up_paper0[1:0];
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g[2:0] = g[5:3];
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r[2:0] = r[5:3];
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b[3:0] = {b[5:4], b[5:4]};
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end
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else begin
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{g[2], r[2], b[1]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
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{g[1], r[1], b[0]} = {g[2] & attr[6], r[2] & attr[6], b[1] & attr[6]};
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{g[0], r[0]} = {g[2], r[2]};
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{g[5], r[5], b[5]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
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{g[4], r[4], b[4]} = {g[5], r[5], b[5]};
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{g[3], r[3], b[3]} = attr[6]? {g[5], r[5], b[5]} : 3'b000;
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{g[2], r[2], b[2]} = {g[3], r[3], b[3]};
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{g[1], r[1], b[1]} = {g[3], r[3], b[3]};
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{g[0], r[0], b[0]} = {g[3], r[3], b[3]};
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end
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end
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@ -22,9 +22,8 @@ module zx_ula(
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output reg n_int,
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output n_nmi,
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output reg [5:0] luma,
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output reg [2:0] chroma,
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output reg csync,
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output [7:0] composite,
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input [1:0] reserv,
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output snd_l,
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output snd_r,
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@ -41,10 +40,15 @@ module zx_ula(
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/* CLOCK */
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wire clk28 = clk_in;
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wire clk40;
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wire clk20;
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wire clk168;
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wire rst_n;
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pll pll0(.inclk0(clk_in), .c0(clk40), .c1(clk20), .locked(rst_n));
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pll pll0(.inclk0(clk_in), .c0(clk168), .locked(rst_n));
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reg [1:0] clk168_en42_cnt = 0;
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reg clk168_en42;
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always @(posedge clk168) begin
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clk168_en42 <= clk168_en42_cnt == 2'b00;
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clk168_en42_cnt <= clk168_en42_cnt + 1'b1;
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end
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/* SHARED DEFINITIONS */
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@ -104,9 +108,8 @@ end
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/* SCREEN CONTROLLER */
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wire blink;
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wire [2:0] screen_border = {border[2] ^ ~sd_cs, border[1] ^ magic_beeper, border[0]};
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wire [2:0] r, g;
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wire [1:0] b;
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wire hsync;
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wire [5:0] r, g, b;
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wire hsync, vsync, csync0;
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wire screen_contention, port_ff_active;
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wire [14:0] screen_addr;
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wire [5:0] up_ink_addr, up_paper_addr;
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@ -124,8 +127,8 @@ screen screen0(
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.r(r),
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.g(g),
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.b(b),
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.csync(csync),
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.vsync(),
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.csync(csync0),
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.vsync(vsync),
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.hsync(hsync),
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.fetch_allow((!bus.iorq && !bus.mreq && !bus.m1) || bus.rfsh || clkwait),
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@ -157,21 +160,17 @@ screen screen0(
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/* VIDEO OUTPUT */
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always @*
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luma <= 2*r + 5*g + b;
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wire [2:0] chroma0;
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chroma_gen #(.CLK_FREQ(40_000_000)) chroma_gen1(
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.cg_clock(clk40),
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.cg_rgb({|g,|r,|b}),
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.cg_hsync(hsync),
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.cg_enable(1'b1),
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.cg_pnsel(1'b0),
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.cg_out(chroma0)
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vencode vencode(
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.clk(clk168),
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.clk_en(clk168_en42),
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.videoR(r),
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.videoG(g),
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.videoB(b),
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.videoHS_n(hsync),
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.videoVS_n(vsync),
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.videoPS_n(csync0),
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.videoV(composite)
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);
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assign chroma[0] = (chroma0[1])? chroma0[0] : 1'bz;
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assign chroma[1] = (chroma0[2])? chroma0[0] : 1'bz;
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assign chroma[2] = (chroma0[2])? chroma0[0] : 1'bz;
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/* PS/2 KEYBOARD */
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194
fpga/rtl/vencode.vhd
Normal file
194
fpga/rtl/vencode.vhd
Normal file
@ -0,0 +1,194 @@
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-- Speccy 2010
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vencode is
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generic(
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freq : integer := 42
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);
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port(
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clk : in std_logic;
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clk_en : in std_logic;
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-- Video Input
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videoR : in std_logic_vector(5 downto 0);
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videoG : in std_logic_vector(5 downto 0);
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videoB : in std_logic_vector(5 downto 0);
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videoHS_n : in std_logic;
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videoVS_n : in std_logic;
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videoPS_n : in std_logic;
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-- Video Output
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videoY : out std_logic_vector(7 downto 0);
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videoC : out std_logic_vector(7 downto 0);
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videoV : out std_logic_vector(7 downto 0)
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);
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end vencode;
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architecture rtl of vencode is
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signal carrier : unsigned(7 downto 0);
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signal vcounter : unsigned(8 downto 0);
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signal hcounter : unsigned(12 downto 0);
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signal burphase : unsigned(1 downto 0) := "00";
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signal window_v : std_logic;
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signal window_h : std_logic;
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signal window_c : std_logic;
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signal ivideoR : unsigned(5 downto 0);
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signal ivideoG : unsigned(5 downto 0);
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signal ivideoB : unsigned(5 downto 0);
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signal Y1 : unsigned(13 downto 0);
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signal Y2 : unsigned(13 downto 0);
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signal Y3 : unsigned(13 downto 0);
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signal U1 : unsigned(13 downto 0);
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signal U2 : unsigned(13 downto 0);
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signal U3 : unsigned(13 downto 0);
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signal V1 : unsigned(13 downto 0);
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signal V2 : unsigned(13 downto 0);
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signal V3 : unsigned(13 downto 0);
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signal burstUV : signed(13 downto 0);
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signal prevY : signed(13 downto 0);
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signal prevU : signed(13 downto 0);
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signal prevV : signed(13 downto 0);
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signal prevC : signed(23 downto 0);
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signal inSin : std_logic_vector(15 downto 0);
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signal inCos : std_logic_vector(15 downto 0);
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signal sin : signed(15 downto 0);
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signal cos : signed(15 downto 0);
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signal pcos : signed(15 downto 0);
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signal Um : signed(23 downto 0);
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signal Vm : signed(23 downto 0);
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signal Y : signed(7 downto 0);
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signal U : signed(7 downto 0);
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signal V : signed(7 downto 0);
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signal C : signed(7 downto 0);
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constant vref : signed(13 downto 0) := to_signed( 54, 8 ) & "000000";
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constant cent : signed(7 downto 0) := X"80";
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component vencode_sin_cos
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port(
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clk : in std_logic;
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phase : in std_logic_vector(7 downto 0);
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sinus : out std_logic_vector(15 downto 0);
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cosinus : out std_logic_vector(15 downto 0)
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);
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end component;
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begin
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process(clk, clk_en )
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variable carrierCounter : unsigned(15 downto 0);
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begin
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if ( clk'event and clk = '1' and clk_en = '1' ) then
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carrierCounter := carrierCounter + 157;
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if carrierCounter >= 6552 then
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carrier <= carrier + 28;
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carrierCounter := carrierCounter - 6552;
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else
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carrier <= carrier + 27;
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end if;
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end if;
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end process;
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vencode_sin_cos0 : vencode_sin_cos port map( clk, std_logic_vector( carrier ), inSin, inCos );
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sin <= signed( inSin( 15 downto 0 ) );
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cos <= signed( inCos( 15 downto 0 ) );
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pcos <= cos when burphase(0) = '0' else -cos;
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process(clk, clk_en )
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variable ivideoVS_n : std_logic;
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variable ivideoHS_n : std_logic;
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begin
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if ( clk'event and clk = '1' and clk_en = '1' ) then
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Y <= prevY( 13 downto 6 );
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Um <= U * sin;
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Vm <= V * pcos;
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videoY <= std_logic_vector( Y );
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videoC <= std_logic_vector( cent + C );
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videoV <= std_logic_vector( Y + C );
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ivideoR <= unsigned( videoR );
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ivideoG <= unsigned( videoG );
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ivideoB <= unsigned( videoB );
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if ( videoHS_n = '0' and ivideoHS_n = '1' ) then
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vcounter <= vcounter + 1;
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burphase <= burphase - 1;
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hcounter <= ( others => '0' );
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else
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hcounter <= hcounter + 1;
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end if;
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if (videoVS_n = '0' and ivideoVS_n = '1') then
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vcounter <= ( others => '0' );
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end if;
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if ( vcounter = ( 10 - 1 ) ) then
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window_v <= '1';
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elsif ( vcounter = ( 310 - 1 ) ) then
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window_v <= '0';
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end if;
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if (hcounter = ( integer( 10.5 * real( freq ) ) - 1 ) ) then
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window_h <= '1';
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elsif ( hcounter = ( integer( 62.5 * real( freq ) ) - 1 ) ) then
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window_h <= '0';
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end if;
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if ( hcounter = ( integer( 5.6 * real( freq ) ) - 1 ) ) then
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window_c <= '1';
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||||
elsif ( hcounter = ( integer( 8.1 * real( freq ) ) - 1 ) ) then
|
||||
window_c <= '0';
|
||||
end if;
|
||||
|
||||
ivideoVS_n := videoVS_n;
|
||||
ivideoHS_n := videoHS_n;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Y = 0.299 R + 0.587 G + 0.114 B
|
||||
-- U = -0.147 R - 0.289 G + 0.436 B
|
||||
-- V = 0.615 R - 0.515 G - 0.100 B
|
||||
|
||||
Y1 <= ( to_unsigned( 38, 8 ) * ivideoR );
|
||||
Y2 <= ( to_unsigned( 75, 8 ) * ivideoG );
|
||||
Y3 <= ( to_unsigned( 15, 8 ) * ivideoB );
|
||||
|
||||
U1 <= ( to_unsigned( 19, 8 ) * ivideoR );
|
||||
U2 <= ( to_unsigned( 37, 8 ) * ivideoG );
|
||||
U3 <= ( to_unsigned( 56, 8 ) * ivideoB );
|
||||
|
||||
V1 <= ( to_unsigned( 79, 8 ) * ivideoR );
|
||||
V2 <= ( to_unsigned( 66, 8 ) * ivideoG );
|
||||
V3 <= ( to_unsigned( 13, 8 ) * ivideoB );
|
||||
|
||||
prevY <= to_signed( 0, 14 ) when videoPS_n = '0' else
|
||||
vref + signed( Y1 + Y2 + Y3 ) when ( window_h = '1' and window_v = '1' ) else
|
||||
vref;
|
||||
|
||||
burstUV <= to_signed( 32, 8 ) & "000000" when ( window_c = '1' and window_v = '1' ) else
|
||||
( others => '0' );
|
||||
prevU <= signed( U3 - U1 - U2 ) when ( window_h = '1' and window_v = '1' ) else
|
||||
( -burstUV );
|
||||
prevV <= signed( V1 - V2 - V3 ) when ( window_h = '1' and window_v = '1' ) else
|
||||
( burstUV );
|
||||
|
||||
U <= prevU( 13 downto 6 );
|
||||
V <= prevV( 13 downto 6 );
|
||||
prevC <= Um + Vm;
|
||||
C <= prevC( 23 downto 16 );
|
||||
|
||||
end rtl;
|
||||
66
fpga/rtl/vencode_sin_cos.v
Normal file
66
fpga/rtl/vencode_sin_cos.v
Normal file
@ -0,0 +1,66 @@
|
||||
module vencode_sin_cos(
|
||||
input clk,
|
||||
input [7:0] phase,
|
||||
output reg [15:0] sinus,
|
||||
output reg [15:0] cosinus
|
||||
);
|
||||
reg [6:0] addr1, addr2;
|
||||
wire [15:0] value1, value2;
|
||||
vencode_sin_cos_rom vencode_sin_cos_rom0(
|
||||
.address_a(addr1),
|
||||
.address_b(addr2),
|
||||
.clock(clk),
|
||||
.q_a(value1),
|
||||
.q_b(value2)
|
||||
);
|
||||
|
||||
always @* begin
|
||||
if(!phase[6])
|
||||
addr1 <= {1'b0, phase[5:0]};
|
||||
else
|
||||
addr1 <= 7'h40 - {1'b0, phase[5:0]};
|
||||
if (!phase[7])
|
||||
sinus <= value1;
|
||||
else
|
||||
sinus <= -value1;
|
||||
end
|
||||
|
||||
wire [7:0] phase_cosinus = phase + 8'b01000000;
|
||||
always @* begin
|
||||
if(!phase_cosinus[6])
|
||||
addr2 <= {1'b0, phase_cosinus[5:0]};
|
||||
else
|
||||
addr2 <= 7'h40 - {1'b0, phase_cosinus[5:0]};
|
||||
if (!phase_cosinus[7])
|
||||
cosinus <= value2;
|
||||
else
|
||||
cosinus <= -value2;
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
module vencode_sin_cos_rom(
|
||||
input [6:0] address_a,
|
||||
input [6:0] address_b,
|
||||
input clock,
|
||||
output reg [15:0] q_a,
|
||||
output reg [15:0] q_b
|
||||
);
|
||||
reg [15:0] rom [0:64];
|
||||
initial begin
|
||||
rom <= '{
|
||||
16'h0000, 16'h025b, 16'h04b6, 16'h0710, 16'h0969, 16'h0bc0, 16'h0e16, 16'h106a,
|
||||
16'h12bb, 16'h1509, 16'h1753, 16'h199b, 16'h1bde, 16'h1e1d, 16'h2057, 16'h228d,
|
||||
16'h24bd, 16'h26e7, 16'h290c, 16'h2b2a, 16'h2d41, 16'h2f51, 16'h315b, 16'h335c,
|
||||
16'h3556, 16'h3747, 16'h3930, 16'h3b10, 16'h3ce7, 16'h3eb4, 16'h4078, 16'h4232,
|
||||
16'h43e2, 16'h4587, 16'h4722, 16'h48b1, 16'h4a36, 16'h4bae, 16'h4d1c, 16'h4e7d,
|
||||
16'h4fd2, 16'h511b, 16'h5258, 16'h5387, 16'h54aa, 16'h55c0, 16'h56c8, 16'h57c4,
|
||||
16'h58b1, 16'h5991, 16'h5a63, 16'h5b28, 16'h5bde, 16'h5c86, 16'h5d1f, 16'h5dab,
|
||||
16'h5e28, 16'h5e96, 16'h5ef6, 16'h5f47, 16'h5f8a, 16'h5fbd, 16'h5fe2, 16'h5ff9,
|
||||
16'h6000 };
|
||||
end
|
||||
always @(negedge clock) begin
|
||||
q_a <= rom[address_a];
|
||||
q_b <= rom[address_b];
|
||||
end
|
||||
endmodule
|
||||
@ -1,13 +1,10 @@
|
||||
create_clock -period 28MHz -name {clk28} [get_ports {clk_in}]
|
||||
|
||||
# clkcpu 3.5 or 7 MHz
|
||||
create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk_in}] [get_registers {cpucontrol:cpucontrol0|clkcpu}]
|
||||
|
||||
# hc0[2] 3.5 MHz
|
||||
create_generated_clock -name {hc0_2} -divide_by 8 -source [get_ports {clk_in}] [get_registers {screen:screen0|hc0[2]}]
|
||||
|
||||
# hsync len 4.7uS, 14e6/(1/4.7e-6) ~= 65
|
||||
create_generated_clock -name {hsync} -divide_by 126 -source [get_ports {clk_in}] [get_registers {screen:screen0|hsync}]
|
||||
create_generated_clock -name {clkcpu} -divide_by 2 -source [get_ports {clk_in}] [get_registers {cpucontrol:cpucontrol0|clkcpu}]
|
||||
create_generated_clock -name {hc0[1]} -divide_by 4 -source [get_ports {clk_in}] [get_registers {screen:screen0|hc0[1]}]
|
||||
|
||||
derive_pll_clocks
|
||||
derive_clocks -period 14MHz
|
||||
|
||||
set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -setup 4
|
||||
set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -hold 3
|
||||
|
||||
@ -4,7 +4,6 @@
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
<pin name="locked" direction="output" scope="external" />
|
||||
|
||||
</global>
|
||||
|
||||
@ -39,27 +39,23 @@
|
||||
module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
|
||||
wire [5:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire [0:0] sub_wire5 = 1'h0;
|
||||
wire [0:0] sub_wire1 = sub_wire0[0:0];
|
||||
wire c0 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
wire sub_wire3 = inclk0;
|
||||
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire5),
|
||||
.inclk (sub_wire4),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
@ -97,14 +93,10 @@ module pll (
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.clk0_divide_by = 7,
|
||||
altpll_component.clk0_divide_by = 1,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 10,
|
||||
altpll_component.clk0_multiply_by = 6,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 7,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 5,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 35714,
|
||||
altpll_component.intended_device_family = "Cyclone",
|
||||
@ -139,7 +131,7 @@ module pll (
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
@ -179,11 +171,8 @@ endmodule
|
||||
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "168.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@ -205,26 +194,18 @@ endmodule
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "168.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
@ -247,25 +228,18 @@ endmodule
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "7"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "7"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "35714"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
|
||||
@ -299,7 +273,7 @@ endmodule
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
@ -316,13 +290,11 @@ endmodule
|
||||
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
|
||||
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
|
||||
@ -96,16 +96,16 @@ set_location_assignment PIN_4 -to va[12]
|
||||
set_location_assignment PIN_5 -to va[11]
|
||||
set_location_assignment PIN_20 -to ps2_dat
|
||||
set_location_assignment PIN_21 -to ps2_clk
|
||||
set_location_assignment PIN_22 -to chroma[0]
|
||||
set_location_assignment PIN_23 -to chroma[1]
|
||||
set_location_assignment PIN_24 -to chroma[2]
|
||||
set_location_assignment PIN_25 -to csync
|
||||
set_location_assignment PIN_26 -to luma[5]
|
||||
set_location_assignment PIN_27 -to luma[4]
|
||||
set_location_assignment PIN_28 -to luma[3]
|
||||
set_location_assignment PIN_29 -to luma[2]
|
||||
set_location_assignment PIN_34 -to luma[1]
|
||||
set_location_assignment PIN_35 -to luma[0]
|
||||
set_location_assignment PIN_22 -to reserv[0]
|
||||
set_location_assignment PIN_23 -to reserv[1]
|
||||
set_location_assignment PIN_24 -to composite[0]
|
||||
set_location_assignment PIN_25 -to composite[7]
|
||||
set_location_assignment PIN_26 -to composite[6]
|
||||
set_location_assignment PIN_27 -to composite[5]
|
||||
set_location_assignment PIN_28 -to composite[4]
|
||||
set_location_assignment PIN_29 -to composite[3]
|
||||
set_location_assignment PIN_34 -to composite[2]
|
||||
set_location_assignment PIN_35 -to composite[1]
|
||||
set_location_assignment PIN_36 -to snd_l
|
||||
set_location_assignment PIN_37 -to snd_r
|
||||
set_location_assignment PIN_38 -to sd_cd
|
||||
@ -167,9 +167,10 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/magic.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/divmmc.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/cpucontrol.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/memcontrol.sv
|
||||
set_global_assignment -name VERILOG_FILE ../rtl/chroma_gen.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/turbosound.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv
|
||||
set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v
|
||||
set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd
|
||||
set_global_assignment -name VERILOG_FILE ../rtl/ps2.v
|
||||
set_global_assignment -name VERILOG_FILE ../rtl/ps2_rxtx.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/common.sv
|
||||
|
||||
@ -93,12 +93,7 @@ zx_ula zx_ula1(
|
||||
.sd_mosi_tape_out(sd_mosi_miso),
|
||||
.sd_miso_tape_in(sd_mosi_miso),
|
||||
.ps2_clk(),
|
||||
.ps2_dat(),
|
||||
.csync(),
|
||||
.luma(),
|
||||
.chroma(),
|
||||
.snd_l(),
|
||||
.snd_r()
|
||||
.ps2_dat()
|
||||
);
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,5 @@
|
||||
- Incorrect Q1 pinout
|
||||
- R7 should be 0 Ohm
|
||||
- R14 should be 82 Ohm
|
||||
- R19 should be 200 Ohm
|
||||
- R20, R22, R25 should be ??? (TODO) Ohm
|
||||
- X1 - 28MHz
|
||||
- R5 should be 200
|
||||
- R14 should be 0
|
||||
- R19 should be 200
|
||||
- do not install: R20, R21, R22, R23, R24, R25, C18, C19, Q1
|
||||
|
||||
@ -3480,8 +3480,6 @@ Connection ~ 11725 2050
|
||||
Wire Wire Line
|
||||
11375 2050 11725 2050
|
||||
NoConn ~ 11175 6475
|
||||
Text Notes 9700 3775 0 39 Italic 0
|
||||
R5 270\nR14 82\nR19 200\nR7 0
|
||||
Wire Bus Line
|
||||
4925 675 3225 675
|
||||
$Comp
|
||||
@ -3591,4 +3589,6 @@ Wire Bus Line
|
||||
3600 3075 3600 6475
|
||||
Wire Bus Line
|
||||
625 675 625 4025
|
||||
Text Notes 9650 3950 0 39 Italic 0
|
||||
R5 200\nR14 0\nR19 200\n\ndo not install:\nR20, R21, R22,\nR23, R24, R25,\nC18, C19, Q1
|
||||
$EndSCHEMATC
|
||||
|
||||
Reference in New Issue
Block a user