diff --git a/fpga/rtl/chroma_gen.v b/fpga/rtl/chroma_gen.v deleted file mode 100755 index c5fa411..0000000 --- a/fpga/rtl/chroma_gen.v +++ /dev/null @@ -1,149 +0,0 @@ -// Based on Joerg Wolfram's code // - -module chroma_gen #( - parameter CLK_FREQ - ) ( - input cg_clock, // input clock - input cg_enable, // colour enable - input cg_hsync, // hor. sync - input cg_pnsel, // system (pal/ntsc) - input [2:0] cg_rgb, // rgb input - output reg [2:0] cg_out // chroma out -); - -localparam CARRIER_WIDTH = - (CLK_FREQ == 14_000_000)? 17 : - (CLK_FREQ == 14_318_180)? 17 : - (CLK_FREQ == 16_000_000)? 14 : - (CLK_FREQ == 17_734_475)? 3 : - (CLK_FREQ == 20_000_000)? 14 : - (CLK_FREQ == 24_000_000)? 17 : - (CLK_FREQ == 25_000_000)? 16 : - (CLK_FREQ == 28_000_000)? 18 : - (CLK_FREQ == 28_375_000)? 16 : - (CLK_FREQ == 28_636_360)? 18 : - (CLK_FREQ == 32_000_000)? 15 : - (CLK_FREQ == 35_468_950)? 3 : - (CLK_FREQ == 40_000_000)? 15 : - 0; -localparam PAL_CARRIER = - (CLK_FREQ == 14_000_000)? 83018 : // 20.776 error - (CLK_FREQ == 14_318_180)? 81173 : // 11.72 error - (CLK_FREQ == 16_000_000)? 9080 : // 25 error - (CLK_FREQ == 17_734_475)? 4 : // 0 error - (CLK_FREQ == 20_000_000)? 7264 : // 25 error - (CLK_FREQ == 24_000_000)? 48427 : // 5.51 error - (CLK_FREQ == 25_000_000)? 23245 : // 13.14 error - (CLK_FREQ == 28_000_000)? 83018 : // 20.78 error - (CLK_FREQ == 28_375_000)? 20480 : // 25 error - (CLK_FREQ == 28_636_360)? 81173 : // 11.76 error - (CLK_FREQ == 32_000_000)? 9080 : // 25 error - (CLK_FREQ == 35_468_950)? 2 : // 0 error - (CLK_FREQ == 40_000_000)? 7264 : // 25 error - 0; -localparam NTSC_CARRIER = - (CLK_FREQ == 14_000_000)? 67025 : // 23.82 error - (CLK_FREQ == 14_318_180)? 65536 : // 0 errror - (CLK_FREQ == 16_000_000)? 7331 : // 44.84 error - (CLK_FREQ == 17_734_475)? 4 : // 0 error (NTSC4.43) - (CLK_FREQ == 20_000_000)? 5865 : // 166.91 error - (CLK_FREQ == 24_000_000)? 39098 : // 16.19 error - (CLK_FREQ == 25_000_000)? 18767 : // 23.82 error - (CLK_FREQ == 28_000_000)? 67025 : // 23.82 error - (CLK_FREQ == 28_375_000)? 16535 : // 19.1 error - (CLK_FREQ == 28_636_360)? 65536 : // 0 error - (CLK_FREQ == 32_000_000)? 7331 : // 44.84 error - (CLK_FREQ == 35_468_950)? 2 : // 0 error (NTSC4.43) - (CLK_FREQ == 40_000_000)? 5865 : // 166.91 error - 0; - -// localparam PAL_CARRIER = 64'd17_734_475 * (1<<(CARRIER_WIDTH-1)) / CLK_FREQ; -// localparam NTSC_CARRIER = 64'd14_318_180 * (1<<(CARRIER_WIDTH-1)) / CLK_FREQ; - -reg [CARRIER_WIDTH:0] carrier; -wire [31:0] carrier_next; -reg [3:0] burst_cnt; -wire burst; -reg oddeven; -reg [3:0] phase; -reg [3:0] scarrier; -wire cenable; - - -// DDS for PAL-carrier -assign carrier_next = (cg_pnsel == 1'b0)? - (carrier + PAL_CARRIER) : - (carrier + NTSC_CARRIER) ; - -always @(posedge cg_clock) begin - carrier <= carrier_next[CARRIER_WIDTH:0]; -end - -// burst generator -always @(posedge carrier[CARRIER_WIDTH] or negedge cg_hsync) begin - if (cg_hsync == 1'b0) - burst_cnt <= 4'b0100; - else if (burst_cnt != 4'b0000) - burst_cnt <= burst_cnt + 1'b1; -end -assign burst = burst_cnt[3]; - -// odd/even line -always @(posedge cg_hsync) begin - if (cg_pnsel == 1'b0) - oddeven <= ~oddeven; - else - oddeven <= 1'b0; -end - -// carrier phase -always @* begin - if (burst == 1'b1) begin - if ((oddeven == 1'b0) && (cg_pnsel == 1'b0)) - phase <= 4'b0110; // burst phase 135 deg - else - phase <= 4'b1010; // burst phase -135 deg - end - else if (oddeven == 1'b0) begin - case (cg_rgb) - 3'b001: phase <= 4'b0000; // blue phase - 3'b010: phase <= 4'b0101; // red phase - 3'b011: phase <= 4'b0011; // magenta phase - 3'b100: phase <= 4'b1011; // green phase - 3'b101: phase <= 4'b1101; // cyan phase - 3'b110: phase <= 4'b0111; // yellow phase - default: phase <= 4'b0000; // dummy function - endcase - end - else begin - case (cg_rgb) - 3'b001: phase <= 4'b0000; // blue phase - 3'b010: phase <= 4'b1011; // red phase - 3'b011: phase <= 4'b1101; // magenta phase - 3'b100: phase <= 4'b0101; // green phase - 3'b101: phase <= 4'b0011; // cyan phase - 3'b110: phase <= 4'b1001; // yellow phase - default: phase <= 4'b0000; // dummy function - endcase - end -end - -// modulated carrier -always @* - scarrier <= carrier[CARRIER_WIDTH:CARRIER_WIDTH-3] + phase; - -// colour enable -assign cenable = - cg_enable == 1'b1 && - cg_rgb != 3'b000 && - cg_rgb != 3'b111; - -// chroma signal -always @(posedge cg_clock) begin - cg_out[2] <= cenable; - cg_out[1] <= burst; - cg_out[0] <= scarrier[3]; -end - - -endmodule diff --git a/fpga/rtl/screen.sv b/fpga/rtl/screen.sv index 9c10593..7337704 100755 --- a/fpga/rtl/screen.sv +++ b/fpga/rtl/screen.sv @@ -7,9 +7,9 @@ module screen( input machine_t machine, input [2:0] border, - output reg [2:0] r, - output reg [2:0] g, - output reg [1:0] b, + output reg [5:0] r, + output reg [5:0] g, + output reg [5:0] b, output reg vsync, output reg hsync, output reg csync, @@ -287,14 +287,20 @@ always @(posedge clk28) begin if (blank) {g, r, b} = 0; else if (up_en) begin - g = pixel? up_ink0[7:5] : up_paper0[7:5]; - r = pixel? up_ink0[4:2] : up_paper0[4:2]; - b = pixel? up_ink0[1:0] : up_paper0[1:0]; + g[5:3] = pixel? up_ink0[7:5] : up_paper0[7:5]; + r[5:3] = pixel? up_ink0[4:2] : up_paper0[4:2]; + b[5:4] = pixel? up_ink0[1:0] : up_paper0[1:0]; + g[2:0] = g[5:3]; + r[2:0] = r[5:3]; + b[3:0] = {b[5:4], b[5:4]}; end else begin - {g[2], r[2], b[1]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3]; - {g[1], r[1], b[0]} = {g[2] & attr[6], r[2] & attr[6], b[1] & attr[6]}; - {g[0], r[0]} = {g[2], r[2]}; + {g[5], r[5], b[5]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3]; + {g[4], r[4], b[4]} = {g[5], r[5], b[5]}; + {g[3], r[3], b[3]} = attr[6]? {g[5], r[5], b[5]} : 3'b000; + {g[2], r[2], b[2]} = {g[3], r[3], b[3]}; + {g[1], r[1], b[1]} = {g[3], r[3], b[3]}; + {g[0], r[0], b[0]} = {g[3], r[3], b[3]}; end end diff --git a/fpga/rtl/top.sv b/fpga/rtl/top.sv index 49f1142..4ee73cd 100755 --- a/fpga/rtl/top.sv +++ b/fpga/rtl/top.sv @@ -22,9 +22,8 @@ module zx_ula( output reg n_int, output n_nmi, - output reg [5:0] luma, - output reg [2:0] chroma, - output reg csync, + output [7:0] composite, + input [1:0] reserv, output snd_l, output snd_r, @@ -41,10 +40,15 @@ module zx_ula( /* CLOCK */ wire clk28 = clk_in; -wire clk40; -wire clk20; +wire clk168; wire rst_n; -pll pll0(.inclk0(clk_in), .c0(clk40), .c1(clk20), .locked(rst_n)); +pll pll0(.inclk0(clk_in), .c0(clk168), .locked(rst_n)); +reg [1:0] clk168_en42_cnt = 0; +reg clk168_en42; +always @(posedge clk168) begin + clk168_en42 <= clk168_en42_cnt == 2'b00; + clk168_en42_cnt <= clk168_en42_cnt + 1'b1; +end /* SHARED DEFINITIONS */ @@ -104,9 +108,8 @@ end /* SCREEN CONTROLLER */ wire blink; wire [2:0] screen_border = {border[2] ^ ~sd_cs, border[1] ^ magic_beeper, border[0]}; -wire [2:0] r, g; -wire [1:0] b; -wire hsync; +wire [5:0] r, g, b; +wire hsync, vsync, csync0; wire screen_contention, port_ff_active; wire [14:0] screen_addr; wire [5:0] up_ink_addr, up_paper_addr; @@ -124,8 +127,8 @@ screen screen0( .r(r), .g(g), .b(b), - .csync(csync), - .vsync(), + .csync(csync0), + .vsync(vsync), .hsync(hsync), .fetch_allow((!bus.iorq && !bus.mreq && !bus.m1) || bus.rfsh || clkwait), @@ -157,21 +160,17 @@ screen screen0( /* VIDEO OUTPUT */ -always @* - luma <= 2*r + 5*g + b; - -wire [2:0] chroma0; -chroma_gen #(.CLK_FREQ(40_000_000)) chroma_gen1( - .cg_clock(clk40), - .cg_rgb({|g,|r,|b}), - .cg_hsync(hsync), - .cg_enable(1'b1), - .cg_pnsel(1'b0), - .cg_out(chroma0) +vencode vencode( + .clk(clk168), + .clk_en(clk168_en42), + .videoR(r), + .videoG(g), + .videoB(b), + .videoHS_n(hsync), + .videoVS_n(vsync), + .videoPS_n(csync0), + .videoV(composite) ); -assign chroma[0] = (chroma0[1])? chroma0[0] : 1'bz; -assign chroma[1] = (chroma0[2])? chroma0[0] : 1'bz; -assign chroma[2] = (chroma0[2])? chroma0[0] : 1'bz; /* PS/2 KEYBOARD */ diff --git a/fpga/rtl/vencode.vhd b/fpga/rtl/vencode.vhd new file mode 100644 index 0000000..4500021 --- /dev/null +++ b/fpga/rtl/vencode.vhd @@ -0,0 +1,194 @@ +-- Speccy 2010 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vencode is + generic( + freq : integer := 42 + ); + + port( + clk : in std_logic; + clk_en : in std_logic; + + -- Video Input + videoR : in std_logic_vector(5 downto 0); + videoG : in std_logic_vector(5 downto 0); + videoB : in std_logic_vector(5 downto 0); + + videoHS_n : in std_logic; + videoVS_n : in std_logic; + videoPS_n : in std_logic; + + -- Video Output + videoY : out std_logic_vector(7 downto 0); + videoC : out std_logic_vector(7 downto 0); + videoV : out std_logic_vector(7 downto 0) + ); +end vencode; + +architecture rtl of vencode is + signal carrier : unsigned(7 downto 0); + + signal vcounter : unsigned(8 downto 0); + signal hcounter : unsigned(12 downto 0); + + signal burphase : unsigned(1 downto 0) := "00"; + + signal window_v : std_logic; + signal window_h : std_logic; + signal window_c : std_logic; + + signal ivideoR : unsigned(5 downto 0); + signal ivideoG : unsigned(5 downto 0); + signal ivideoB : unsigned(5 downto 0); + + signal Y1 : unsigned(13 downto 0); + signal Y2 : unsigned(13 downto 0); + signal Y3 : unsigned(13 downto 0); + signal U1 : unsigned(13 downto 0); + signal U2 : unsigned(13 downto 0); + signal U3 : unsigned(13 downto 0); + signal V1 : unsigned(13 downto 0); + signal V2 : unsigned(13 downto 0); + signal V3 : unsigned(13 downto 0); + + signal burstUV : signed(13 downto 0); + + signal prevY : signed(13 downto 0); + signal prevU : signed(13 downto 0); + signal prevV : signed(13 downto 0); + signal prevC : signed(23 downto 0); + + signal inSin : std_logic_vector(15 downto 0); + signal inCos : std_logic_vector(15 downto 0); + signal sin : signed(15 downto 0); + signal cos : signed(15 downto 0); + signal pcos : signed(15 downto 0); + + signal Um : signed(23 downto 0); + signal Vm : signed(23 downto 0); + + signal Y : signed(7 downto 0); + signal U : signed(7 downto 0); + signal V : signed(7 downto 0); + signal C : signed(7 downto 0); + + constant vref : signed(13 downto 0) := to_signed( 54, 8 ) & "000000"; + constant cent : signed(7 downto 0) := X"80"; + + component vencode_sin_cos + port( + clk : in std_logic; + phase : in std_logic_vector(7 downto 0); + sinus : out std_logic_vector(15 downto 0); + cosinus : out std_logic_vector(15 downto 0) + ); + end component; +begin + + process(clk, clk_en ) + variable carrierCounter : unsigned(15 downto 0); + begin + if ( clk'event and clk = '1' and clk_en = '1' ) then + carrierCounter := carrierCounter + 157; + if carrierCounter >= 6552 then + carrier <= carrier + 28; + carrierCounter := carrierCounter - 6552; + else + carrier <= carrier + 27; + end if; + end if; + end process; + + vencode_sin_cos0 : vencode_sin_cos port map( clk, std_logic_vector( carrier ), inSin, inCos ); + sin <= signed( inSin( 15 downto 0 ) ); + cos <= signed( inCos( 15 downto 0 ) ); + pcos <= cos when burphase(0) = '0' else -cos; + + process(clk, clk_en ) + variable ivideoVS_n : std_logic; + variable ivideoHS_n : std_logic; + begin + if ( clk'event and clk = '1' and clk_en = '1' ) then + Y <= prevY( 13 downto 6 ); + Um <= U * sin; + Vm <= V * pcos; + + videoY <= std_logic_vector( Y ); + videoC <= std_logic_vector( cent + C ); + videoV <= std_logic_vector( Y + C ); + + ivideoR <= unsigned( videoR ); + ivideoG <= unsigned( videoG ); + ivideoB <= unsigned( videoB ); + if ( videoHS_n = '0' and ivideoHS_n = '1' ) then + vcounter <= vcounter + 1; + burphase <= burphase - 1; + hcounter <= ( others => '0' ); + else + hcounter <= hcounter + 1; + end if; + + if (videoVS_n = '0' and ivideoVS_n = '1') then + vcounter <= ( others => '0' ); + end if; + + if ( vcounter = ( 10 - 1 ) ) then + window_v <= '1'; + elsif ( vcounter = ( 310 - 1 ) ) then + window_v <= '0'; + end if; + + if (hcounter = ( integer( 10.5 * real( freq ) ) - 1 ) ) then + window_h <= '1'; + elsif ( hcounter = ( integer( 62.5 * real( freq ) ) - 1 ) ) then + window_h <= '0'; + end if; + + if ( hcounter = ( integer( 5.6 * real( freq ) ) - 1 ) ) then + window_c <= '1'; + elsif ( hcounter = ( integer( 8.1 * real( freq ) ) - 1 ) ) then + window_c <= '0'; + end if; + + ivideoVS_n := videoVS_n; + ivideoHS_n := videoHS_n; + end if; + end process; + +-- Y = 0.299 R + 0.587 G + 0.114 B +-- U = -0.147 R - 0.289 G + 0.436 B +-- V = 0.615 R - 0.515 G - 0.100 B + + Y1 <= ( to_unsigned( 38, 8 ) * ivideoR ); + Y2 <= ( to_unsigned( 75, 8 ) * ivideoG ); + Y3 <= ( to_unsigned( 15, 8 ) * ivideoB ); + + U1 <= ( to_unsigned( 19, 8 ) * ivideoR ); + U2 <= ( to_unsigned( 37, 8 ) * ivideoG ); + U3 <= ( to_unsigned( 56, 8 ) * ivideoB ); + + V1 <= ( to_unsigned( 79, 8 ) * ivideoR ); + V2 <= ( to_unsigned( 66, 8 ) * ivideoG ); + V3 <= ( to_unsigned( 13, 8 ) * ivideoB ); + + prevY <= to_signed( 0, 14 ) when videoPS_n = '0' else + vref + signed( Y1 + Y2 + Y3 ) when ( window_h = '1' and window_v = '1' ) else + vref; + + burstUV <= to_signed( 32, 8 ) & "000000" when ( window_c = '1' and window_v = '1' ) else + ( others => '0' ); + prevU <= signed( U3 - U1 - U2 ) when ( window_h = '1' and window_v = '1' ) else + ( -burstUV ); + prevV <= signed( V1 - V2 - V3 ) when ( window_h = '1' and window_v = '1' ) else + ( burstUV ); + + U <= prevU( 13 downto 6 ); + V <= prevV( 13 downto 6 ); + prevC <= Um + Vm; + C <= prevC( 23 downto 16 ); + +end rtl; diff --git a/fpga/rtl/vencode_sin_cos.v b/fpga/rtl/vencode_sin_cos.v new file mode 100644 index 0000000..1d6e44b --- /dev/null +++ b/fpga/rtl/vencode_sin_cos.v @@ -0,0 +1,66 @@ +module vencode_sin_cos( + input clk, + input [7:0] phase, + output reg [15:0] sinus, + output reg [15:0] cosinus +); + reg [6:0] addr1, addr2; + wire [15:0] value1, value2; + vencode_sin_cos_rom vencode_sin_cos_rom0( + .address_a(addr1), + .address_b(addr2), + .clock(clk), + .q_a(value1), + .q_b(value2) + ); + + always @* begin + if(!phase[6]) + addr1 <= {1'b0, phase[5:0]}; + else + addr1 <= 7'h40 - {1'b0, phase[5:0]}; + if (!phase[7]) + sinus <= value1; + else + sinus <= -value1; + end + + wire [7:0] phase_cosinus = phase + 8'b01000000; + always @* begin + if(!phase_cosinus[6]) + addr2 <= {1'b0, phase_cosinus[5:0]}; + else + addr2 <= 7'h40 - {1'b0, phase_cosinus[5:0]}; + if (!phase_cosinus[7]) + cosinus <= value2; + else + cosinus <= -value2; + end +endmodule + + +module vencode_sin_cos_rom( + input [6:0] address_a, + input [6:0] address_b, + input clock, + output reg [15:0] q_a, + output reg [15:0] q_b +); + reg [15:0] rom [0:64]; + initial begin + rom <= '{ + 16'h0000, 16'h025b, 16'h04b6, 16'h0710, 16'h0969, 16'h0bc0, 16'h0e16, 16'h106a, + 16'h12bb, 16'h1509, 16'h1753, 16'h199b, 16'h1bde, 16'h1e1d, 16'h2057, 16'h228d, + 16'h24bd, 16'h26e7, 16'h290c, 16'h2b2a, 16'h2d41, 16'h2f51, 16'h315b, 16'h335c, + 16'h3556, 16'h3747, 16'h3930, 16'h3b10, 16'h3ce7, 16'h3eb4, 16'h4078, 16'h4232, + 16'h43e2, 16'h4587, 16'h4722, 16'h48b1, 16'h4a36, 16'h4bae, 16'h4d1c, 16'h4e7d, + 16'h4fd2, 16'h511b, 16'h5258, 16'h5387, 16'h54aa, 16'h55c0, 16'h56c8, 16'h57c4, + 16'h58b1, 16'h5991, 16'h5a63, 16'h5b28, 16'h5bde, 16'h5c86, 16'h5d1f, 16'h5dab, + 16'h5e28, 16'h5e96, 16'h5ef6, 16'h5f47, 16'h5f8a, 16'h5fbd, 16'h5fe2, 16'h5ff9, + 16'h6000 }; + end + always @(negedge clock) begin + q_a <= rom[address_a]; + q_b <= rom[address_b]; + end +endmodule diff --git a/fpga/syn/clocks.sdc b/fpga/syn/clocks.sdc index 1e56a80..1a5036d 100755 --- a/fpga/syn/clocks.sdc +++ b/fpga/syn/clocks.sdc @@ -1,13 +1,10 @@ -create_clock -period 28MHz -name {clk28} [get_ports {clk_in}] - -# clkcpu 3.5 or 7 MHz -create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk_in}] [get_registers {cpucontrol:cpucontrol0|clkcpu}] - -# hc0[2] 3.5 MHz -create_generated_clock -name {hc0_2} -divide_by 8 -source [get_ports {clk_in}] [get_registers {screen:screen0|hc0[2]}] - -# hsync len 4.7uS, 14e6/(1/4.7e-6) ~= 65 -create_generated_clock -name {hsync} -divide_by 126 -source [get_ports {clk_in}] [get_registers {screen:screen0|hsync}] - -derive_pll_clocks -derive_clocks -period 14MHz \ No newline at end of file +create_clock -period 28MHz -name {clk28} [get_ports {clk_in}] + +create_generated_clock -name {clkcpu} -divide_by 2 -source [get_ports {clk_in}] [get_registers {cpucontrol:cpucontrol0|clkcpu}] +create_generated_clock -name {hc0[1]} -divide_by 4 -source [get_ports {clk_in}] [get_registers {screen:screen0|hc0[1]}] + +derive_pll_clocks +derive_clocks -period 14MHz + +set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -setup 4 +set_multicycle_path -from {vencode:*|*} -to {vencode:*|*} -hold 3 diff --git a/fpga/syn/ip/pll.ppf b/fpga/syn/ip/pll.ppf index 96152fb..ab54226 100755 --- a/fpga/syn/ip/pll.ppf +++ b/fpga/syn/ip/pll.ppf @@ -1,11 +1,10 @@ - - - - - - - - - - - + + + + + + + + + + diff --git a/fpga/syn/ip/pll.v b/fpga/syn/ip/pll.v index 5d03e25..881bea6 100755 --- a/fpga/syn/ip/pll.v +++ b/fpga/syn/ip/pll.v @@ -1,335 +1,307 @@ -// megafunction wizard: %ALTPLL% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: altpll - -// ============================================================ -// File Name: pll.v -// Megafunction Name(s): -// altpll -// -// Simulation Library Files(s): -// altera_mf -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version -// ************************************************************ - - -//Copyright (C) 1991-2013 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module pll ( - inclk0, - c0, - c1, - locked); - - input inclk0; - output c0; - output c1; - output locked; - - wire [5:0] sub_wire0; - wire sub_wire2; - wire [0:0] sub_wire6 = 1'h0; - wire [0:0] sub_wire3 = sub_wire0[0:0]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; - wire locked = sub_wire2; - wire c0 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; - - altpll altpll_component ( - .inclk (sub_wire5), - .clk (sub_wire0), - .locked (sub_wire2), - .activeclock (), - .areset (1'b0), - .clkbad (), - .clkena ({6{1'b1}}), - .clkloss (), - .clkswitch (1'b0), - .configupdate (1'b0), - .enable0 (), - .enable1 (), - .extclk (), - .extclkena ({4{1'b1}}), - .fbin (1'b1), - .fbmimicbidir (), - .fbout (), - .fref (), - .icdrclk (), - .pfdena (1'b1), - .phasecounterselect ({4{1'b1}}), - .phasedone (), - .phasestep (1'b1), - .phaseupdown (1'b1), - .pllena (1'b1), - .scanaclr (1'b0), - .scanclk (1'b0), - .scanclkena (1'b1), - .scandata (1'b0), - .scandataout (), - .scandone (), - .scanread (1'b0), - .scanwrite (1'b0), - .sclkout0 (), - .sclkout1 (), - .vcooverrange (), - .vcounderrange ()); - defparam - altpll_component.clk0_divide_by = 7, - altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 10, - altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 7, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 5, - altpll_component.clk1_phase_shift = "0", - altpll_component.compensate_clock = "CLK0", - altpll_component.inclk0_input_frequency = 35714, - altpll_component.intended_device_family = "Cyclone", - altpll_component.invalid_lock_multiplier = 5, - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", - altpll_component.lpm_type = "altpll", - altpll_component.operation_mode = "NORMAL", - altpll_component.pll_type = "AUTO", - altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_UNUSED", - altpll_component.port_clkbad0 = "PORT_UNUSED", - altpll_component.port_clkbad1 = "PORT_UNUSED", - altpll_component.port_clkloss = "PORT_UNUSED", - altpll_component.port_clkswitch = "PORT_UNUSED", - altpll_component.port_configupdate = "PORT_UNUSED", - altpll_component.port_fbin = "PORT_UNUSED", - altpll_component.port_inclk0 = "PORT_USED", - altpll_component.port_inclk1 = "PORT_UNUSED", - altpll_component.port_locked = "PORT_USED", - altpll_component.port_pfdena = "PORT_UNUSED", - altpll_component.port_phasecounterselect = "PORT_UNUSED", - altpll_component.port_phasedone = "PORT_UNUSED", - altpll_component.port_phasestep = "PORT_UNUSED", - altpll_component.port_phaseupdown = "PORT_UNUSED", - altpll_component.port_pllena = "PORT_UNUSED", - altpll_component.port_scanaclr = "PORT_UNUSED", - altpll_component.port_scanclk = "PORT_UNUSED", - altpll_component.port_scanclkena = "PORT_UNUSED", - altpll_component.port_scandata = "PORT_UNUSED", - altpll_component.port_scandataout = "PORT_UNUSED", - altpll_component.port_scandone = "PORT_UNUSED", - altpll_component.port_scanread = "PORT_UNUSED", - altpll_component.port_scanwrite = "PORT_UNUSED", - altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk3 = "PORT_UNUSED", - altpll_component.port_clk4 = "PORT_UNUSED", - altpll_component.port_clk5 = "PORT_UNUSED", - altpll_component.port_clkena0 = "PORT_UNUSED", - altpll_component.port_clkena1 = "PORT_UNUSED", - altpll_component.port_clkena3 = "PORT_UNUSED", - altpll_component.port_clkena4 = "PORT_UNUSED", - altpll_component.port_clkena5 = "PORT_UNUSED", - altpll_component.port_extclk0 = "PORT_UNUSED", - altpll_component.port_extclk1 = "PORT_UNUSED", - altpll_component.port_extclk2 = "PORT_UNUSED", - altpll_component.port_extclk3 = "PORT_UNUSED", - altpll_component.valid_lock_multiplier = 1; - - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" -// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" -// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" -// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" -// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "4" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000" -// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" -// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "28.000" -// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" -// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" -// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" -// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" -// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" -// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" -// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" -// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -// Retrieval info: PRIVATE: SPREAD_USE STRING "0" -// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" -// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" -// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -// Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "7" -// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10" -// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "7" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "35714" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" -// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" -// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" -// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" -// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" -// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE -// Retrieval info: LIB_FILE: altera_mf -// Retrieval info: CBX_MODULE_PREFIX: ON +// megafunction wizard: %ALTPLL% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altpll + +// ============================================================ +// File Name: pll.v +// Megafunction Name(s): +// altpll +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pll ( + inclk0, + c0, + locked); + + input inclk0; + output c0; + output locked; + + wire [5:0] sub_wire0; + wire sub_wire2; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; + wire locked = sub_wire2; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; + + altpll altpll_component ( + .inclk (sub_wire4), + .clk (sub_wire0), + .locked (sub_wire2), + .activeclock (), + .areset (1'b0), + .clkbad (), + .clkena ({6{1'b1}}), + .clkloss (), + .clkswitch (1'b0), + .configupdate (1'b0), + .enable0 (), + .enable1 (), + .extclk (), + .extclkena ({4{1'b1}}), + .fbin (1'b1), + .fbmimicbidir (), + .fbout (), + .fref (), + .icdrclk (), + .pfdena (1'b1), + .phasecounterselect ({4{1'b1}}), + .phasedone (), + .phasestep (1'b1), + .phaseupdown (1'b1), + .pllena (1'b1), + .scanaclr (1'b0), + .scanclk (1'b0), + .scanclkena (1'b1), + .scandata (1'b0), + .scandataout (), + .scandone (), + .scanread (1'b0), + .scanwrite (1'b0), + .sclkout0 (), + .sclkout1 (), + .vcooverrange (), + .vcounderrange ()); + defparam + altpll_component.clk0_divide_by = 1, + altpll_component.clk0_duty_cycle = 50, + altpll_component.clk0_multiply_by = 6, + altpll_component.clk0_phase_shift = "0", + altpll_component.compensate_clock = "CLK0", + altpll_component.inclk0_input_frequency = 35714, + altpll_component.intended_device_family = "Cyclone", + altpll_component.invalid_lock_multiplier = 5, + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", + altpll_component.lpm_type = "altpll", + altpll_component.operation_mode = "NORMAL", + altpll_component.pll_type = "AUTO", + altpll_component.port_activeclock = "PORT_UNUSED", + altpll_component.port_areset = "PORT_UNUSED", + altpll_component.port_clkbad0 = "PORT_UNUSED", + altpll_component.port_clkbad1 = "PORT_UNUSED", + altpll_component.port_clkloss = "PORT_UNUSED", + altpll_component.port_clkswitch = "PORT_UNUSED", + altpll_component.port_configupdate = "PORT_UNUSED", + altpll_component.port_fbin = "PORT_UNUSED", + altpll_component.port_inclk0 = "PORT_USED", + altpll_component.port_inclk1 = "PORT_UNUSED", + altpll_component.port_locked = "PORT_USED", + altpll_component.port_pfdena = "PORT_UNUSED", + altpll_component.port_phasecounterselect = "PORT_UNUSED", + altpll_component.port_phasedone = "PORT_UNUSED", + altpll_component.port_phasestep = "PORT_UNUSED", + altpll_component.port_phaseupdown = "PORT_UNUSED", + altpll_component.port_pllena = "PORT_UNUSED", + altpll_component.port_scanaclr = "PORT_UNUSED", + altpll_component.port_scanclk = "PORT_UNUSED", + altpll_component.port_scanclkena = "PORT_UNUSED", + altpll_component.port_scandata = "PORT_UNUSED", + altpll_component.port_scandataout = "PORT_UNUSED", + altpll_component.port_scandone = "PORT_UNUSED", + altpll_component.port_scanread = "PORT_UNUSED", + altpll_component.port_scanwrite = "PORT_UNUSED", + altpll_component.port_clk0 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk3 = "PORT_UNUSED", + altpll_component.port_clk4 = "PORT_UNUSED", + altpll_component.port_clk5 = "PORT_UNUSED", + altpll_component.port_clkena0 = "PORT_UNUSED", + altpll_component.port_clkena1 = "PORT_UNUSED", + altpll_component.port_clkena3 = "PORT_UNUSED", + altpll_component.port_clkena4 = "PORT_UNUSED", + altpll_component.port_clkena5 = "PORT_UNUSED", + altpll_component.port_extclk0 = "PORT_UNUSED", + altpll_component.port_extclk1 = "PORT_UNUSED", + altpll_component.port_extclk2 = "PORT_UNUSED", + altpll_component.port_extclk3 = "PORT_UNUSED", + altpll_component.valid_lock_multiplier = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "4" +// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "168.000000" +// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "28.000" +// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0" +// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "168.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +// Retrieval info: PRIVATE: SPREAD_USE STRING "0" +// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6" +// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "35714" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone" +// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf +// Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/fpga/syn/zx_ula.qsf b/fpga/syn/zx_ula.qsf index 9fb43b5..343ce59 100755 --- a/fpga/syn/zx_ula.qsf +++ b/fpga/syn/zx_ula.qsf @@ -96,16 +96,16 @@ set_location_assignment PIN_4 -to va[12] set_location_assignment PIN_5 -to va[11] set_location_assignment PIN_20 -to ps2_dat set_location_assignment PIN_21 -to ps2_clk -set_location_assignment PIN_22 -to chroma[0] -set_location_assignment PIN_23 -to chroma[1] -set_location_assignment PIN_24 -to chroma[2] -set_location_assignment PIN_25 -to csync -set_location_assignment PIN_26 -to luma[5] -set_location_assignment PIN_27 -to luma[4] -set_location_assignment PIN_28 -to luma[3] -set_location_assignment PIN_29 -to luma[2] -set_location_assignment PIN_34 -to luma[1] -set_location_assignment PIN_35 -to luma[0] +set_location_assignment PIN_22 -to reserv[0] +set_location_assignment PIN_23 -to reserv[1] +set_location_assignment PIN_24 -to composite[0] +set_location_assignment PIN_25 -to composite[7] +set_location_assignment PIN_26 -to composite[6] +set_location_assignment PIN_27 -to composite[5] +set_location_assignment PIN_28 -to composite[4] +set_location_assignment PIN_29 -to composite[3] +set_location_assignment PIN_34 -to composite[2] +set_location_assignment PIN_35 -to composite[1] set_location_assignment PIN_36 -to snd_l set_location_assignment PIN_37 -to snd_r set_location_assignment PIN_38 -to sd_cd @@ -167,9 +167,10 @@ set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/magic.sv set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/divmmc.sv set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/cpucontrol.sv set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/memcontrol.sv -set_global_assignment -name VERILOG_FILE ../rtl/chroma_gen.v set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/turbosound.sv set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv +set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v +set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd set_global_assignment -name VERILOG_FILE ../rtl/ps2.v set_global_assignment -name VERILOG_FILE ../rtl/ps2_rxtx.v set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/common.sv diff --git a/fpga/tb/testbench_zx_ula.v b/fpga/tb/testbench_zx_ula.v index 6b2ba6f..0a03c5e 100644 --- a/fpga/tb/testbench_zx_ula.v +++ b/fpga/tb/testbench_zx_ula.v @@ -93,12 +93,7 @@ zx_ula zx_ula1( .sd_mosi_tape_out(sd_mosi_miso), .sd_miso_tape_in(sd_mosi_miso), .ps2_clk(), - .ps2_dat(), - .csync(), - .luma(), - .chroma(), - .snd_l(), - .snd_r() + .ps2_dat() ); diff --git a/pcb/rev.A/ERRATA.txt b/pcb/rev.A/ERRATA.txt index e4943f4..282effd 100644 --- a/pcb/rev.A/ERRATA.txt +++ b/pcb/rev.A/ERRATA.txt @@ -1,6 +1,5 @@ -- Incorrect Q1 pinout -- R7 should be 0 Ohm -- R14 should be 82 Ohm -- R19 should be 200 Ohm -- R20, R22, R25 should be ??? (TODO) Ohm - X1 - 28MHz +- R5 should be 200 +- R14 should be 0 +- R19 should be 200 +- do not install: R20, R21, R22, R23, R24, R25, C18, C19, Q1 diff --git a/pcb/rev.A/sizif-xxs.sch b/pcb/rev.A/sizif-xxs.sch index 045ca91..69401c7 100755 --- a/pcb/rev.A/sizif-xxs.sch +++ b/pcb/rev.A/sizif-xxs.sch @@ -3480,8 +3480,6 @@ Connection ~ 11725 2050 Wire Wire Line 11375 2050 11725 2050 NoConn ~ 11175 6475 -Text Notes 9700 3775 0 39 Italic 0 -R5 270\nR14 82\nR19 200\nR7 0 Wire Bus Line 4925 675 3225 675 $Comp @@ -3591,4 +3589,6 @@ Wire Bus Line 3600 3075 3600 6475 Wire Bus Line 625 675 625 4025 +Text Notes 9650 3950 0 39 Italic 0 +R5 200\nR14 0\nR19 200\n\ndo not install:\nR20, R21, R22,\nR23, R24, R25,\nC18, C19, Q1 $EndSCHEMATC