mirror of
https://github.com/UzixLS/zx-sizif-xxs.git
synced 2025-07-18 23:01:40 +03:00
e33bd97a7e
New one is borrowed from Speccy 2010 project. It's have a much, much better output quality in price of increased FPGA resources usage.
67 lines
2.0 KiB
Verilog
67 lines
2.0 KiB
Verilog
module vencode_sin_cos(
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input clk,
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input [7:0] phase,
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output reg [15:0] sinus,
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output reg [15:0] cosinus
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);
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reg [6:0] addr1, addr2;
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wire [15:0] value1, value2;
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vencode_sin_cos_rom vencode_sin_cos_rom0(
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.address_a(addr1),
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.address_b(addr2),
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.clock(clk),
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.q_a(value1),
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.q_b(value2)
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);
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always @* begin
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if(!phase[6])
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addr1 <= {1'b0, phase[5:0]};
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else
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addr1 <= 7'h40 - {1'b0, phase[5:0]};
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if (!phase[7])
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sinus <= value1;
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else
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sinus <= -value1;
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end
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wire [7:0] phase_cosinus = phase + 8'b01000000;
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always @* begin
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if(!phase_cosinus[6])
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addr2 <= {1'b0, phase_cosinus[5:0]};
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else
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addr2 <= 7'h40 - {1'b0, phase_cosinus[5:0]};
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if (!phase_cosinus[7])
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cosinus <= value2;
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else
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cosinus <= -value2;
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end
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endmodule
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module vencode_sin_cos_rom(
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input [6:0] address_a,
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input [6:0] address_b,
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input clock,
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output reg [15:0] q_a,
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output reg [15:0] q_b
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);
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reg [15:0] rom [0:64];
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initial begin
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rom <= '{
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16'h0000, 16'h025b, 16'h04b6, 16'h0710, 16'h0969, 16'h0bc0, 16'h0e16, 16'h106a,
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16'h12bb, 16'h1509, 16'h1753, 16'h199b, 16'h1bde, 16'h1e1d, 16'h2057, 16'h228d,
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16'h24bd, 16'h26e7, 16'h290c, 16'h2b2a, 16'h2d41, 16'h2f51, 16'h315b, 16'h335c,
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16'h3556, 16'h3747, 16'h3930, 16'h3b10, 16'h3ce7, 16'h3eb4, 16'h4078, 16'h4232,
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16'h43e2, 16'h4587, 16'h4722, 16'h48b1, 16'h4a36, 16'h4bae, 16'h4d1c, 16'h4e7d,
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16'h4fd2, 16'h511b, 16'h5258, 16'h5387, 16'h54aa, 16'h55c0, 16'h56c8, 16'h57c4,
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16'h58b1, 16'h5991, 16'h5a63, 16'h5b28, 16'h5bde, 16'h5c86, 16'h5d1f, 16'h5dab,
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16'h5e28, 16'h5e96, 16'h5ef6, 16'h5f47, 16'h5f8a, 16'h5fbd, 16'h5fe2, 16'h5ff9,
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16'h6000 };
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end
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always @(negedge clock) begin
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q_a <= rom[address_a];
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q_b <= rom[address_b];
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end
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endmodule
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