|
|
e952ec2b86
|
add pcb rev.A2
|
2025-03-29 22:53:39 +03:00 |
|
|
|
abc904c204
|
rename "out" -> "release"; merge 3d view into pdf
|
2025-03-29 22:53:38 +03:00 |
|
|
|
ee06137b9d
|
update pcb rev.A and rev.A1 errata
|
2025-01-28 21:25:53 +03:00 |
|
|
|
85656da5b8
|
update gs rom 1.05a -> 1.05b
|
2024-10-02 19:43:35 +03:00 |
|
|
|
cdcc768584
|
add quartus 2mb project revision (forgot to add within d11ef18c)
|
2024-10-02 19:39:59 +03:00 |
|
|
|
d11ef18cab
|
add 2mb pof file variant
|
2024-04-03 21:22:18 +03:00 |
|
|
|
1ee608e378
|
swap YM chips (fixes stellar.scl)
|
2024-01-25 20:16:32 +03:00 |
|
|
|
35bb9686b7
|
exclude port #FF from iorqge signal
|
2023-12-24 23:25:14 +03:00 |
|
|
|
548d6ef245
|
exclude ports #0F, #1F, #4F, #5F from iorqge signal
|
2023-12-24 23:24:50 +03:00 |
|
|
|
0023e1afc9
|
update errata for pcb rev.A and rev.A1
|
2023-09-09 11:20:28 +03:00 |
|
|
|
63a2324711
|
gs refactor
|
2023-08-19 23:06:15 +03:00 |
|
|
|
a696ecdf28
|
fix compatibility with NemoIDE
|
2023-03-26 22:10:33 +03:00 |
|
|
|
7e836fba8d
|
update readme
|
2023-03-13 11:38:11 +03:00 |
|
|
|
884f8308b0
|
cpld: add build option to support 2mb gs ram
|
2023-02-03 20:49:41 +03:00 |
|
|
|
4fe3fd7606
|
fix gs glitches with contended timings
|
2022-12-18 15:37:11 +03:00 |
|
|
|
bd57e87d4f
|
refactor gs register names
|
2022-12-18 14:21:01 +03:00 |
|
|
|
8733d015a4
|
general sound - 16mhz clock
|
2022-11-25 19:23:57 +03:00 |
|
|
|
ab9648caf2
|
add license
|
2022-11-19 11:14:51 +03:00 |
|
|
|
15cc1da745
|
add readme
|
2022-11-19 11:14:51 +03:00 |
|
|
|
66ca58d37a
|
add pcb rev.A1
|
2022-11-18 21:38:48 +03:00 |
|
|
|
d1af9dadbf
|
add testbench
|
2022-11-18 20:01:26 +03:00 |
|
|
|
ab320aa0d9
|
add gs rom
|
2022-11-18 20:00:50 +03:00 |
|
|
|
fc319bd685
|
update cpld firmware - finally working version
|
2022-11-15 20:44:01 +03:00 |
|
|
|
81513481fe
|
update pcb rev.A - final version; add errata
|
2022-11-10 21:12:30 +03:00 |
|
|
|
ede0a27ce7
|
update gitignore
|
2022-10-29 19:51:49 +03:00 |
|
|
|
cf5398377c
|
wip pcb rev.A
|
2022-08-14 22:01:41 +03:00 |
|
|
|
2f1024a29c
|
wip pcb rev.A
|
2022-07-02 20:21:29 +03:00 |
|
|
|
994cb042ad
|
wip pcb rev.A
|
2022-06-12 21:31:29 +03:00 |
|
|
|
9d544911c1
|
add cpld sources
|
2022-06-11 08:40:23 +03:00 |
|
|
|
1ad83b07a9
|
wip pcb rev.A
|
2022-06-11 08:37:13 +03:00 |
|
|
|
7b84a8d83a
|
wip pcb rev.A
|
2022-06-09 21:38:50 +03:00 |
|
|
|
b4dcc7f5f6
|
wip pcb rev.A
|
2022-06-08 21:07:27 +03:00 |
|
|
|
f1c3da1e5e
|
wip pcb rev.A
|
2022-06-06 22:33:22 +03:00 |
|
|
|
838afd89eb
|
wip pcb rev.A
|
2022-06-05 21:15:24 +03:00 |
|
|
|
9ba5afdd57
|
wip pcb rev.A
|
2022-06-03 22:33:15 +03:00 |
|
|
|
84da79f3a6
|
wip pcb rev.A
|
2022-06-02 22:40:15 +03:00 |
|
|
|
12b47f44d6
|
init
|
2022-06-02 22:19:22 +03:00 |
|
