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UzixLS
2021-06-14 10:13:12 +03:00
parent eb6f3c1463
commit baf2f9a348
18 changed files with 1308 additions and 1308 deletions
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28
fpga/rtl/common.sv
View File

@ -1,21 +1,21 @@
package common;
typedef enum { TIMINGS_PENT, TIMINGS_S128, TIMINGS_S48 } timings_t;
typedef enum { TURBO_NONE, TURBO_7, TURBO_14 = 3 } turbo_t;
typedef enum { TIMINGS_PENT, TIMINGS_S128, TIMINGS_S48 } timings_t;
typedef enum { TURBO_NONE, TURBO_7, TURBO_14 = 3 } turbo_t;
endpackage
interface cpu_bus();
wire [15:0] a;
wire [7:0] d;
wire iorq;
wire mreq;
wire m1;
wire rfsh;
wire rd;
wire wr;
wire [15:0] a;
wire [7:0] d;
wire iorq;
wire mreq;
wire m1;
wire rfsh;
wire rd;
wire wr;
reg [15:0] a_reg;
reg [7:0] d_reg;
wire ioreq;
wire memreq;
reg [15:0] a_reg;
reg [7:0] d_reg;
wire ioreq;
wire memreq;
endinterface

104
fpga/rtl/cpucontrol.sv
View File

@ -1,39 +1,39 @@
import common::*;
module cpucontrol(
input rst_n,
input clk28,
input clk14,
input clk7,
input clk35,
input rst_n,
input clk28,
input clk14,
input clk7,
input clk35,
cpu_bus bus,
cpu_bus bus,
input [8:0] vc,
input [8:0] hc,
input [2:0] rampage128,
input screen_loading,
input turbo_t turbo,
input timings_t timings,
input pause,
input ext_wait_cycle,
input init_done_in,
input [8:0] vc,
input [8:0] hc,
input [2:0] rampage128,
input screen_loading,
input turbo_t turbo,
input timings_t timings,
input pause,
input ext_wait_cycle,
input init_done_in,
output reg n_rstcpu,
output reg clkcpu,
output clkcpu_ck,
output clkwait,
output reg n_int,
output n_int_next,
output snow
output reg n_rstcpu,
output reg clkcpu,
output clkcpu_ck,
output clkwait,
output reg n_int,
output n_int_next,
output snow
);
/* CONTENTION */
logic mreq_delayed, iorq_delayed;
always @(posedge clkcpu)
mreq_delayed <= bus.mreq;
mreq_delayed <= bus.mreq;
always @(posedge clkcpu)
iorq_delayed <= bus.iorq;
iorq_delayed <= bus.iorq;
wire contention_mem_addr = bus.a[14] & (~bus.a[15] | (bus.a[15] & rampage128[0]));
wire contention_mem = iorq_delayed == 1'b0 && mreq_delayed == 1'b0 && contention_mem_addr;
wire contention_io = iorq_delayed == 1'b0 && bus.iorq;
@ -47,18 +47,18 @@ logic [2:0] turbo_wait;
wire turbo_wait_trig0 = bus.rd || bus.wr;
reg turbo_wait_trig1;
always @(posedge clk28) begin
turbo_wait_trig1 <= turbo_wait_trig0;
turbo_wait[0] <= turbo == TURBO_14 && turbo_wait_trig0 && !turbo_wait_trig1;
turbo_wait[1] <= turbo_wait[0] && (bus.iorq || ext_wait_cycle);
turbo_wait[2] <= turbo_wait[1];
turbo_wait_trig1 <= turbo_wait_trig0;
turbo_wait[0] <= turbo == TURBO_14 && turbo_wait_trig0 && !turbo_wait_trig1;
turbo_wait[1] <= turbo_wait[0] && (bus.iorq || ext_wait_cycle);
turbo_wait[2] <= turbo_wait[1];
end
logic clkcpu_prev;
assign clkcpu_ck = clkcpu && ! clkcpu_prev;
assign clkwait = pause || contention || (|turbo_wait);
always @(negedge clk28) begin
clkcpu_prev <= clkcpu;
clkcpu <= clkwait? clkcpu : (turbo == TURBO_14)? clk14 : (turbo == TURBO_7)? clk7 : clk35;
clkcpu_prev <= clkcpu;
clkcpu <= clkwait? clkcpu : (turbo == TURBO_14)? clk14 : (turbo == TURBO_7)? clk7 : clk35;
end
@ -70,36 +70,36 @@ localparam INT_H_S128 = 450;
localparam INT_V_PENT = 239;
localparam INT_H_PENT = 316;
wire int_begin =
(timings == TIMINGS_PENT)?
vc == INT_V_PENT && hc == INT_H_PENT :
(timings == TIMINGS_S128)?
vc == INT_V_S128 && hc == INT_H_S128 :
// 48K
vc == INT_V_S48 && hc == INT_H_S48 ;
(timings == TIMINGS_PENT)?
vc == INT_V_PENT && hc == INT_H_PENT :
(timings == TIMINGS_S128)?
vc == INT_V_S128 && hc == INT_H_S128 :
// 48K
vc == INT_V_S48 && hc == INT_H_S48 ;
logic [4:0] int_cnt;
assign n_int_next = (|int_cnt)? 1'b0 : 1'b1;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
int_cnt <= 0;
n_int <= 1'b1;
end
else begin
if (clkcpu_ck)
n_int <= n_int_next;
if ((int_cnt != 0 && clkcpu_ck) || (int_cnt == 0 && int_begin))
int_cnt <= int_cnt + 1'b1;
end
if (!rst_n) begin
int_cnt <= 0;
n_int <= 1'b1;
end
else begin
if (clkcpu_ck)
n_int <= n_int_next;
if ((int_cnt != 0 && clkcpu_ck) || (int_cnt == 0 && int_begin))
int_cnt <= int_cnt + 1'b1;
end
end
/* RESET */
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
n_rstcpu <= 0;
else if (!init_done_in)
n_rstcpu <= 0;
else if (vc[0])
n_rstcpu <= 1'b1;
if (!rst_n)
n_rstcpu <= 0;
else if (!init_done_in)
n_rstcpu <= 0;
else if (vc[0])
n_rstcpu <= 1'b1;
end

184
fpga/rtl/divmmc.sv
View File

@ -1,63 +1,63 @@
module divmmc(
input rst_n,
input clk28,
input ck14,
input ck7,
input en,
input rst_n,
input clk28,
input ck14,
input ck7,
input en,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
input sd_cd,
input sd_miso,
output sd_mosi,
output reg sd_sck,
output reg sd_cs,
input sd_cd,
input sd_miso,
output sd_mosi,
output reg sd_sck,
output reg sd_cs,
input port_dffd_d4,
input port_1ffd_d0,
input magic_mode,
input magic_map,
input port_dffd_d4,
input port_1ffd_d0,
input magic_mode,
input magic_map,
output reg [3:0] div_page,
output div_map,
output div_ram,
output div_ramwr_mask,
output div_wait
output reg [3:0] div_page,
output div_map,
output div_ram,
output div_ramwr_mask,
output div_wait
);
reg div_automap, div_automap_next;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
div_automap_next <= 0;
div_automap <= 0;
end
else if (bus.m1 && bus.memreq && magic_map == 0) begin
if (sd_cd || !en || port_dffd_d4 || port_1ffd_d0) begin
div_automap_next <= 0;
end
else if (bus.a_reg[15:3] == 13'h3FF) begin // exit vectors 1FF8-1FFF
div_automap_next <= 0;
end
else if (
bus.a_reg == 16'h0000 || // power-on/reset/rst0/software restart
bus.a_reg == 16'h0008 || // syntax error
bus.a_reg == 16'h0038 || // im1 interrupt/rst #38
(bus.a_reg == 16'h0066 && !magic_mode) || // nmi routine
bus.a_reg == 16'h04C6 || // tape save routine
bus.a_reg == 16'h0562 // tape load and verify routine
) begin
div_automap_next <= 1'b1;
end
else if (bus.a_reg[15:8] == 8'h3D) begin // tr-dos mapping area
div_automap_next <= 1'b1;
div_automap <= 1'b1;
end
end
else if (!bus.m1) begin
div_automap <= div_automap_next;
end
if (!rst_n) begin
div_automap_next <= 0;
div_automap <= 0;
end
else if (bus.m1 && bus.memreq && magic_map == 0) begin
if (sd_cd || !en || port_dffd_d4 || port_1ffd_d0) begin
div_automap_next <= 0;
end
else if (bus.a_reg[15:3] == 13'h3FF) begin // exit vectors 1FF8-1FFF
div_automap_next <= 0;
end
else if (
bus.a_reg == 16'h0000 || // power-on/reset/rst0/software restart
bus.a_reg == 16'h0008 || // syntax error
bus.a_reg == 16'h0038 || // im1 interrupt/rst #38
(bus.a_reg == 16'h0066 && !magic_mode) || // nmi routine
bus.a_reg == 16'h04C6 || // tape save routine
bus.a_reg == 16'h0562 // tape load and verify routine
) begin
div_automap_next <= 1'b1;
end
else if (bus.a_reg[15:8] == 8'h3D) begin // tr-dos mapping area
div_automap_next <= 1'b1;
div_automap <= 1'b1;
end
end
else if (!bus.m1) begin
div_automap <= div_automap_next;
end
end
reg spi_rd;
@ -66,71 +66,71 @@ wire port_e3_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hE3;
wire port_e7_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hE7;
wire port_eb_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hEB;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
spi_rd <= 0;
div_page <= 0;
div_mapram <= 0;
div_conmem <= 0;
sd_cs <= 1'b1;
end
else begin
spi_rd <= port_eb_cs && bus.rd;
if (port_e3_cs && bus.wr) begin
div_page <= bus.d_reg[3:0];
div_mapram <= bus.d_reg[6] | div_mapram;
div_conmem <= bus.d_reg[7];
end
if (port_e7_cs && bus.wr) begin
sd_cs <= bus.d_reg[0];
end
end
if (!rst_n) begin
spi_rd <= 0;
div_page <= 0;
div_mapram <= 0;
div_conmem <= 0;
sd_cs <= 1'b1;
end
else begin
spi_rd <= port_eb_cs && bus.rd;
if (port_e3_cs && bus.wr) begin
div_page <= bus.d_reg[3:0];
div_mapram <= bus.d_reg[6] | div_mapram;
div_conmem <= bus.d_reg[7];
end
if (port_e7_cs && bus.wr) begin
sd_cs <= bus.d_reg[0];
end
end
end
reg [3:0] spi_cnt;
wire spi_cnt_en = ~spi_cnt[3] | spi_cnt[2] | spi_cnt[1] | spi_cnt[0];
assign div_wait = ~spi_cnt[3];
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
spi_cnt <= 0;
else if (port_eb_cs && (bus.rd || bus.wr))
spi_cnt <= 4'b1110;
else if (spi_cnt_en && ck7)
spi_cnt <= spi_cnt + 1'b1;
if (!rst_n)
spi_cnt <= 0;
else if (port_eb_cs && (bus.rd || bus.wr))
spi_cnt <= 4'b1110;
else if (spi_cnt_en && ck7)
spi_cnt <= spi_cnt + 1'b1;
end
reg spi_mosi_en;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
spi_mosi_en <= 0;
else if (port_eb_cs && bus.wr)
spi_mosi_en <= 1'b1;
else if (!spi_cnt_en)
spi_mosi_en <= 0;
if (!rst_n)
spi_mosi_en <= 0;
else if (port_eb_cs && bus.wr)
spi_mosi_en <= 1'b1;
else if (!spi_cnt_en)
spi_mosi_en <= 0;
end
reg [7:0] spi_reg;
assign sd_mosi = spi_mosi_en? spi_reg[7] : 1'b1;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
spi_reg <= 0;
else if (port_eb_cs && bus.wr)
spi_reg <= bus.d_reg;
else if (spi_cnt[3] == 1'b0 && ck7)
spi_reg[7:0] <= {spi_reg[6:0], sd_miso};
if (!rst_n)
spi_reg <= 0;
else if (port_eb_cs && bus.wr)
spi_reg <= bus.d_reg;
else if (spi_cnt[3] == 1'b0 && ck7)
spi_reg[7:0] <= {spi_reg[6:0], sd_miso};
end
always @(posedge clk28) begin
if (ck14)
sd_sck <= ~sd_sck & ~spi_cnt[3];
if (ck14)
sd_sck <= ~sd_sck & ~spi_cnt[3];
end
assign div_map = div_automap | div_conmem;
assign div_ram = (div_conmem == 1 && bus.a[13] == 1) ||
(div_automap == 1 && bus.a[13] == 1) ||
(div_conmem == 0 && div_automap == 1 && div_mapram == 1);
(div_automap == 1 && bus.a[13] == 1) ||
(div_conmem == 0 && div_automap == 1 && div_mapram == 1);
assign div_ramwr_mask = bus.a[15] == 0 && bus.a[14] == 0 &&
(bus.a[13] == 0 || div_page == 4'b0011) && div_conmem == 0 && div_automap == 1 && div_mapram == 1;
(bus.a[13] == 0 || div_page == 4'b0011) && div_conmem == 0 && div_automap == 1 && div_mapram == 1;
assign d_out_active = spi_rd;
assign d_out = spi_reg;

148
fpga/rtl/magic.sv
View File

@ -1,28 +1,28 @@
import common::*;
module magic(
input rst_n,
input clk28,
input rst_n,
input clk28,
cpu_bus bus,
input n_int,
input n_int_next,
output n_nmi,
cpu_bus bus,
input n_int,
input n_int_next,
output n_nmi,
input magic_button,
input magic_button,
output logic magic_mode,
output logic magic_map,
output magic_active_next,
output logic magic_mode,
output logic magic_map,
output magic_active_next,
output logic extlock,
output logic magic_beeper,
output timings_t timings,
output turbo_t turbo,
output logic joy_sinclair,
output logic rom_plus3,
output logic rom_alt48,
output logic ay_abc,
output logic ay_mono
output logic extlock,
output logic magic_beeper,
output timings_t timings,
output turbo_t turbo,
output logic joy_sinclair,
output logic rom_plus3,
output logic rom_alt48,
output logic ay_abc,
output logic ay_mono
);
assign magic_active_next = magic_button;
@ -30,68 +30,68 @@ logic magic_unmap_next;
logic magic_map_next;
assign n_nmi = magic_mode? 1'b0 : 1'b1;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
magic_mode <= 0;
magic_map <= 0;
magic_unmap_next <= 0;
magic_map_next <= 0;
end
else begin
if (magic_button == 1'b1 && n_int == 1'b1 && n_int_next == 1'b0)
magic_mode <= 1'b1;
if (!rst_n) begin
magic_mode <= 0;
magic_map <= 0;
magic_unmap_next <= 0;
magic_map_next <= 0;
end
else begin
if (magic_button == 1'b1 && n_int == 1'b1 && n_int_next == 1'b0)
magic_mode <= 1'b1;
if (magic_map && bus.memreq && bus.rd && bus.a_reg == 16'hf000 && !magic_map_next) begin
magic_unmap_next <= 1'b1;
magic_mode <= 1'b0;
end
else if (magic_map && bus.memreq && bus.rd && bus.a_reg == 16'hf008) begin
magic_unmap_next <= 1'b1;
magic_map_next <= 1'b1;
end
else if (magic_unmap_next && !bus.memreq) begin
magic_map <= 1'b0;
magic_unmap_next <= 1'b0;
end
else if (magic_mode && bus.m1 && bus.memreq && (bus.a_reg == 16'h0066 || magic_map_next)) begin
magic_map <= 1'b1;
magic_map_next <= 1'b0;
end
end
if (magic_map && bus.memreq && bus.rd && bus.a_reg == 16'hf000 && !magic_map_next) begin
magic_unmap_next <= 1'b1;
magic_mode <= 1'b0;
end
else if (magic_map && bus.memreq && bus.rd && bus.a_reg == 16'hf008) begin
magic_unmap_next <= 1'b1;
magic_map_next <= 1'b1;
end
else if (magic_unmap_next && !bus.memreq) begin
magic_map <= 1'b0;
magic_unmap_next <= 1'b0;
end
else if (magic_mode && bus.m1 && bus.memreq && (bus.a_reg == 16'h0066 || magic_map_next)) begin
magic_map <= 1'b1;
magic_map_next <= 1'b0;
end
end
end
/* MAGIC CONFIG */
wire config_cs = magic_map && bus.ioreq && bus.a_reg[7:0] == 8'hff;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
magic_beeper <= 0;
extlock <= 0;
timings <= TIMINGS_PENT;
turbo <= TURBO_NONE;
ay_abc <= 1'b1;
ay_mono <= 0;
rom_plus3 <= 0;
rom_alt48 <= 0;
joy_sinclair <= 0;
end
else if (config_cs && bus.wr) begin
if (bus.a_reg[15:12] == 4'h0)
magic_beeper <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h1)
extlock <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h2)
timings <= timings_t'(bus.d_reg[1:0]);
if (bus.a_reg[15:12] == 4'h3)
turbo <= turbo_t'(bus.d_reg[1:0]);
if (bus.a_reg[15:12] == 4'h4)
{ay_mono, ay_abc} <= bus.d_reg[1:0];
if (bus.a_reg[15:12] == 4'h5)
rom_plus3 <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h6)
rom_alt48 <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h7)
joy_sinclair <= bus.d_reg[0];
end
if (!rst_n) begin
magic_beeper <= 0;
extlock <= 0;
timings <= TIMINGS_PENT;
turbo <= TURBO_NONE;
ay_abc <= 1'b1;
ay_mono <= 0;
rom_plus3 <= 0;
rom_alt48 <= 0;
joy_sinclair <= 0;
end
else if (config_cs && bus.wr) begin
if (bus.a_reg[15:12] == 4'h0)
magic_beeper <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h1)
extlock <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h2)
timings <= timings_t'(bus.d_reg[1:0]);
if (bus.a_reg[15:12] == 4'h3)
turbo <= turbo_t'(bus.d_reg[1:0]);
if (bus.a_reg[15:12] == 4'h4)
{ay_mono, ay_abc} <= bus.d_reg[1:0];
if (bus.a_reg[15:12] == 4'h5)
rom_plus3 <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h6)
rom_alt48 <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h7)
joy_sinclair <= bus.d_reg[0];
end
end
endmodule

76
fpga/rtl/mixer.sv
View File

@ -1,26 +1,26 @@
module mixer(
input rst_n,
input clk28,
input rst_n,
input clk28,
input beeper,
input tape_out,
input tape_in,
input [7:0] ay_a0,
input [7:0] ay_b0,
input [7:0] ay_c0,
input [7:0] ay_a1,
input [7:0] ay_b1,
input [7:0] ay_c1,
input [7:0] sd_l0,
input [7:0] sd_l1,
input [7:0] sd_r0,
input [7:0] sd_r1,
input beeper,
input tape_out,
input tape_in,
input [7:0] ay_a0,
input [7:0] ay_b0,
input [7:0] ay_c0,
input [7:0] ay_a1,
input [7:0] ay_b1,
input [7:0] ay_c1,
input [7:0] sd_l0,
input [7:0] sd_l1,
input [7:0] sd_r0,
input [7:0] sd_r1,
input ay_abc,
input ay_mono,
input ay_abc,
input ay_mono,
output dac_l,
output dac_r
output dac_l,
output dac_r
);
localparam WIDTH = 11;
@ -29,28 +29,28 @@ reg [WIDTH:0] dac_l_cnt, dac_r_cnt;
assign dac_l = dac_l_cnt[WIDTH];
assign dac_r = dac_r_cnt[WIDTH];
wire [WIDTH-1:0] dac_next_l =
sd_l0 + sd_l1 +
ay_a0 + ay_b0 +
ay_a1 + ay_b1 +
{beeper, tape_out, tape_in, 6'b000000}
;
wire [WIDTH-1:0] dac_next_l =
sd_l0 + sd_l1 +
ay_a0 + ay_b0 +
ay_a1 + ay_b1 +
{beeper, tape_out, tape_in, 6'b000000}
;
wire [WIDTH-1:0] dac_next_r =
sd_r0 + sd_r1 +
ay_b0 + ay_c0 +
ay_b1 + ay_c1 +
{beeper, tape_out, tape_in, 6'b000000}
;
sd_r0 + sd_r1 +
ay_b0 + ay_c0 +
ay_b1 + ay_c1 +
{beeper, tape_out, tape_in, 6'b000000}
;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
dac_l_cnt <= 0;
dac_r_cnt <= 0;
end
else begin
dac_l_cnt <= dac_l_cnt[WIDTH-1:0] + dac_next_l;
dac_r_cnt <= dac_r_cnt[WIDTH-1:0] + dac_next_r;
end
if (!rst_n) begin
dac_l_cnt <= 0;
dac_r_cnt <= 0;
end
else begin
dac_l_cnt <= dac_l_cnt[WIDTH-1:0] + dac_next_l;
dac_r_cnt <= dac_r_cnt[WIDTH-1:0] + dac_next_r;
end
end
endmodule

184
fpga/rtl/ports.sv
View File

@ -1,46 +1,46 @@
import common::*;
module ports(
input rst_n,
input clk28,
input en_128k,
input en_plus3,
input en_profi,
input en_kempston,
input en_sinclair,
input rst_n,
input clk28,
input en_128k,
input en_plus3,
input en_profi,
input en_kempston,
input en_sinclair,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
input clkcpu_ck,
input timings_t timings,
input screen_loading,
input [7:0] attr_next,
input [4:0] kd,
input [7:0] kempston_data,
input magic_active_next,
input tape_in,
input clkcpu_ck,
input timings_t timings,
input screen_loading,
input [7:0] attr_next,
input [4:0] kd,
input [7:0] kempston_data,
input magic_active_next,
input tape_in,
output reg tape_out,
output reg beeper,
output reg [2:0] border,
output reg screen_page,
output reg rompage128,
output reg [2:0] rampage128,
output reg [3:0] rampage_ext,
output reg [2:0] port_1ffd,
output reg port_dffd_d3,
output reg port_dffd_d4
output reg tape_out,
output reg beeper,
output reg [2:0] border,
output reg screen_page,
output reg rompage128,
output reg [2:0] rampage128,
output reg [3:0] rampage_ext,
output reg [2:0] port_1ffd,
output reg port_dffd_d3,
output reg port_dffd_d4
);
/* PORT #FF */
wire [7:0] port_ff_data = attr_next;
reg port_ff_rd;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
port_ff_rd <= 0;
else
port_ff_rd <= bus.rd && bus.ioreq && (timings != TIMINGS_PENT || bus.a_reg[7:0] == 8'hFF) && screen_loading;
if (!rst_n)
port_ff_rd <= 0;
else
port_ff_rd <= bus.rd && bus.ioreq && (timings != TIMINGS_PENT || bus.a_reg[7:0] == 8'hFF) && screen_loading;
end
@ -48,39 +48,39 @@ end
wire port_fe_cs = bus.ioreq && bus.a_reg[0] == 0;
reg port_fe_rd;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
port_fe_rd <= 0;
else
port_fe_rd <= port_fe_cs && bus.rd;
if (!rst_n)
port_fe_rd <= 0;
else
port_fe_rd <= port_fe_cs && bus.rd;
end
reg [4:0] kd0;
wire [7:0] port_fe_data = {~magic_active_next, tape_in, 1'b1, kd0};
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
beeper <= 0;
tape_out <= 0;
border <= 0;
end
else if (port_fe_cs && bus.wr && clkcpu_ck) begin // clkcpu_ck to synchronize border
beeper <= bus.d_reg[4];
tape_out <= bus.d_reg[3];
border <= bus.d_reg[2:0];
end
if (!rst_n) begin
beeper <= 0;
tape_out <= 0;
border <= 0;
end
else if (port_fe_cs && bus.wr && clkcpu_ck) begin // clkcpu_ck to synchronize border
beeper <= bus.d_reg[4];
tape_out <= bus.d_reg[3];
border <= bus.d_reg[2:0];
end
end
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
kd0 <= 5'b11111;
end
else if (en_sinclair) begin
kd0 <= kd
& (bus.a_reg[12] == 0? {~kempston_data[1], ~kempston_data[0], ~kempston_data[2], ~kempston_data[3], ~kempston_data[4]} : 5'b11111) // 6-0 keys
& (bus.a_reg[15] == 0? {1'b1, ~kempston_data[6], ~kempston_data[5], 2'b11} : 5'b11111 ) ; // b-space keys
end
else begin
kd0 <= kd;
end
if (!rst_n) begin
kd0 <= 5'b11111;
end
else if (en_sinclair) begin
kd0 <= kd
& (bus.a_reg[12] == 0? {~kempston_data[1], ~kempston_data[0], ~kempston_data[2], ~kempston_data[3], ~kempston_data[4]} : 5'b11111) // 6-0 keys
& (bus.a_reg[15] == 0? {1'b1, ~kempston_data[6], ~kempston_data[5], 2'b11} : 5'b11111 ) ; // b-space keys
end
else begin
kd0 <= kd;
end
end
@ -88,66 +88,66 @@ end
wire port_7ffd_cs = en_128k && bus.ioreq && bus.a_reg[1] == 0 && bus.a_reg[15] == 0 && (bus.a_reg[14] == 1'b1 || !en_plus3);
reg lock_7ffd;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
rampage128 <= 0;
screen_page <= 0;
rompage128 <= 0;
lock_7ffd <= 0;
end
else if (port_7ffd_cs && bus.wr && (lock_7ffd == 0 || port_dffd_d4 == 1'b1)) begin
rampage128 <= bus.d_reg[2:0];
screen_page <= bus.d_reg[3];
rompage128 <= bus.d_reg[4];
lock_7ffd <= bus.d_reg[5];
end
if (!rst_n) begin
rampage128 <= 0;
screen_page <= 0;
rompage128 <= 0;
lock_7ffd <= 0;
end
else if (port_7ffd_cs && bus.wr && (lock_7ffd == 0 || port_dffd_d4 == 1'b1)) begin
rampage128 <= bus.d_reg[2:0];
screen_page <= bus.d_reg[3];
rompage128 <= bus.d_reg[4];
lock_7ffd <= bus.d_reg[5];
end
end
/* PORT #DFFD */
wire port_dffd_cs = en_profi && bus.ioreq && bus.a_reg == 16'hDFFD;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
rampage_ext <= 0;
port_dffd_d3 <= 0;
port_dffd_d4 <= 0;
end
else if (port_dffd_cs && bus.wr) begin
rampage_ext <= bus.d_reg[2:0];
port_dffd_d3 <= bus.d_reg[3];
port_dffd_d4 <= bus.d_reg[4];
end
if (!rst_n) begin
rampage_ext <= 0;
port_dffd_d3 <= 0;
port_dffd_d4 <= 0;
end
else if (port_dffd_cs && bus.wr) begin
rampage_ext <= bus.d_reg[2:0];
port_dffd_d3 <= bus.d_reg[3];
port_dffd_d4 <= bus.d_reg[4];
end
end
/* PORT #1FFD */
wire port_1ffd_cs = en_plus3 && bus.ioreq && bus.a_reg == 16'h1FFD;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
port_1ffd <= 0;
end
else if (port_1ffd_cs && bus.wr) begin
port_1ffd <= bus.d_reg[2:0];
end
if (!rst_n) begin
port_1ffd <= 0;
end
else if (port_1ffd_cs && bus.wr) begin
port_1ffd <= bus.d_reg[2:0];
end
end
/* KEMPSTON */
reg kempston_rd;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
kempston_rd <= 0;
else
kempston_rd <= en_kempston && bus.ioreq && bus.rd && bus.a_reg[7:5] == 3'b000;
if (!rst_n)
kempston_rd <= 0;
else
kempston_rd <= en_kempston && bus.ioreq && bus.rd && bus.a_reg[7:5] == 3'b000;
end
/* BUS CONTROLLER */
assign d_out_active = port_fe_rd | port_ff_rd | kempston_rd;
assign d_out =
assign d_out =
kempston_rd? kempston_data :
port_fe_rd? port_fe_data :
port_ff_data ;
port_fe_rd? port_fe_data :
port_ff_data ;
endmodule

298
fpga/rtl/ps2.v
View File

@ -1,26 +1,26 @@
`include "ps2_codes.vh"
module ps2#(
parameter CLK_FREQ
) (
input rst_n,
input clk,
input ps2_clk_in,
input ps2_dat_in,
output ps2_clk_out,
output ps2_dat_out,
input [7:0] zxkb_addr,
output reg [4:0] zxkb_data,
output reg key_magic,
output reg key_reset,
output reg key_pause,
output reg joy_up,
output reg joy_down,
output reg joy_left,
output reg joy_right,
output reg joy_fire
parameter CLK_FREQ
) (
input rst_n,
input clk,
input ps2_clk_in,
input ps2_dat_in,
output ps2_clk_out,
output ps2_dat_out,
input [7:0] zxkb_addr,
output reg [4:0] zxkb_data,
output reg key_magic,
output reg key_reset,
output reg key_pause,
output reg joy_up,
output reg joy_down,
output reg joy_left,
output reg joy_right,
output reg joy_fire
);
@ -28,15 +28,15 @@ reg rxdone;
reg rxerr;
reg [7:0] rxbyte;
ps2_rxtx #(.CLK_FREQ(CLK_FREQ)) ps2_rxtx0(
.rst_n(rst_n),
.clk(clk),
.ps2_clk_in(ps2_clk_in),
.ps2_dat_in(ps2_dat_in),
.ps2_clk_out(ps2_clk_out),
.ps2_dat_out(ps2_dat_out),
.dataout(rxbyte),
.dataout_valid(rxdone),
.dataout_error(rxerr)
.rst_n(rst_n),
.clk(clk),
.ps2_clk_in(ps2_clk_in),
.ps2_dat_in(ps2_dat_in),
.ps2_clk_out(ps2_clk_out),
.ps2_dat_out(ps2_dat_out),
.dataout(rxbyte),
.dataout_valid(rxdone),
.dataout_error(rxerr)
);
@ -51,120 +51,120 @@ reg key2_alt, key2_del;
reg is_press;
reg is_ext;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
is_press <= 1'b1;
is_ext <= 0;
key_magic <= 0;
key_pause <= 0;
{joy_up, joy_down, joy_left, joy_right, joy_fire} <= 0;
{key2_a, key2_b, key2_c, key2_d, key2_e, key2_f, key2_g, key2_h, key2_i, key2_j, key2_k, key2_l, key2_m, key2_n} <= 0;
{key2_o, key2_p, key2_q, key2_r, key2_s, key2_t, key2_u, key2_v, key2_w, key2_x, key2_y, key2_z, key2_0, key2_1} <= 0;
{key2_2, key2_3, key2_4, key2_5, key2_6, key2_7, key2_8, key2_9, key2_space, key2_enter, key2_l_shift, key2_r_shift} <= 0;
{key2_l_ctrl, key2_r_ctrl, key2_up, key2_down, key2_left, key2_right, key2_esc, key2_backspace, key2_accent} <= 0;
{key2_minus, key2_equals, key2_back_slash, key2_tab, key2_l_bracket, key2_r_bracket, key2_semicolon, key2_quote} <= 0;
{key2_comma, key2_period, key2_slash, key2_caps, key2_pgup, key2_pgdn} <= 0;
{key2_alt, key2_del} <= 0;
end
else begin
if (rxdone) begin
case ({is_ext, rxbyte})
`PS2_A: key2_a <= is_press;
`PS2_B: key2_b <= is_press;
`PS2_C: key2_c <= is_press;
`PS2_D: key2_d <= is_press;
`PS2_E: key2_e <= is_press;
`PS2_F: key2_f <= is_press;
`PS2_G: key2_g <= is_press;
`PS2_H: key2_h <= is_press;
`PS2_I: key2_i <= is_press;
`PS2_J: key2_j <= is_press;
`PS2_K: key2_k <= is_press;
`PS2_L: key2_l <= is_press;
`PS2_M: key2_m <= is_press;
`PS2_N: key2_n <= is_press;
`PS2_O: key2_o <= is_press;
`PS2_P: key2_p <= is_press;
`PS2_Q: key2_q <= is_press;
`PS2_R: key2_r <= is_press;
`PS2_S: key2_s <= is_press;
`PS2_T: key2_t <= is_press;
`PS2_U: key2_u <= is_press;
`PS2_V: key2_v <= is_press;
`PS2_W: key2_w <= is_press;
`PS2_X: key2_x <= is_press;
`PS2_Y: key2_y <= is_press;
`PS2_Z: key2_z <= is_press;
`PS2_0: key2_0 <= is_press;
`PS2_1: key2_1 <= is_press;
`PS2_2: key2_2 <= is_press;
`PS2_3: key2_3 <= is_press;
`PS2_4: key2_4 <= is_press;
`PS2_5: key2_5 <= is_press;
`PS2_6: key2_6 <= is_press;
`PS2_7: key2_7 <= is_press;
`PS2_8: key2_8 <= is_press;
`PS2_9: key2_9 <= is_press;
`PS2_SPACE: key2_space <= is_press;
`PS2_ENTER: key2_enter <= is_press;
if (!rst_n) begin
is_press <= 1'b1;
is_ext <= 0;
key_magic <= 0;
key_pause <= 0;
{joy_up, joy_down, joy_left, joy_right, joy_fire} <= 0;
{key2_a, key2_b, key2_c, key2_d, key2_e, key2_f, key2_g, key2_h, key2_i, key2_j, key2_k, key2_l, key2_m, key2_n} <= 0;
{key2_o, key2_p, key2_q, key2_r, key2_s, key2_t, key2_u, key2_v, key2_w, key2_x, key2_y, key2_z, key2_0, key2_1} <= 0;
{key2_2, key2_3, key2_4, key2_5, key2_6, key2_7, key2_8, key2_9, key2_space, key2_enter, key2_l_shift, key2_r_shift} <= 0;
{key2_l_ctrl, key2_r_ctrl, key2_up, key2_down, key2_left, key2_right, key2_esc, key2_backspace, key2_accent} <= 0;
{key2_minus, key2_equals, key2_back_slash, key2_tab, key2_l_bracket, key2_r_bracket, key2_semicolon, key2_quote} <= 0;
{key2_comma, key2_period, key2_slash, key2_caps, key2_pgup, key2_pgdn} <= 0;
{key2_alt, key2_del} <= 0;
end
else begin
if (rxdone) begin
case ({is_ext, rxbyte})
`PS2_A: key2_a <= is_press;
`PS2_B: key2_b <= is_press;
`PS2_C: key2_c <= is_press;
`PS2_D: key2_d <= is_press;
`PS2_E: key2_e <= is_press;
`PS2_F: key2_f <= is_press;
`PS2_G: key2_g <= is_press;
`PS2_H: key2_h <= is_press;
`PS2_I: key2_i <= is_press;
`PS2_J: key2_j <= is_press;
`PS2_K: key2_k <= is_press;
`PS2_L: key2_l <= is_press;
`PS2_M: key2_m <= is_press;
`PS2_N: key2_n <= is_press;
`PS2_O: key2_o <= is_press;
`PS2_P: key2_p <= is_press;
`PS2_Q: key2_q <= is_press;
`PS2_R: key2_r <= is_press;
`PS2_S: key2_s <= is_press;
`PS2_T: key2_t <= is_press;
`PS2_U: key2_u <= is_press;
`PS2_V: key2_v <= is_press;
`PS2_W: key2_w <= is_press;
`PS2_X: key2_x <= is_press;
`PS2_Y: key2_y <= is_press;
`PS2_Z: key2_z <= is_press;
`PS2_0: key2_0 <= is_press;
`PS2_1: key2_1 <= is_press;
`PS2_2: key2_2 <= is_press;
`PS2_3: key2_3 <= is_press;
`PS2_4: key2_4 <= is_press;
`PS2_5: key2_5 <= is_press;
`PS2_6: key2_6 <= is_press;
`PS2_7: key2_7 <= is_press;
`PS2_8: key2_8 <= is_press;
`PS2_9: key2_9 <= is_press;
`PS2_SPACE: key2_space <= is_press;
`PS2_ENTER: key2_enter <= is_press;
`PS2_L_SHIFT: key2_l_shift <= is_press;
`PS2_R_SHIFT: key2_r_shift <= is_press;
`PS2_L_CTRL: key2_l_ctrl <= is_press;
`PS2_R_CTRL: key2_r_ctrl <= is_press;
`PS2_L_SHIFT: key2_l_shift <= is_press;
`PS2_R_SHIFT: key2_r_shift <= is_press;
`PS2_L_CTRL: key2_l_ctrl <= is_press;
`PS2_R_CTRL: key2_r_ctrl <= is_press;
`PS2_UP: key2_up <= is_press;
`PS2_DOWN: key2_down <= is_press;
`PS2_LEFT: key2_left <= is_press;
`PS2_RIGHT: key2_right <= is_press;
`PS2_UP: key2_up <= is_press;
`PS2_DOWN: key2_down <= is_press;
`PS2_LEFT: key2_left <= is_press;
`PS2_RIGHT: key2_right <= is_press;
`PS2_ESC: key2_esc <= is_press;
`PS2_BACKSPACE: key2_backspace <= is_press;
`PS2_ACCENT: key2_accent <= is_press;
`PS2_MINUS: key2_minus <= is_press;
`PS2_EQUALS: key2_equals <= is_press;
`PS2_BACK_SLASH: key2_back_slash <= is_press;
`PS2_TAB: key2_tab <= is_press;
`PS2_L_BRACKET: key2_l_bracket <= is_press;
`PS2_R_BRACKET: key2_r_bracket <= is_press;
`PS2_SEMICOLON: key2_semicolon <= is_press;
`PS2_QUOTE: key2_quote <= is_press;
`PS2_COMMA: key2_comma <= is_press;
`PS2_PERIOD: key2_period <= is_press;
`PS2_SLASH: key2_slash <= is_press;
`PS2_CAPS: key2_caps <= is_press;
`PS2_PGUP: key2_pgup <= is_press;
`PS2_PGDN: key2_pgdn <= is_press;
`PS2_ESC: key2_esc <= is_press;
`PS2_BACKSPACE: key2_backspace <= is_press;
`PS2_ACCENT: key2_accent <= is_press;
`PS2_MINUS: key2_minus <= is_press;
`PS2_EQUALS: key2_equals <= is_press;
`PS2_BACK_SLASH: key2_back_slash <= is_press;
`PS2_TAB: key2_tab <= is_press;
`PS2_L_BRACKET: key2_l_bracket <= is_press;
`PS2_R_BRACKET: key2_r_bracket <= is_press;
`PS2_SEMICOLON: key2_semicolon <= is_press;
`PS2_QUOTE: key2_quote <= is_press;
`PS2_COMMA: key2_comma <= is_press;
`PS2_PERIOD: key2_period <= is_press;
`PS2_SLASH: key2_slash <= is_press;
`PS2_CAPS: key2_caps <= is_press;
`PS2_PGUP: key2_pgup <= is_press;
`PS2_PGDN: key2_pgdn <= is_press;
`PS2_F5: key_magic <= is_press;
`PS2_F11: key_pause <= 1'b0;
`PS2_F12: key_pause <= 1'b1;
`PS2_DELETE: key2_del <= is_press;
`PS2_KP_8: joy_up <= is_press;
`PS2_KP_2: joy_down <= is_press;
`PS2_KP_5: joy_down <= is_press;
`PS2_KP_4: joy_left <= is_press;
`PS2_KP_6: joy_right <= is_press;
`PS2_KP_0: joy_fire <= is_press;
`PS2_KP_ENTER: joy_fire <= is_press;
`PS2_L_ALT: begin joy_fire <= is_press; key2_alt <= is_press; end
`PS2_R_ALT: begin joy_fire <= is_press; key2_alt <= is_press; end
endcase
is_press <= rxbyte != 8'hF0;
is_ext <= rxbyte == 8'hE0 || (rxbyte == 8'hF0 && is_ext);
end
else if (rxerr) begin
is_press <= 1'b1;
is_ext <= 0;
end
end
`PS2_F5: key_magic <= is_press;
`PS2_F11: key_pause <= 1'b0;
`PS2_F12: key_pause <= 1'b1;
`PS2_DELETE: key2_del <= is_press;
`PS2_KP_8: joy_up <= is_press;
`PS2_KP_2: joy_down <= is_press;
`PS2_KP_5: joy_down <= is_press;
`PS2_KP_4: joy_left <= is_press;
`PS2_KP_6: joy_right <= is_press;
`PS2_KP_0: joy_fire <= is_press;
`PS2_KP_ENTER: joy_fire <= is_press;
`PS2_L_ALT: begin joy_fire <= is_press; key2_alt <= is_press; end
`PS2_R_ALT: begin joy_fire <= is_press; key2_alt <= is_press; end
endcase
is_press <= rxbyte != 8'hF0;
is_ext <= rxbyte == 8'hE0 || (rxbyte == 8'hF0 && is_ext);
end
else if (rxerr) begin
is_press <= 1'b1;
is_ext <= 0;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
key_reset <= 0;
else
key_reset <= (key2_l_ctrl || key2_r_ctrl) && key2_alt && key2_del;
if (!rst_n)
key_reset <= 0;
else
key_reset <= (key2_l_ctrl || key2_r_ctrl) && key2_alt && key2_del;
end
@ -207,22 +207,22 @@ wire key_9 = key2_9 | key2_r_bracket;
wire key_en = key2_enter;
wire key_sp = key2_space | key2_esc;
wire key_cs = key2_l_shift | key2_r_shift | key2_up | key2_down | key2_left | key2_right | key2_esc | key2_backspace
| key2_tab | key2_caps | key2_pgup | key2_pgdn ;
| key2_tab | key2_caps | key2_pgup | key2_pgdn ;
wire key_ss = key2_l_ctrl | key2_r_ctrl | key2_accent | key2_minus | key2_equals | key2_back_slash | key2_l_bracket
| key2_r_bracket | key2_semicolon | key2_quote | key2_comma | key2_period | key2_slash ;
| key2_r_bracket | key2_semicolon | key2_quote | key2_comma | key2_period | key2_slash ;
always @* begin
zxkb_data <= ~(
// KD4 KD3 KD2 KD1 KD0
((~zxkb_addr[0])? { key_v, key_c, key_x, key_z, key_cs } : 5'd0) | // KA8
((~zxkb_addr[1])? { key_g, key_f, key_d, key_s, key_a } : 5'd0) | // KA9
((~zxkb_addr[2])? { key_t, key_r, key_e, key_w, key_q } : 5'd0) | // KA10
((~zxkb_addr[3])? { key_5, key_4, key_3, key_2, key_1 } : 5'd0) | // KA11
((~zxkb_addr[4])? { key_6, key_7, key_8, key_9, key_0 } : 5'd0) | // KA12
((~zxkb_addr[5])? { key_y, key_u, key_i, key_o, key_p } : 5'd0) | // KA13
((~zxkb_addr[6])? { key_h, key_j, key_k, key_l, key_en } : 5'd0) | // KA14
((~zxkb_addr[7])? { key_b, key_n, key_m, key_ss, key_sp } : 5'd0) // KA15
);
zxkb_data <= ~(
// KD4 KD3 KD2 KD1 KD0
((~zxkb_addr[0])? { key_v, key_c, key_x, key_z, key_cs } : 5'd0) | // KA8
((~zxkb_addr[1])? { key_g, key_f, key_d, key_s, key_a } : 5'd0) | // KA9
((~zxkb_addr[2])? { key_t, key_r, key_e, key_w, key_q } : 5'd0) | // KA10
((~zxkb_addr[3])? { key_5, key_4, key_3, key_2, key_1 } : 5'd0) | // KA11
((~zxkb_addr[4])? { key_6, key_7, key_8, key_9, key_0 } : 5'd0) | // KA12
((~zxkb_addr[5])? { key_y, key_u, key_i, key_o, key_p } : 5'd0) | // KA13
((~zxkb_addr[6])? { key_h, key_j, key_k, key_l, key_en } : 5'd0) | // KA14
((~zxkb_addr[7])? { key_b, key_n, key_m, key_ss, key_sp } : 5'd0) // KA15
);
end
endmodule

116
fpga/rtl/ps2_rxtx.v
View File

@ -1,17 +1,17 @@
module ps2_rxtx#(
parameter CLK_FREQ
) (
input rst_n,
input clk,
input ps2_clk_in,
input ps2_dat_in,
output ps2_clk_out,
output ps2_dat_out,
output [7:0] dataout,
output reg dataout_valid,
output reg dataout_error
parameter CLK_FREQ
) (
input rst_n,
input clk,
input ps2_clk_in,
input ps2_dat_in,
output ps2_clk_out,
output ps2_dat_out,
output [7:0] dataout,
output reg dataout_valid,
output reg dataout_error
);
@ -28,19 +28,19 @@ reg ps2_dat;
reg [1:0] ps2_clk;
wire ps2_clk_fall = ps2_freeze? 1'b0 : (ps2_clk[0] == 0 && ps2_clk[1] == 1'b1);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
ps2_freeze <= 0;
ps2_dat <= 1'b1;
ps2_clk <= 2'b11;
end
else begin
if (timer == CLKWAIT_TICKS)
ps2_freeze <= 1'b0;
else if (ps2_clk_fall)
ps2_freeze <= 1'b1;
ps2_dat <= ps2_dat_in;
ps2_clk <= {ps2_clk[0], ps2_clk_in};
end
if (!rst_n) begin
ps2_freeze <= 0;
ps2_dat <= 1'b1;
ps2_clk <= 2'b11;
end
else begin
if (timer == CLKWAIT_TICKS)
ps2_freeze <= 1'b0;
else if (ps2_clk_fall)
ps2_freeze <= 1'b1;
ps2_dat <= ps2_dat_in;
ps2_clk <= {ps2_clk[0], ps2_clk_in};
end
end
@ -48,38 +48,38 @@ reg [3:0] bit_cnt;
reg [9:0] rxbits;
assign dataout = rxbits[8:1];
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dataout_valid <= 0;
dataout_error <= 0;
timer <= 0;
bit_cnt <= 0;
rxbits <= 0;
end
else begin
dataout_valid <= 0;
dataout_error <= 0;
if (ps2_clk_fall) begin
if (bit_cnt == 4'd10) begin
bit_cnt <= 0;
if (rxbits[0] == 0 && ~rxbits[9] == ^rxbits[8:1] && ps2_dat == 1'b1)
dataout_valid <= 1'b1;
else
dataout_error <= 1'b1;
end
else begin
bit_cnt <= bit_cnt + 1'b1;
rxbits <= {ps2_dat, rxbits[9:1]};
end
timer <= 1'b1;
end
else if (timer != 0) begin
if (timer == TOUT_TICKS) begin
dataout_error <= bit_cnt != 0;
bit_cnt <= 0;
end
timer <= timer + 1'b1;
end
end
if (!rst_n) begin
dataout_valid <= 0;
dataout_error <= 0;
timer <= 0;
bit_cnt <= 0;
rxbits <= 0;
end
else begin
dataout_valid <= 0;
dataout_error <= 0;
if (ps2_clk_fall) begin
if (bit_cnt == 4'd10) begin
bit_cnt <= 0;
if (rxbits[0] == 0 && ~rxbits[9] == ^rxbits[8:1] && ps2_dat == 1'b1)
dataout_valid <= 1'b1;
else
dataout_error <= 1'b1;
end
else begin
bit_cnt <= bit_cnt + 1'b1;
rxbits <= {ps2_dat, rxbits[9:1]};
end
timer <= 1'b1;
end
else if (timer != 0) begin
if (timer == TOUT_TICKS) begin
dataout_error <= bit_cnt != 0;
bit_cnt <= 0;
end
timer <= timer + 1'b1;
end
end
end

292
fpga/rtl/screen.sv
View File

@ -1,43 +1,43 @@
`include "util.vh"
import common::*;
module screen(
input rst_n,
input clk28,
input rst_n,
input clk28,
cpu_bus bus,
output [14:0] addr,
cpu_bus bus,
output [14:0] addr,
input clkwait,
input timings_t timings,
input [2:0] border,
input clkwait,
input timings_t timings,
input [2:0] border,
output reg [2:0] r,
output reg [2:0] g,
output reg [2:0] b,
output reg vsync,
output reg hsync,
output reg csync,
output reg [2:0] r,
output reg [2:0] g,
output reg [2:0] b,
output reg vsync,
output reg hsync,
output reg csync,
output blink,
output reg [7:0] attr_next,
output loading,
output reg fetch,
output fetch_next,
input up_en,
output [5:0] up_ink_addr,
output [5:0] up_paper_addr,
input [7:0] up_ink,
input [7:0] up_paper,
output blink,
output reg [7:0] attr_next,
output loading,
output reg fetch,
output fetch_next,
output [8:0] hc_out,
output [8:0] vc_out,
output clk14,
output clk7,
output clk35,
output ck14,
output ck7,
output ck35
input up_en,
output [5:0] up_ink_addr,
output [5:0] up_paper_addr,
input [7:0] up_ink,
input [7:0] up_paper,
output [8:0] hc_out,
output [8:0] vc_out,
output clk14,
output clk7,
output clk35,
output ck14,
output ck7,
output ck35
);
@ -92,77 +92,77 @@ assign ck7 = hc0[0] & hc0[1];
assign ck35 = hc0[0] & hc0[1] & hc0[2];
wire hc0_reset =
(timings == TIMINGS_PENT)?
hc0 == (H_TOTAL_PENT<<2) - 1'b1 :
(timings == TIMINGS_S128)?
hc0 == (H_TOTAL_S128<<2) - 1'b1 :
// 48K
hc0 == (H_TOTAL_S48<<2) - 1'b1 ;
wire vc_reset =
(timings == TIMINGS_PENT)?
vc == V_TOTAL_PENT - 1'b1 :
(timings == TIMINGS_S128)?
vc == V_TOTAL_S128 - 1'b1 :
// 48K
vc == V_TOTAL_S48 - 1'b1;
(timings == TIMINGS_PENT)?
hc0 == (H_TOTAL_PENT<<2) - 1'b1 :
(timings == TIMINGS_S128)?
hc0 == (H_TOTAL_S128<<2) - 1'b1 :
// 48K
hc0 == (H_TOTAL_S48<<2) - 1'b1 ;
wire vc_reset =
(timings == TIMINGS_PENT)?
vc == V_TOTAL_PENT - 1'b1 :
(timings == TIMINGS_S128)?
vc == V_TOTAL_S128 - 1'b1 :
// 48K
vc == V_TOTAL_S48 - 1'b1;
wire hsync0 =
(timings == TIMINGS_PENT)?
(hc >= (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT)) &&
(hc < (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT)) :
(timings == TIMINGS_S128)?
(hc >= (H_AREA + H_RBORDER_S128 + H_BLANK1_S128)) &&
(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128)) :
// 48K
(hc >= (H_AREA + H_RBORDER_S48 + H_BLANK1_S48)) &&
(hc < (H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48)) ;
wire vsync0 =
(timings == TIMINGS_PENT)?
(vc >= (V_AREA + V_BBORDER_PENT)) && (vc < (V_AREA + V_BBORDER_PENT + V_SYNC_PENT)) :
(timings == TIMINGS_S128)?
(vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128)) :
// 48K
(vc >= (V_AREA + V_BBORDER_S48)) && (vc < (V_AREA + V_BBORDER_S48 + V_SYNC_S48)) ;
(timings == TIMINGS_PENT)?
(hc >= (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT)) &&
(hc < (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT)) :
(timings == TIMINGS_S128)?
(hc >= (H_AREA + H_RBORDER_S128 + H_BLANK1_S128)) &&
(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128)) :
// 48K
(hc >= (H_AREA + H_RBORDER_S48 + H_BLANK1_S48)) &&
(hc < (H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48)) ;
wire vsync0 =
(timings == TIMINGS_PENT)?
(vc >= (V_AREA + V_BBORDER_PENT)) && (vc < (V_AREA + V_BBORDER_PENT + V_SYNC_PENT)) :
(timings == TIMINGS_S128)?
(vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128)) :
// 48K
(vc >= (V_AREA + V_BBORDER_S48)) && (vc < (V_AREA + V_BBORDER_S48 + V_SYNC_S48)) ;
wire blank =
(timings == TIMINGS_PENT)?
((vc >= (V_AREA + V_BBORDER_PENT)) && (vc < (V_AREA + V_BBORDER_PENT + V_SYNC_PENT))) ||
((hc >= (H_AREA + H_RBORDER_PENT)) &&
(hc < (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT + H_BLANK2_PENT))) :
(timings == TIMINGS_S128)?
((vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128))) ||
((hc >= (H_AREA + H_RBORDER_S128)) &&
(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128 + H_BLANK2_S128))) :
// 48K
((vc >= (V_AREA + V_BBORDER_S48)) && (vc < (V_AREA + V_BBORDER_S48 + V_SYNC_S48))) ||
((hc >= (H_AREA + H_RBORDER_S48)) &&
(hc < (H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48 + H_BLANK2_S48))) ;
(timings == TIMINGS_PENT)?
((vc >= (V_AREA + V_BBORDER_PENT)) && (vc < (V_AREA + V_BBORDER_PENT + V_SYNC_PENT))) ||
((hc >= (H_AREA + H_RBORDER_PENT)) &&
(hc < (H_AREA + H_RBORDER_PENT + H_BLANK1_PENT + H_SYNC_PENT + H_BLANK2_PENT))) :
(timings == TIMINGS_S128)?
((vc >= (V_AREA + V_BBORDER_S128)) && (vc < (V_AREA + V_BBORDER_S128 + V_SYNC_S128))) ||
((hc >= (H_AREA + H_RBORDER_S128)) &&
(hc < (H_AREA + H_RBORDER_S128 + H_BLANK1_S128 + H_SYNC_S128 + H_BLANK2_S128))) :
// 48K
((vc >= (V_AREA + V_BBORDER_S48)) && (vc < (V_AREA + V_BBORDER_S48 + V_SYNC_S48))) ||
((hc >= (H_AREA + H_RBORDER_S48)) &&
(hc < (H_AREA + H_RBORDER_S48 + H_BLANK1_S48 + H_SYNC_S48 + H_BLANK2_S48))) ;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
hc0 <= 0;
vc <= 0;
end
else if (hc0_reset) begin
hc0 <= 0;
if (vc_reset) begin
vc <= 0;
end
else begin
vc <= vc + 1'b1;
end
end
else begin
hc0 <= hc0 + 1'b1;
end
if (!rst_n) begin
hc0 <= 0;
vc <= 0;
end
else if (hc0_reset) begin
hc0 <= 0;
if (vc_reset) begin
vc <= 0;
end
else begin
vc <= vc + 1'b1;
end
end
else begin
hc0 <= hc0 + 1'b1;
end
end
reg [4:0] blink_cnt;
assign blink = blink_cnt[$bits(blink_cnt)-1];
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
blink_cnt <= 0;
else if (hc0_reset && vc_reset)
blink_cnt <= blink_cnt + 1'b1;
if (!rst_n)
blink_cnt <= 0;
else if (hc0_reset && vc_reset)
blink_cnt <= blink_cnt + 1'b1;
end
@ -172,9 +172,9 @@ reg [7:0] bitmap, attr, bitmap_next;
reg fetch_step;
wire fetch_bitmap = fetch && fetch_step == 1'd1;
wire fetch_attr = fetch && fetch_step == 1'd0;
assign addr = fetch_bitmap?
{ 2'b10, vc[7:6], vc[2:0], vc[5:3], hc[7:3] } :
{ 5'b10110, vc[7:3], hc[7:3] };
assign addr = fetch_bitmap?
{ 2'b10, vc[7:6], vc[2:0], vc[5:3], hc[7:3] } :
{ 5'b10110, vc[7:3], hc[7:3] };
assign loading = (vc < V_AREA) && (hc < H_AREA || hc0_reset);
wire screen_show = (vc < V_AREA) && (hc0 >= (SCREEN_DELAY<<2) - 2) && (hc0 < ((H_AREA + SCREEN_DELAY)<<2) - 2);
@ -188,64 +188,64 @@ assign up_ink_addr = { attr_next[7:6], 1'b0, attr_next[2:0] };
assign up_paper_addr = { attr_next[7:6], 1'b1, attr_next[5:3] };
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
fetch <= 0;
fetch_step <= 0;
attr <= 0;
bitmap <= 0;
attr_next <= 0;
bitmap_next <= 0;
end
else begin
if (ck14) begin
if (fetch)
fetch_step <= fetch_step + 1'b1;
fetch <= fetch_next;
if (!rst_n) begin
fetch <= 0;
fetch_step <= 0;
attr <= 0;
bitmap <= 0;
attr_next <= 0;
bitmap_next <= 0;
end
else begin
if (ck14) begin
if (fetch)
fetch_step <= fetch_step + 1'b1;
fetch <= fetch_next;
if (fetch_attr)
attr_next <= bus.d;
else if (!loading)
attr_next <= attr_border;
if (fetch_bitmap)
bitmap_next <= bus.d;
end
if (fetch_attr)
attr_next <= bus.d;
else if (!loading)
attr_next <= attr_border;
if (fetch_bitmap)
bitmap_next <= bus.d;
end
if (border_update)
attr <= attr_border;
else if (screen_update)
attr <= attr_next;
if (border_update)
attr <= attr_border;
else if (screen_update)
attr <= attr_next;
if (screen_update)
bitmap <= bitmap_next;
else if (bitmap_shift)
bitmap <= {bitmap[6:0], 1'b0};
if (screen_update)
up_ink0 <= up_ink;
if (screen_update || (!screen_show && !loading))
up_paper0 <= up_paper;
end
if (screen_update)
bitmap <= bitmap_next;
else if (bitmap_shift)
bitmap <= {bitmap[6:0], 1'b0};
if (screen_update)
up_ink0 <= up_ink;
if (screen_update || (!screen_show && !loading))
up_paper0 <= up_paper;
end
end
wire pixel = bitmap[7];
always @(posedge clk28) begin
if (blank)
{g, r, b} = 0;
else if (up_en) begin
g = pixel? up_ink0[7:5] : up_paper0[7:5];
r = pixel? up_ink0[4:2] : up_paper0[4:2];
b[2:1] = pixel? up_ink0[1:0] : up_paper0[1:0];
b[0] = |b[2:1];
end
else begin
{g[2], r[2], b[2]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
{g[1], r[1], b[1]} = ((g[2] | r[2] | b[2]) & attr[6])? 3'b111 : 3'b000;
{g[0], r[0], b[0]} = {g[1], r[1], b[1]};
end
csync = ~(vsync0 ^ hsync0);
vsync = ~vsync0;
hsync = ~hsync0;
if (blank)
{g, r, b} = 0;
else if (up_en) begin
g = pixel? up_ink0[7:5] : up_paper0[7:5];
r = pixel? up_ink0[4:2] : up_paper0[4:2];
b[2:1] = pixel? up_ink0[1:0] : up_paper0[1:0];
b[0] = |b[2:1];
end
else begin
{g[2], r[2], b[2]} = (pixel ^ (attr[7] & blink))? attr[2:0] : attr[5:3];
{g[1], r[1], b[1]} = ((g[2] | r[2] | b[2]) & attr[6])? 3'b111 : 3'b000;
{g[0], r[0], b[0]} = {g[1], r[1], b[1]};
end
csync = ~(vsync0 ^ hsync0);
vsync = ~vsync0;
hsync = ~hsync0;
end

50
fpga/rtl/soundrive.sv
View File

@ -1,15 +1,15 @@
module soundrive(
input rst_n,
input clk28,
input en_soundrive,
input en_covox,
input rst_n,
input clk28,
input en_soundrive,
input en_covox,
cpu_bus bus,
cpu_bus bus,
output reg [7:0] ch_l0,
output reg [7:0] ch_l1,
output reg [7:0] ch_r0,
output reg [7:0] ch_r1
output reg [7:0] ch_l0,
output reg [7:0] ch_l1,
output reg [7:0] ch_r0,
output reg [7:0] ch_r1
);
wire covox_cs = en_covox && bus.ioreq && bus.a_reg[7:0] == 8'hFB;
@ -19,22 +19,22 @@ wire soundrive_c_cs = en_soundrive && bus.ioreq && bus.a_reg[7:0] == 8'h4F;
wire soundrive_d_cs = en_soundrive && bus.ioreq && bus.a_reg[7:0] == 8'h5F;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
ch_l0 <= 8'h80;
ch_l1 <= 8'h80;
ch_r0 <= 8'h80;
ch_r1 <= 8'h80;
end
else begin
if ((covox_cs || soundrive_a_cs) && bus.wr)
ch_l0 <= bus.d_reg;
if ((covox_cs || soundrive_b_cs) && bus.wr)
ch_l1 <= bus.d_reg;
if ((covox_cs || soundrive_c_cs) && bus.wr)
ch_r0 <= bus.d_reg;
if ((covox_cs || soundrive_d_cs) && bus.wr)
ch_r1 <= bus.d_reg;
end
if (!rst_n) begin
ch_l0 <= 8'h80;
ch_l1 <= 8'h80;
ch_r0 <= 8'h80;
ch_r1 <= 8'h80;
end
else begin
if ((covox_cs || soundrive_a_cs) && bus.wr)
ch_l0 <= bus.d_reg;
if ((covox_cs || soundrive_b_cs) && bus.wr)
ch_l1 <= bus.d_reg;
if ((covox_cs || soundrive_c_cs) && bus.wr)
ch_r0 <= bus.d_reg;
if ((covox_cs || soundrive_d_cs) && bus.wr)
ch_r1 <= bus.d_reg;
end
end

640
fpga/rtl/top.sv
View File

@ -1,42 +1,42 @@
import common::*;
module zx_ula(
input clk_in,
input clk_in,
output reg n_rstcpu,
output reg clkcpu,
output reg n_rstcpu,
output reg clkcpu,
inout [18:0] va,
inout [7:0] vd,
input [15:13] a,
inout [18:0] va,
inout [7:0] vd,
input [15:13] a,
output n_vrd,
output n_vwr,
output n_vrd,
output n_vwr,
input n_rd,
input n_wr,
input n_mreq,
input n_iorq,
input n_m1,
input n_rfsh,
output reg n_int,
output n_nmi,
input n_rd,
input n_wr,
input n_mreq,
input n_iorq,
input n_m1,
input n_rfsh,
output reg n_int,
output n_nmi,
output reg [5:0] luma,
output reg [2:0] chroma,
output reg csync,
output reg [5:0] luma,
output reg [2:0] chroma,
output reg csync,
output snd_l,
output snd_r,
output snd_l,
output snd_r,
inout reg ps2_clk,
inout reg ps2_dat,
inout reg ps2_clk,
inout reg ps2_dat,
input sd_cd,
input sd_miso_tape_in,
output sd_mosi,
output reg sd_sck,
output reg sd_cs
input sd_cd,
input sd_miso_tape_in,
output sd_mosi,
output reg sd_sck,
output reg sd_cs
);
/* CLOCK */
@ -58,22 +58,22 @@ wire screen_fetch, screen_fetch_next;
cpu_bus bus();
reg bus_memreq, bus_ioreq;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
bus_ioreq <= 0;
bus_memreq <= 0;
end
else if (!screen_fetch && !screen_fetch_next) begin
bus.a_reg <= bus.a;
bus.d_reg <= bus.d;
bus_ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1;
bus_memreq <= n_mreq == 1'b0;
end
else begin
if (n_iorq)
bus_ioreq <= 0;
if (n_mreq)
bus_memreq <= 0;
end
if (!rst_n) begin
bus_ioreq <= 0;
bus_memreq <= 0;
end
else if (!screen_fetch && !screen_fetch_next) begin
bus.a_reg <= bus.a;
bus.d_reg <= bus.d;
bus_ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1;
bus_memreq <= n_mreq == 1'b0;
end
else begin
if (n_iorq)
bus_ioreq <= 0;
if (n_mreq)
bus_memreq <= 0;
end
end
assign bus.a = {a[15:13], va[12:0]};
assign bus.d = vd;
@ -94,22 +94,22 @@ reg key_magic, key_reset, pause;
wire usrrst_n = ~key_reset;
reg joy_up, joy_down, joy_left, joy_right, joy_fire;
ps2 #(.CLK_FREQ(28_000_000)) ps2_0(
.rst_n(rst_n),
.clk(clk28),
.ps2_clk_in(ps2_clk),
.ps2_dat_in(ps2_dat),
.ps2_clk_out(ps2_clk_out),
.ps2_dat_out(ps2_dat_out),
.zxkb_addr(bus.a_reg[15:8]),
.zxkb_data(ps2_kd),
.key_magic(key_magic),
.key_reset(key_reset),
.key_pause(pause),
.joy_up(joy_up),
.joy_down(joy_down),
.joy_left(joy_left),
.joy_right(joy_right),
.joy_fire(joy_fire)
.rst_n(rst_n),
.clk(clk28),
.ps2_clk_in(ps2_clk),
.ps2_dat_in(ps2_dat),
.ps2_clk_out(ps2_clk_out),
.ps2_dat_out(ps2_dat_out),
.zxkb_addr(bus.a_reg[15:8]),
.zxkb_data(ps2_kd),
.key_magic(key_magic),
.key_reset(key_reset),
.key_pause(pause),
.joy_up(joy_up),
.joy_down(joy_down),
.joy_left(joy_left),
.joy_right(joy_right),
.joy_fire(joy_fire)
);
assign ps2_clk = (ps2_clk_out == 0)? 1'b0 : 1'bz;
assign ps2_dat = (ps2_dat_out == 0)? 1'b0 : 1'bz;
@ -131,58 +131,58 @@ wire [7:0] attr_next;
wire [8:0] vc, hc;
wire clk14, clk7, clk35, ck14, ck7, ck35;
screen screen0(
.rst_n(rst_n),
.clk28(clk28),
.rst_n(rst_n),
.clk28(clk28),
.bus(bus),
.addr(screen_addr),
.bus(bus),
.addr(screen_addr),
.clkwait(clkwait),
.timings(timings),
.border(screen_border),
.clkwait(clkwait),
.timings(timings),
.border(screen_border),
.r(r),
.g(g),
.b(b),
.csync(csync),
.vsync(),
.hsync(hsync),
.r(r),
.g(g),
.b(b),
.csync(csync),
.vsync(),
.hsync(hsync),
.blink(blink),
.fetch(screen_fetch),
.fetch_next(screen_fetch_next),
.loading(screen_loading),
.attr_next(attr_next),
.blink(blink),
.fetch(screen_fetch),
.fetch_next(screen_fetch_next),
.loading(screen_loading),
.attr_next(attr_next),
.up_en(up_en),
.up_ink_addr(up_ink_addr),
.up_paper_addr(up_paper_addr),
.up_ink(up_ink),
.up_paper(up_paper),
.up_en(up_en),
.up_ink_addr(up_ink_addr),
.up_paper_addr(up_paper_addr),
.up_ink(up_ink),
.up_paper(up_paper),
.vc_out(vc),
.hc_out(hc),
.clk14(clk14),
.clk7(clk7),
.clk35(clk35),
.ck14(ck14),
.ck7(ck7),
.ck35(ck35)
.vc_out(vc),
.hc_out(hc),
.clk14(clk14),
.clk7(clk7),
.clk35(clk35),
.ck14(ck14),
.ck7(ck7),
.ck35(ck35)
);
/* VIDEO OUTPUT */
always @*
luma <= {g[2], r[2], b[2], g[1], r[1], b[1]};
luma <= {g[2], r[2], b[2], g[1], r[1], b[1]};
reg [2:0] chroma0;
chroma_gen #(.CLK_FREQ(40_000_000)) chroma_gen1(
.cg_clock(clk40),
.cg_rgb({g[2],r[2],b[2]}),
.cg_hsync(hsync),
.cg_enable(1'b1),
.cg_pnsel(1'b0),
.cg_out(chroma0)
.cg_clock(clk40),
.cg_rgb({g[2],r[2],b[2]}),
.cg_hsync(hsync),
.cg_enable(1'b1),
.cg_pnsel(1'b0),
.cg_out(chroma0)
);
assign chroma[0] = (chroma0[2]|chroma0[1])? chroma0[0] : 1'bz;
assign chroma[1] = (chroma0[2]|chroma0[1])? chroma0[0] : 1'bz;
@ -196,31 +196,31 @@ logic n_int_next;
wire snow, clkcpu_ck;
wire init_done;
cpucontrol cpucontrol0(
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.clk14(clk14),
.clk7(clk7),
.clk35(clk35),
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.clk14(clk14),
.clk7(clk7),
.clk35(clk35),
.bus(bus),
.bus(bus),
.vc(vc),
.hc(hc),
.rampage128(rampage128),
.screen_loading(screen_loading),
.turbo(turbo),
.timings(timings),
.pause(pause),
.ext_wait_cycle(div_wait || up_en),
.init_done_in(init_done),
.vc(vc),
.hc(hc),
.rampage128(rampage128),
.screen_loading(screen_loading),
.turbo(turbo),
.timings(timings),
.pause(pause),
.ext_wait_cycle(div_wait || up_en),
.init_done_in(init_done),
.n_rstcpu(n_rstcpu),
.clkcpu(clkcpu),
.clkcpu_ck(clkcpu_ck),
.clkwait(clkwait),
.n_int(n_int),
.n_int_next(n_int_next),
.snow(snow)
.n_rstcpu(n_rstcpu),
.clkcpu(clkcpu),
.clkcpu_ck(clkcpu_ck),
.clkwait(clkwait),
.n_int(n_int),
.n_int_next(n_int_next),
.snow(snow)
);
@ -230,29 +230,29 @@ wire magic_active_next;
reg n_nmi0;
reg extlock, joy_sinclair, rom_plus3, rom_alt48, ay_abc, ay_mono;
magic magic0(
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.bus(bus),
.n_int(n_int),
.n_int_next(n_int_next),
.n_nmi(n_nmi),
.bus(bus),
.n_int(n_int),
.n_int_next(n_int_next),
.n_nmi(n_nmi),
.magic_button(key_magic),
.magic_button(key_magic),
.magic_mode(magic_mode),
.magic_map(magic_map),
.magic_active_next(magic_active_next),
.magic_mode(magic_mode),
.magic_map(magic_map),
.magic_active_next(magic_active_next),
.extlock(extlock),
.magic_beeper(magic_beeper),
.timings(timings),
.turbo(turbo),
.joy_sinclair(joy_sinclair),
.rom_plus3(rom_plus3),
.rom_alt48(rom_alt48),
.ay_abc(ay_abc),
.ay_mono(ay_mono)
.extlock(extlock),
.magic_beeper(magic_beeper),
.timings(timings),
.turbo(turbo),
.joy_sinclair(joy_sinclair),
.rom_plus3(rom_plus3),
.rom_alt48(rom_alt48),
.ay_abc(ay_abc),
.ay_mono(ay_mono)
);
@ -267,38 +267,38 @@ reg [2:0] port_1ffd;
reg port_dffd_d3;
reg port_dffd_d4;
ports ports0 (
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.bus(bus),
.d_out(ports_dout),
.d_out_active(ports_dout_active),
.bus(bus),
.d_out(ports_dout),
.d_out_active(ports_dout_active),
.en_128k(1'b1),
.en_plus3(rom_plus3),
.en_profi(!extlock),
.en_kempston(!joy_sinclair),
.en_sinclair(joy_sinclair),
.en_128k(1'b1),
.en_plus3(rom_plus3),
.en_profi(!extlock),
.en_kempston(!joy_sinclair),
.en_sinclair(joy_sinclair),
.clkcpu_ck(clkcpu_ck),
.timings(timings),
.screen_loading(screen_loading),
.attr_next(attr_next),
.kd(ps2_kd),
.kempston_data({3'b000, joy_fire, joy_up, joy_down, joy_left, joy_right}),
.magic_active_next(magic_active_next),
.tape_in(sd_miso_tape_in),
.clkcpu_ck(clkcpu_ck),
.timings(timings),
.screen_loading(screen_loading),
.attr_next(attr_next),
.kd(ps2_kd),
.kempston_data({3'b000, joy_fire, joy_up, joy_down, joy_left, joy_right}),
.magic_active_next(magic_active_next),
.tape_in(sd_miso_tape_in),
.tape_out(tape_out),
.beeper(beeper),
.border(border),
.screen_page(screenpage),
.rompage128(rompage128),
.rampage128(rampage128),
.rampage_ext(rampage_ext),
.port_1ffd(port_1ffd),
.port_dffd_d3(port_dffd_d3),
.port_dffd_d4(port_dffd_d4)
.tape_out(tape_out),
.beeper(beeper),
.border(border),
.screen_page(screenpage),
.rompage128(rompage128),
.rampage128(rampage128),
.rampage_ext(rampage_ext),
.port_1ffd(port_1ffd),
.port_dffd_d3(port_dffd_d3),
.port_dffd_d4(port_dffd_d4)
);
@ -307,67 +307,67 @@ wire turbosound_dout_active;
wire [7:0] turbosound_dout;
wire [7:0] ay_a0, ay_b0, ay_c0, ay_a1, ay_b1, ay_c1;
turbosound turbosound0(
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.ck35(ck35),
.en(1'b1),
.bus(bus),
.d_out(turbosound_dout),
.d_out_active(turbosound_dout_active),
.pause(pause),
.ay_a0(ay_a0),
.ay_b0(ay_b0),
.ay_c0(ay_c0),
.ay_a1(ay_a1),
.ay_b1(ay_b1),
.ay_c1(ay_c1)
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.ck35(ck35),
.en(1'b1),
.bus(bus),
.d_out(turbosound_dout),
.d_out_active(turbosound_dout_active),
.pause(pause),
.ay_a0(ay_a0),
.ay_b0(ay_b0),
.ay_c0(ay_c0),
.ay_a1(ay_a1),
.ay_b1(ay_b1),
.ay_c1(ay_c1)
);
/* COVOX & SOUNDRIVE */
reg [7:0] soundrive_l0, soundrive_l1, soundrive_r0, soundrive_r1;
soundrive soundrive0(
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.en_covox(!extlock),
.en_soundrive(!extlock),
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.en_covox(!extlock),
.en_soundrive(!extlock),
.bus(bus),
.bus(bus),
.ch_l0(soundrive_l0),
.ch_l1(soundrive_l1),
.ch_r0(soundrive_r0),
.ch_r1(soundrive_r1)
.ch_l0(soundrive_l0),
.ch_l1(soundrive_l1),
.ch_r0(soundrive_r0),
.ch_r1(soundrive_r1)
);
/* SOUND MIXER */
mixer mixer0(
.rst_n(rst_n),
.clk28(clk28),
.rst_n(rst_n),
.clk28(clk28),
.beeper(beeper),
.tape_out(tape_out),
.tape_in(sd_miso_tape_in),
.ay_a0(ay_a0),
.ay_b0(ay_b0),
.ay_c0(ay_c0),
.ay_a1(ay_a1),
.ay_b1(ay_b1),
.ay_c1(ay_c1),
.sd_l0(soundrive_l0),
.sd_l1(soundrive_l1),
.sd_r0(soundrive_r0),
.sd_r1(soundrive_r1),
.beeper(beeper),
.tape_out(tape_out),
.tape_in(sd_miso_tape_in),
.ay_a0(ay_a0),
.ay_b0(ay_b0),
.ay_c0(ay_c0),
.ay_a1(ay_a1),
.ay_b1(ay_b1),
.ay_c1(ay_c1),
.sd_l0(soundrive_l0),
.sd_l1(soundrive_l1),
.sd_r0(soundrive_r0),
.sd_r1(soundrive_r1),
.ay_abc(ay_abc),
.ay_mono(ay_mono),
.ay_abc(ay_abc),
.ay_mono(ay_mono),
.dac_l(snd_l),
.dac_r(snd_r)
.dac_l(snd_l),
.dac_r(snd_r)
);
@ -377,32 +377,32 @@ wire [7:0] div_dout;
reg [3:0] div_page;
reg sd_mosi0;
divmmc divmmc0(
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.ck14(ck14),
.ck7(ck7),
.en(!extlock),
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.ck14(ck14),
.ck7(ck7),
.en(!extlock),
.bus(bus),
.d_out(div_dout),
.d_out_active(div_dout_active),
.bus(bus),
.d_out(div_dout),
.d_out_active(div_dout_active),
.sd_cd(sd_cd),
.sd_miso(sd_miso_tape_in),
.sd_mosi(sd_mosi0),
.sd_sck(sd_sck),
.sd_cs(sd_cs),
.port_dffd_d4(port_dffd_d4),
.port_1ffd_d0(port_1ffd[0]),
.magic_mode(magic_mode),
.magic_map(magic_map),
.sd_cd(sd_cd),
.sd_miso(sd_miso_tape_in),
.sd_mosi(sd_mosi0),
.sd_sck(sd_sck),
.sd_cs(sd_cs),
.div_page(div_page),
.div_map(div_map),
.div_ram(div_ram),
.div_ramwr_mask(div_ramwr_mask),
.div_wait(div_wait)
.port_dffd_d4(port_dffd_d4),
.port_1ffd_d0(port_1ffd[0]),
.magic_mode(magic_mode),
.magic_map(magic_map),
.div_page(div_page),
.div_map(div_map),
.div_ram(div_ram),
.div_ramwr_mask(div_ramwr_mask),
.div_wait(div_wait)
);
///assign sd_mosi = (sd_cs == 1'b0)? sd_mosi0 : tape_out;
assign sd_mosi = sd_mosi0;
@ -412,19 +412,19 @@ assign sd_mosi = sd_mosi0;
wire up_dout_active;
wire [7:0] up_dout;
ulaplus ulaplus0(
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.en(!extlock),
.bus(bus),
.d_out(up_dout),
.d_out_active(up_dout_active),
.active(up_en),
.ink_addr(up_ink_addr),
.paper_addr(up_paper_addr),
.ink(up_ink),
.paper(up_paper)
.rst_n(rst_n & usrrst_n),
.clk28(clk28),
.en(!extlock),
.bus(bus),
.d_out(up_dout),
.d_out_active(up_dout_active),
.active(up_en),
.ink_addr(up_ink_addr),
.paper_addr(up_paper_addr),
.ink(up_ink),
.paper(up_paper)
);
@ -439,54 +439,54 @@ wire rom2ram_active;
assign init_done = !rom2ram_active;
reg [1:0] rom2ram_init;
always @(posedge rom2ram_clk or negedge rst_n) begin
if (!rst_n)
rom2ram_init <= 0;
else if (rom2ram_init != 3)
rom2ram_init <= rom2ram_init + 1'b1;
if (!rst_n)
rom2ram_init <= 0;
else if (rom2ram_init != 3)
rom2ram_init <= rom2ram_init + 1'b1;
end
rom2ram rom2ram0(
.clock(rom2ram_clk),
.init(rom2ram_init == 2),
.datain(rom2ram_datain),
.rom_data_ready(rom2ram_rom_data_ready),
.init_busy(rom2ram_active),
.rom_address(rom2ram_rom_address),
.rom_rden(rom2ram_rom_rden),
.ram_wren(rom2ram_ram_wren),
.ram_address(rom2ram_ram_address),
.dataout(rom2ram_dataout)
.clock(rom2ram_clk),
.init(rom2ram_init == 2),
.datain(rom2ram_datain),
.rom_data_ready(rom2ram_rom_data_ready),
.init_busy(rom2ram_active),
.rom_address(rom2ram_rom_address),
.rom_rden(rom2ram_rom_rden),
.ram_wren(rom2ram_ram_wren),
.ram_address(rom2ram_ram_address),
.dataout(rom2ram_dataout)
);
localparam ROM_OFFSET = 24'h13256;
wire [23:0] asmi_addr = ROM_OFFSET + rom2ram_rom_address;
asmi asmi0(
.clkin(rom2ram_clk),
.read(rom2ram_rom_rden),
.rden(rom2ram_active),
.addr(asmi_addr),
.reset(!rst_n),
.dataout(rom2ram_datain),
.busy(),
.data_valid(rom2ram_rom_data_ready)
.clkin(rom2ram_clk),
.read(rom2ram_rom_rden),
.rden(rom2ram_active),
.addr(asmi_addr),
.reset(!rst_n),
.dataout(rom2ram_datain),
.busy(),
.data_valid(rom2ram_rom_data_ready)
);
/* MEMORY CONTROLLER */
reg romreq, ramreq, ramreq_wr;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
romreq = 1'b0;
ramreq = 1'b0;
ramreq_wr = 1'b0;
end
else begin
romreq = bus.mreq && !bus.rfsh && bus.a[14] == 0 && bus.a[15] == 0 &&
(magic_map || (!div_ram && div_map) || (!div_ram && !port_dffd_d4 && !port_1ffd[0]));
ramreq = bus.mreq && !bus.rfsh && !romreq;
ramreq_wr = ramreq && bus.wr && div_ramwr_mask == 0;
end
if (!rst_n) begin
romreq = 1'b0;
ramreq = 1'b0;
ramreq_wr = 1'b0;
end
else begin
romreq = bus.mreq && !bus.rfsh && bus.a[14] == 0 && bus.a[15] == 0 &&
(magic_map || (!div_ram && div_map) || (!div_ram && !port_dffd_d4 && !port_1ffd[0]));
ramreq = bus.mreq && !bus.rfsh && !romreq;
ramreq_wr = ramreq && bus.wr && div_ramwr_mask == 0;
end
end
assign n_vrd = ((((ramreq || romreq) && bus.rd) || screen_fetch) && !rom2ram_ram_wren)? 1'b0 : 1'b1;
@ -498,53 +498,53 @@ assign n_vwr = ((ramreq_wr && bus.wr && !screen_fetch) || rom2ram_ram_wren)? 1'b
* 01xxxx 128Kb of divmmc memory
* 10xxxx 128Kb of extended ram (via port dffd)
* 11xxxx 128Kb of main ram
*/
*/
reg [18:13] ram_a;
always @(posedge clk28) begin
ram_a <=
magic_map & bus.a[15] & bus.a[14]? {2'b00, 3'b111, bus.a[13]} :
magic_map? {3'b111, screenpage, bus.a[14:13]} :
div_map & ~bus.a[14] & ~bus.a[15] & bus.a[13]? {2'b01, div_page} :
div_map & ~bus.a[14] & ~bus.a[15]? {2'b01, 4'b0011} :
port_dffd_d3 & bus.a[15]? {2'b11, bus.a[14], bus.a[15], bus.a[14], bus.a[13]} :
port_dffd_d3 & bus.a[14]? {1'b1, ~rampage_ext[0], rampage128, bus.a[13]} :
(port_1ffd[2] == 1'b0 && port_1ffd[0] == 1'b1)? {2'b11, port_1ffd[1], bus.a[15], bus.a[14], bus.a[13]} :
(port_1ffd == 3'b101)? {2'b11, ~(bus.a[15] & bus.a[14]), bus.a[15], bus.a[14]} :
(port_1ffd == 3'b111)? {2'b11, ~(bus.a[15] & bus.a[14]), (bus.a[15] | bus.a[14]), bus.a[14]} :
bus.a[15] & bus.a[14]? {1'b1, ~rampage_ext[0], rampage128, bus.a[13]} :
{2'b11, bus.a[14], bus.a[15], bus.a[14], bus.a[13]} ;
ram_a <=
magic_map & bus.a[15] & bus.a[14]? {2'b00, 3'b111, bus.a[13]} :
magic_map? {3'b111, screenpage, bus.a[14:13]} :
div_map & ~bus.a[14] & ~bus.a[15] & bus.a[13]? {2'b01, div_page} :
div_map & ~bus.a[14] & ~bus.a[15]? {2'b01, 4'b0011} :
port_dffd_d3 & bus.a[15]? {2'b11, bus.a[14], bus.a[15], bus.a[14], bus.a[13]} :
port_dffd_d3 & bus.a[14]? {1'b1, ~rampage_ext[0], rampage128, bus.a[13]} :
(port_1ffd[2] == 1'b0 && port_1ffd[0] == 1'b1)? {2'b11, port_1ffd[1], bus.a[15], bus.a[14], bus.a[13]} :
(port_1ffd == 3'b101)? {2'b11, ~(bus.a[15] & bus.a[14]), bus.a[15], bus.a[14]} :
(port_1ffd == 3'b111)? {2'b11, ~(bus.a[15] & bus.a[14]), (bus.a[15] | bus.a[14]), bus.a[14]} :
bus.a[15] & bus.a[14]? {1'b1, ~rampage_ext[0], rampage128, bus.a[13]} :
{2'b11, bus.a[14], bus.a[15], bus.a[14], bus.a[13]} ;
end
reg [16:14] rom_a;
always @(posedge clk28) begin
rom_a <=
magic_map? 3'd2 :
div_map? 3'd3 :
(rom_plus3 && port_1ffd[2] == 1'b0 && rompage128 == 1'b0)? 3'd4 :
(rom_plus3 && port_1ffd[2] == 1'b0 && rompage128 == 1'b1)? 3'd5 :
(rom_plus3 && port_1ffd[2] == 1'b1 && rompage128 == 1'b0)? 3'd6 :
(rompage128 == 1'b1 && rom_alt48 == 1'b1)? 3'd7 :
(rompage128 == 1'b1)? 3'd1 :
3'd0;
rom_a <=
magic_map? 3'd2 :
div_map? 3'd3 :
(rom_plus3 && port_1ffd[2] == 1'b0 && rompage128 == 1'b0)? 3'd4 :
(rom_plus3 && port_1ffd[2] == 1'b0 && rompage128 == 1'b1)? 3'd5 :
(rom_plus3 && port_1ffd[2] == 1'b1 && rompage128 == 1'b0)? 3'd6 :
(rompage128 == 1'b1 && rom_alt48 == 1'b1)? 3'd7 :
(rompage128 == 1'b1)? 3'd1 :
3'd0;
end
assign va[18:0] =
rom2ram_ram_wren? {2'b00, rom2ram_ram_address} :
screen_fetch && snow? {3'b111, screenpage, screen_addr[14:8], {8{1'bz}}} :
screen_fetch? {3'b111, screenpage, screen_addr} :
romreq? {2'b00, rom_a[16:14], bus.a[13], {13{1'bz}}} :
{ram_a[18:13], {13{1'bz}}};
rom2ram_ram_wren? {2'b00, rom2ram_ram_address} :
screen_fetch && snow? {3'b111, screenpage, screen_addr[14:8], {8{1'bz}}} :
screen_fetch? {3'b111, screenpage, screen_addr} :
romreq? {2'b00, rom_a[16:14], bus.a[13], {13{1'bz}}} :
{ram_a[18:13], {13{1'bz}}};
assign vd[7:0] =
~n_vrd? {8{1'bz}} :
rom2ram_ram_wren? rom2ram_dataout :
up_dout_active? up_dout :
div_dout_active? div_dout :
turbosound_dout_active? turbosound_dout :
ports_dout_active? ports_dout :
~n_wr? {8{1'bz}} :
8'hFF;
~n_vrd? {8{1'bz}} :
rom2ram_ram_wren? rom2ram_dataout :
up_dout_active? up_dout :
div_dout_active? div_dout :
turbosound_dout_active? turbosound_dout :
ports_dout_active? ports_dout :
~n_wr? {8{1'bz}} :
8'hFF;
endmodule

140
fpga/rtl/turbosound.sv
View File

@ -1,21 +1,21 @@
module turbosound(
input rst_n,
input clk28,
input ck35,
input en,
input rst_n,
input clk28,
input ck35,
input en,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
input pause,
output [7:0] ay_a0,
output [7:0] ay_b0,
output [7:0] ay_c0,
output [7:0] ay_a1,
output [7:0] ay_b1,
output [7:0] ay_c1
input pause,
output [7:0] ay_a0,
output [7:0] ay_b0,
output [7:0] ay_c0,
output [7:0] ay_a1,
output [7:0] ay_b1,
output [7:0] ay_c1
);
@ -27,74 +27,74 @@ wire ay_rd1 = bus.rd && ay_bc1 == 1'b1 && ay_bdir == 1'b0 && ay_sel == 1'b1;
wire port_bffd = bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[1] == 0;
wire port_fffd = bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[14] == 1'b1 && bus.a_reg[1] == 0;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
ay_bc1 <= 0;
ay_bdir <= 0;
ay_sel <= 0;
end
else begin
ay_bc1 <= en && port_fffd;
ay_bdir <= en && port_bffd && bus.wr;
if (bus.ioreq && port_fffd && bus.wr && bus.d_reg[7:3] == 5'b11111)
ay_sel <= bus.d_reg[0];
end
if (!rst_n) begin
ay_bc1 <= 0;
ay_bdir <= 0;
ay_sel <= 0;
end
else begin
ay_bc1 <= en && port_fffd;
ay_bdir <= en && port_bffd && bus.wr;
if (bus.ioreq && port_fffd && bus.wr && bus.d_reg[7:3] == 5'b11111)
ay_sel <= bus.d_reg[0];
end
end
reg [1:0] ay_ck;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
ay_ck <= 0;
else if (ck35 && en && !pause)
ay_ck <= ay_ck + 1'b1;
else
ay_ck[1] <= 0;
if (!rst_n)
ay_ck <= 0;
else if (ck35 && en && !pause)
ay_ck <= ay_ck + 1'b1;
else
ay_ck[1] <= 0;
end
wire [7:0] ay_dout0, ay_dout1;
YM2149 ym2149_0(
.CLK(clk28),
.ENA(ay_ck[1]),
.RESET_H(~rst_n),
.I_SEL_L(1'b1),
.I_DA(bus.d_reg),
.O_DA(ay_dout0),
.I_REG(1'b0),
.busctrl_addr(ay_bc1 & ay_bdir & ~ay_sel),
.busctrl_we(~ay_bc1 & ay_bdir & ~ay_sel),
.ctrl_aymode(1'b1),
.port_a_i(8'hff),
.port_b_i(8'hff),
.port_a_o(),
.port_b_o(),
.O_AUDIO_A(ay_a0),
.O_AUDIO_B(ay_b0),
.O_AUDIO_C(ay_c0)
);
.CLK(clk28),
.ENA(ay_ck[1]),
.RESET_H(~rst_n),
.I_SEL_L(1'b1),
.I_DA(bus.d_reg),
.O_DA(ay_dout0),
.I_REG(1'b0),
.busctrl_addr(ay_bc1 & ay_bdir & ~ay_sel),
.busctrl_we(~ay_bc1 & ay_bdir & ~ay_sel),
.ctrl_aymode(1'b1),
.port_a_i(8'hff),
.port_b_i(8'hff),
.port_a_o(),
.port_b_o(),
.O_AUDIO_A(ay_a0),
.O_AUDIO_B(ay_b0),
.O_AUDIO_C(ay_c0)
);
YM2149 ym2149_1(
.CLK(clk28),
.ENA(ay_ck[1]),
.RESET_H(~rst_n),
.I_SEL_L(1'b1),
.I_DA(bus.d_reg),
.O_DA(ay_dout1),
.I_REG(1'b0),
.busctrl_addr(ay_bc1 & ay_bdir & ay_sel),
.busctrl_we(~ay_bc1 & ay_bdir & ay_sel),
.ctrl_aymode(1'b1),
.port_a_i(8'hff),
.port_b_i(8'hff),
.port_a_o(),
.port_b_o(),
.O_AUDIO_A(ay_a1),
.O_AUDIO_B(ay_b1),
.O_AUDIO_C(ay_c1)
);
.CLK(clk28),
.ENA(ay_ck[1]),
.RESET_H(~rst_n),
.I_SEL_L(1'b1),
.I_DA(bus.d_reg),
.O_DA(ay_dout1),
.I_REG(1'b0),
.busctrl_addr(ay_bc1 & ay_bdir & ay_sel),
.busctrl_we(~ay_bc1 & ay_bdir & ay_sel),
.ctrl_aymode(1'b1),
.port_a_i(8'hff),
.port_b_i(8'hff),
.port_a_o(),
.port_b_o(),
.O_AUDIO_A(ay_a1),
.O_AUDIO_B(ay_b1),
.O_AUDIO_C(ay_c1)
);
assign d_out_active = ay_rd0 | ay_rd1;
assign d_out = ay_rd1? ay_dout1 : ay_dout0;
endmodule

72
fpga/rtl/ulaplus.sv
View File

@ -1,17 +1,17 @@
module ulaplus(
input rst_n,
input clk28,
input en,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
output reg active,
input [5:0] ink_addr,
input [5:0] paper_addr,
output reg [7:0] ink,
output reg [7:0] paper
input rst_n,
input clk28,
input en,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
output reg active,
input [5:0] ink_addr,
input [5:0] paper_addr,
output reg [7:0] ink,
output reg [7:0] paper
);
@ -24,21 +24,21 @@ reg [7:0] addr_reg;
reg [1:0] write_req;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
active <= 0;
addr_reg <= 0;
write_req <= 0;
port_ff3b_rd <= 0;
end
else begin
if (port_bf3b_cs && bus.wr)
addr_reg <= bus.d_reg;
if (port_ff3b_cs && bus.wr && addr_reg == 8'b01000000)
active <= bus.d_reg[0];
write_req <= {write_req[0], port_ff3b_cs && bus.wr && addr_reg[7:6] == 2'b00};
port_ff3b_rd <= port_ff3b_cs && bus.rd;
end
if (!rst_n) begin
active <= 0;
addr_reg <= 0;
write_req <= 0;
port_ff3b_rd <= 0;
end
else begin
if (port_bf3b_cs && bus.wr)
addr_reg <= bus.d_reg;
if (port_ff3b_cs && bus.wr && addr_reg == 8'b01000000)
active <= bus.d_reg[0];
write_req <= {write_req[0], port_ff3b_cs && bus.wr && addr_reg[7:6] == 2'b00};
port_ff3b_rd <= port_ff3b_cs && bus.rd;
end
end
@ -49,17 +49,17 @@ wire [7:0] ram_q;
ram pallete(ram_q, ram_a, bus.d_reg, write_req0, clk28);
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
read_step <= 0;
else
read_step <= !read_step;
if (!rst_n)
read_step <= 0;
else
read_step <= !read_step;
end
always @(posedge clk28) begin
if (read_step)
paper <= ram_q;
else
ink <= ram_q;
if (read_step)
paper <= ram_q;
else
ink <= ram_q;
end

86
fpga/rtl/util.vh
View File

@ -1,10 +1,10 @@
`define MAX(a,b) (a)>(b)?(a):(b)
`define MIN(a,b) (a)<(b)?(a):(b)
`define MIN(a,b) (a)<(b)?(a):(b)
`define ISDEF(N) (^(N) >= 0 === 1'b1 || ^(N) < 0 === 1'b1) //"IS DEFined", is an
//integer strictly defined; Xilinx warnings about "===" in synthesable
//code - include in supression rules.
//Why so complicated - I forgot :)
`define ISDEF(N) (^(N) >= 0 === 1'b1 || ^(N) < 0 === 1'b1) //"IS DEFined", is an
//integer strictly defined; Xilinx warnings about "===" in synthesable
//code - include in supression rules.
//Why so complicated - I forgot :)
`define TZER(N) (!`ISDEF(N) || (N) <= 0) ? 'hx : \
(~|((N)&'h7fff_ffff)?31:(~|((N)&'h3fff_ffff)?30: \
@ -16,9 +16,9 @@
(~|((N)&'h7ff)?11:(~|((N)&'h3ff)?10:(~|((N)&'h1ff)?9:(~|((N)&'hff)?8: \
(~|((N)&'h7f)?7:(~|((N)&'h3f)?6:(~|((N)&'h1f)?5:(~|((N)&'hf)?4: \
(~|((N)&'h7)?3:(~|((N)&'h3)?2: \
(~N&'h1))))))))))))))))))))))))))))))) //"Trailong ZERoes". ONLY FOR ARGUMENTS <= 32 BITS!
//Maximum 2's power divider of a number. Both for synthesis and simulation; bit
//selection is not used since N could be an expression.
(~N&'h1))))))))))))))))))))))))))))))) //"Trailong ZERoes". ONLY FOR ARGUMENTS <= 32 BITS!
//Maximum 2's power divider of a number. Both for synthesis and simulation; bit
//selection is not used since N could be an expression.
`define CLOG2_CORE(N) \
((N)&'h8000_0000 ?32:((N)&'h4000_0000 ?31:((N)&'h2000_0000 ?30:((N)&'h1000_0000 ?29: \
@ -29,56 +29,56 @@
((N)&'h800 ?12:((N)&'h400 ?11:((N)&'h200 ?10:((N)&'h100 ?9: \
((N)&'h80 ?8:((N)&'h40 ?7:((N)&'h20 ?6:((N)&'h10 ?5: \
((N)&'h8 ?4:((N)&'h4 ?3:((N)&'h2 ?2: \
((N)&'h1)))))))))))))))))))))))))))))))) //"Core Ceil(LOG2(N+1))" for correctly defined
//values (<= 32 bits). Both for synthesis and not; bit selection is not
//used since N could be an expression.
((N)&'h1)))))))))))))))))))))))))))))))) //"Core Ceil(LOG2(N+1))" for correctly defined
//values (<= 32 bits). Both for synthesis and not; bit selection is not
//used since N could be an expression.
`define HZ2NS(F) (1.0e9 / (F)) //Convert frequency [Hz] to delay in [ns].
`define HZ2NS(F) (1.0e9 / (F)) //Convert frequency [Hz] to delay in [ns].
`define ABS(X) ((X >= 0) ? (X) : (-X)) //ABSolute value of X.
`define ABS(X) ((X >= 0) ? (X) : (-X)) //ABSolute value of X.
`define CLOG2(N) ((!`ISDEF(N) || (N) <= 0) ? 'hx : `CLOG2_CORE((N)-1)) //"Ceil(LOG2(N))"
//ONLY FOR ARGUMENTS <= 32 BITS! Ceil (nearest greater or equal integer) of
//binary logarithm.
//ONLY FOR ARGUMENTS <= 32 BITS! Ceil (nearest greater or equal integer) of
//binary logarithm.
`define WIDINPAR(W) ((W) >= 1 ? (W) : ((W) == 0 ? 1'b1 : 1'bx)) //"WIDth INdex from a
//PARameter" ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus from given
//parameter, to avoid index "-1".
//Ex.: bus with width W: "[widinpar(W)-1:0];"
`define WIDINPAR(W) ((W) >= 1 ? (W) : ((W) == 0 ? 1'b1 : 1'bx)) //"WIDth INdex from a
//PARameter" ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus from given
//parameter, to avoid index "-1".
//Ex.: bus with width W: "[widinpar(W)-1:0];"
`define WIDC(N) (`ISDEF(N) && (N) == 0 ? 1 : `CLOG2((N) + 1)) //"WIDth Computation"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of it's maximum
//value (from 0).
//Ex.: bus for holding numbers in range [0..N]: "wire [`WIDCF(N)-1:0] bus;"
//Precision width of parameters: "localparam [`WIDCF(<expr>)-1:0] N = <expr>;"
`define WIDC(N) (`ISDEF(N) && (N) == 0 ? 1 : `CLOG2((N) + 1)) //"WIDth Computation"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of it's maximum
//value (from 0).
//Ex.: bus for holding numbers in range [0..N]: "wire [`WIDCF(N)-1:0] bus;"
//Precision width of parameters: "localparam [`WIDCF(<expr>)-1:0] N = <expr>;"
`define WIDCN(N) (`ISDEF(N) && ((N) == 0 || (N) == 1) ? 1 : `CLOG2(N)) //"WIDth Computation from N"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of number of it's
//different values. Handy for computation of high index of a bus.
//Ex.: coder with N inputs output: "output [`WIDCFN(N)-1:0] out;";
//N-words RAM adress input: "input [`WIDCFN(N)-1:0] adr;"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of number of it's
//different values. Handy for computation of high index of a bus.
//Ex.: coder with N inputs output: "output [`WIDCFN(N)-1:0] out;";
//N-words RAM adress input: "input [`WIDCFN(N)-1:0] adr;"
`define URAND(MIN, MAX) ((MAX) < (MIN) ? 1'bx : (((MAX) == (MIN)) ? (MIN) : \
(MIN + {$random} % ((MAX) - (MIN)))) )
//Form an unsigned random value in the range [MIN..MAX-1];
//"{}" makes unsigned.
(MIN + {$random} % ((MAX) - (MIN)))) )
//Form an unsigned random value in the range [MIN..MAX-1];
//"{}" makes unsigned.
`define POS_FMOD(A, B) A - B * ($rtoi((A + 0.0) / B) + $signed(A < 0)) //Positive fraction
//modulo. Only for POSITIVE dividers!!!
`define POS_FMOD(A, B) A - B * ($rtoi((A + 0.0) / B) + $signed(A < 0)) //Positive fraction
//modulo. Only for POSITIVE dividers!!!
`define ISHEXD(L) (`ISDEF(L) && ((L) >= "A" && (L) <= "F" || (L) >= "a" && (L) <= "f" || \
(L) >= "0" && (L) <= "9")) //IS byte a HEX Digit. x- and z-
//bits are treated correctly.
(L) >= "0" && (L) <= "9")) //IS byte a HEX Digit. x- and z-
//bits are treated correctly.
`define ISHEXDX(L) (`ISHEXD(L) || \
`ISDEF(L) && ((L) == "X" || (L) == "x")) //IS byte a HEX Digit or X/x.
`ISDEF(L) && ((L) == "X" || (L) == "x")) //IS byte a HEX Digit or X/x.
`define IS_DEC_INT_DIG(L) ((L) >= "0" && (L) <= "9") //Is a byte a valid decimal
//integer digit.
`define IS_DEC_INT_DIG(L) ((L) >= "0" && (L) <= "9") //Is a byte a valid decimal
//integer digit.
`define HEXD2DEC(L) (!`ISHEXD(L) ? \
0 : \
((L) >= "a" ? (L) - "a" + 10 : \
((L) >= "A" ? (L) - "A" + 10 : \
(L) - "0"))) //Convert
//HEXadecimal Digit to decimal number, on all incorrect inputs returns 0.
0 : \
((L) >= "a" ? (L) - "a" + 10 : \
((L) >= "A" ? (L) - "A" + 10 : \
(L) - "0"))) //Convert
//HEXadecimal Digit to decimal number, on all incorrect inputs returns 0.

104
fpga/tb/rom.asm
View File

@ -1,71 +1,71 @@
DEVICE ZXSPECTRUM48
DEVICE ZXSPECTRUM48
ORG #0000
ORG #0000
Start:
nop
jp Main
nop
jp Main
ORG #0038
ORG #0038
Int1:
jp #1ff8
ORG #00FF
DB #38
jp #1ff8
ORG #00FF
DB #38
ORG #0066
ORG #0066
Nmi:
jp #1ffa
push af
ld a, #08
out (#ff), a
pop af
retn
jp #1ffa
push af
ld a, #08
out (#ff), a
pop af
retn
ORG #1000
ORG #1000
Main:
im 2
ei
im 2
ei
ld bc, #7ffd
ld a, #83
.200 out (c), a
ld bc, #7ffd
ld a, #83
.200 out (c), a
//.72 nop
//ld a, 7
//out (#fe), a
//.72 nop
//ld a, 7
//out (#fe), a
//ld hl, #4000
//ld de, #c000
//ld bc, 100
//ldir
//ld hl, #4000
//ld de, #c000
//ld bc, 100
//ldir
//ld c, #ff
//ld b, #ff
//ld hl, #4000
//otir
//ld c, #ff
//ld b, #ff
//ld hl, #4000
//otir
jp #1fff
jp #1fff
Loop:
halt
jp Loop
halt
jp Loop
ORG #1FF8 // DivROM exit vector
reti
ORG #1FFA // DivROM exit vector
retn
ORG #1FFF // DivROM exit vector
nop
jp #3D00
ORG #1FF8 // DivROM exit vector
reti
ORG #1FFA // DivROM exit vector
retn
ORG #1FFF // DivROM exit vector
nop
jp #3D00
ORG #C000 // mapped #0000
ORG #C000 // mapped #0000
DivROM_Start:
nop
ld bc, #3D00
push bc
jp #1FFF
ORG #DFFF // mapped #1FFF
nop
ORG #1D00 // mapped #3D00
jp #0000
nop
ld bc, #3D00
push bc
jp #1FFF
ORG #DFFF // mapped #1FFF
nop
ORG #1D00 // mapped #3D00
jp #0000
SAVEBIN "rom.bin",0,65536
SAVEBIN "rom.bin",0,65536

38
fpga/tb/stubs/asmi.v
View File

@ -1,24 +1,24 @@
module asmi (
addr,
clkin,
rden,
read,
reset,
busy,
data_valid,
dataout)/* synthesis synthesis_clearbox = 2 */;
addr,
clkin,
rden,
read,
reset,
busy,
data_valid,
dataout)/* synthesis synthesis_clearbox = 2 */;
input [23:0] addr;
input clkin;
input rden;
input read;
input reset;
output busy;
output data_valid;
output [7:0] dataout;
input [23:0] addr;
input clkin;
input rden;
input read;
input reset;
output busy;
output data_valid;
output [7:0] dataout;
assign busy = 0;
assign data_valid = 1'b1;
assign dataout = 0;
assign busy = 0;
assign data_valid = 1'b1;
assign dataout = 0;
endmodule

16
fpga/tb/stubs/pll.v
View File

@ -1,14 +1,14 @@
`timescale 1 ps / 1 ps
module pll (
inclk0,
c0,
c1,
locked);
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output reg locked;
input inclk0;
output c0;
output c1;
output reg locked;
initial begin
locked = 0;

40
fpga/tb/stubs/rom2ram.v
View File

@ -1,25 +1,25 @@
module rom2ram (
clock,
datain,
init,
rom_data_ready,
dataout,
init_busy,
ram_address,
ram_wren,
rom_address,
rom_rden);
clock,
datain,
init,
rom_data_ready,
dataout,
init_busy,
ram_address,
ram_wren,
rom_address,
rom_rden);
input clock;
input [7:0] datain;
input init;
input rom_data_ready;
output [7:0] dataout;
output init_busy;
output [16:0] ram_address;
output ram_wren;
output [16:0] rom_address;
output rom_rden;
input clock;
input [7:0] datain;
input init;
input rom_data_ready;
output [7:0] dataout;
output init_busy;
output [16:0] ram_address;
output ram_wren;
output [16:0] rom_address;
output rom_rden;
assign init_busy = 0;
assign ram_wren = 0;