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101 lines
2.2 KiB
Systemverilog
101 lines
2.2 KiB
Systemverilog
module turbosound(
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input rst_n,
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input clk28,
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input ck35,
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input en,
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cpu_bus bus,
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output [7:0] d_out,
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output d_out_active,
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input pause,
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output [7:0] ay_a0,
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output [7:0] ay_b0,
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output [7:0] ay_c0,
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output [7:0] ay_a1,
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output [7:0] ay_b1,
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output [7:0] ay_c1
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);
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reg ay_bdir;
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reg ay_bc1;
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reg ay_sel;
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wire ay_rd0 = bus.rd && ay_bc1 == 1'b1 && ay_bdir == 1'b0 && ay_sel == 1'b0;
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wire ay_rd1 = bus.rd && ay_bc1 == 1'b1 && ay_bdir == 1'b0 && ay_sel == 1'b1;
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wire port_bffd = bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[1] == 0;
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wire port_fffd = bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[14] == 1'b1 && bus.a_reg[1] == 0;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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ay_bc1 <= 0;
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ay_bdir <= 0;
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ay_sel <= 0;
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end
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else begin
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ay_bc1 <= en && port_fffd;
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ay_bdir <= en && port_bffd && bus.wr;
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if (bus.ioreq && port_fffd && bus.wr && bus.d_reg[7:3] == 5'b11111)
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ay_sel <= bus.d_reg[0];
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end
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end
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reg [1:0] ay_ck;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n)
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ay_ck <= 0;
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else if (ck35 && en && !pause)
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ay_ck <= ay_ck + 1'b1;
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else
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ay_ck[1] <= 0;
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end
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wire [7:0] ay_dout0, ay_dout1;
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YM2149 ym2149_0(
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.CLK(clk28),
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.ENA(ay_ck[1]),
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.RESET_H(~rst_n),
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.I_SEL_L(1'b1),
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.I_DA(bus.d_reg),
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.O_DA(ay_dout0),
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.I_REG(1'b0),
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.busctrl_addr(ay_bc1 & ay_bdir & ~ay_sel),
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.busctrl_we(~ay_bc1 & ay_bdir & ~ay_sel),
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.ctrl_aymode(1'b1),
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.port_a_i(8'hff),
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.port_b_i(8'hff),
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.port_a_o(),
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.port_b_o(),
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.O_AUDIO_A(ay_a0),
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.O_AUDIO_B(ay_b0),
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.O_AUDIO_C(ay_c0)
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);
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YM2149 ym2149_1(
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.CLK(clk28),
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.ENA(ay_ck[1]),
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.RESET_H(~rst_n),
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.I_SEL_L(1'b1),
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.I_DA(bus.d_reg),
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.O_DA(ay_dout1),
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.I_REG(1'b0),
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.busctrl_addr(ay_bc1 & ay_bdir & ay_sel),
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.busctrl_we(~ay_bc1 & ay_bdir & ay_sel),
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.ctrl_aymode(1'b1),
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.port_a_i(8'hff),
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.port_b_i(8'hff),
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.port_a_o(),
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.port_b_o(),
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.O_AUDIO_A(ay_a1),
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.O_AUDIO_B(ay_b1),
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.O_AUDIO_C(ay_c1)
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);
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assign d_out_active = ay_rd0 | ay_rd1;
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assign d_out = ay_rd1? ay_dout1 : ay_dout0;
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endmodule
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