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screen: minor refactor

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UzixLS
2021-05-06 16:33:44 +03:00
parent 96c5875a1b
commit 27fcb57f87
4 changed files with 35 additions and 37 deletions
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4
fpga/rtl/cpucontrol.sv
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@ -13,7 +13,7 @@ module cpucontrol(
input [8:0] vc,
input [8:0] hc,
input [2:0] rampage128,
input screen_load,
input screen_loading,
input turbo_t turbo,
input timings_t timings,
input pause,
@ -39,7 +39,7 @@ always @(posedge clkcpu)
wire contention_mem_addr = bus.a[14] & (~bus.a[15] | (bus.a[15] & rampage128[0]));
wire contention_mem = iorq_delayed == 1'b0 && mreq_delayed == 1'b0 && contention_mem_addr;
wire contention_io = iorq_delayed == 1'b0 && bus.iorq;
wire contention0 = screen_load && (hc[2] || hc[3]) && (contention_mem || contention_io);
wire contention0 = screen_loading && (hc[2] || hc[3]) && (contention_mem || contention_io);
wire contention = clkcpu && contention0 && turbo == TURBO_NONE && timings != TIMINGS_PENT;
assign snow = (timings != TIMINGS_PENT) && bus.a[14] && ~bus.a[15] && bus.rfsh;

4
fpga/rtl/ports.sv
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@ -14,7 +14,7 @@ module ports(
input clkcpu_ck,
input timings_t timings,
input screen_load,
input screen_loading,
input [7:0] attr_next,
input [4:0] kd,
input [7:0] kempston_data,
@ -40,7 +40,7 @@ always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
port_ff_rd <= 0;
else
port_ff_rd <= bus.rd && bus.ioreq && (timings != TIMINGS_PENT || bus.a[7:0] == 8'hFF) && screen_load;
port_ff_rd <= bus.rd && bus.ioreq && (timings != TIMINGS_PENT || bus.a[7:0] == 8'hFF) && screen_loading;
end

40
fpga/rtl/screen.sv
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@ -5,7 +5,7 @@ module screen(
input clk28,
cpu_bus bus,
output [14:0] screen_addr,
output [14:0] addr,
input clkwait,
input timings_t timings,
@ -18,10 +18,11 @@ module screen(
output reg hsync,
output reg csync,
output read,
output blink,
output load,
output reg [7:0] attr_next,
output loading,
output reg fetch,
output fetch_next,
input up_en,
output [5:0] up_ink_addr,
@ -168,22 +169,19 @@ end
wire [7:0] attr_border = {2'b00, border, 3'b000};
reg [7:0] bitmap, attr, bitmap_next;
reg screen_read;
assign read = screen_read;
reg screen_read_step;
wire bitmap_read = screen_read && screen_read_step == 1'd1;
wire attr_read = screen_read && screen_read_step == 1'd0;
assign screen_addr = bitmap_read?
reg fetch_step;
wire fetch_bitmap = fetch && fetch_step == 1'd1;
wire fetch_attr = fetch && fetch_step == 1'd0;
assign addr = fetch_bitmap?
{ 2'b10, vc[7:6], vc[2:0], vc[5:3], hc[7:3] } :
{ 5'b10110, vc[7:3], hc[7:3] };
wire screen_load = (vc < V_AREA) && (hc < H_AREA || hc0_reset);
assign load = screen_load;
assign loading = (vc < V_AREA) && (hc < H_AREA || hc0_reset);
wire screen_show = (vc < V_AREA) && (hc0 >= (SCREEN_DELAY<<2) - 2) && (hc0 < ((H_AREA + SCREEN_DELAY)<<2) - 2);
wire screen_update = vc < V_AREA && hc <= H_AREA && hc != 0 && hc0[4:0] == 5'b11110;
wire border_update = !screen_show && ((timings == TIMINGS_PENT && ck7) || hc0[4:0] == 5'b11110);
wire bitmap_shift = hc0[1:0] == 2'b10;
wire screen_read_next = screen_load && ((!bus.iorq && !bus.mreq && !bus.m1) || bus.rfsh || clkwait);
assign fetch_next = loading && ((!bus.iorq && !bus.mreq && !bus.m1) || bus.rfsh || clkwait);
reg [7:0] up_ink0, up_paper0;
assign up_ink_addr = { attr_next[7:6], 1'b0, attr_next[2:0] };
@ -191,8 +189,8 @@ assign up_paper_addr = { attr_next[7:6], 1'b1, attr_next[5:3] };
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
screen_read <= 0;
screen_read_step <= 0;
fetch <= 0;
fetch_step <= 0;
attr <= 0;
bitmap <= 0;
attr_next <= 0;
@ -200,15 +198,15 @@ always @(posedge clk28 or negedge rst_n) begin
end
else begin
if (ck14) begin
if (screen_read)
screen_read_step <= screen_read_step + 1'b1;
screen_read <= screen_read_next;
if (fetch)
fetch_step <= fetch_step + 1'b1;
fetch <= fetch_next;
if (attr_read)
if (fetch_attr)
attr_next <= bus.d;
else if (!screen_load)
else if (!loading)
attr_next <= attr_border;
if (bitmap_read)
if (fetch_bitmap)
bitmap_next <= bus.d;
end
@ -224,7 +222,7 @@ always @(posedge clk28 or negedge rst_n) begin
if (screen_update)
up_ink0 <= up_ink;
if (screen_update || (!screen_show && !screen_load))
if (screen_update || (!screen_show && !loading))
up_paper0 <= up_paper;
end
end

24
fpga/rtl/top.sv
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@ -51,7 +51,7 @@ pll pll0(.inclk0(clk_in), .c0(clk40), .c1(clk20), .locked(rst_n));
timings_t timings;
turbo_t turbo;
wire clkwait;
wire screen_read;
wire screen_fetch;
reg n_iorq_delayed, a_valid;
always @(posedge clk28) begin
@ -67,7 +67,7 @@ assign bus.m1 = ~n_m1;
assign bus.rfsh = ~n_rfsh;
assign bus.rd = ~n_rd;
assign bus.wr = ~n_wr;
assign bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && n_iorq_delayed == 1'b0 && a_valid;
assign bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && a_valid;
assign bus.a_valid = a_valid;
@ -109,7 +109,7 @@ reg hsync;
reg up_en;
wire [5:0] up_ink_addr, up_paper_addr;
wire [7:0] up_ink, up_paper;
wire screen_load, screen_read_up;
wire screen_loading;
wire [14:0] screen_addr;
wire [7:0] attr_next;
wire [8:0] vc, hc;
@ -119,7 +119,7 @@ screen screen0(
.clk28(clk28),
.bus(bus),
.screen_addr(screen_addr),
.addr(screen_addr),
.clkwait(clkwait),
.timings(timings),
@ -133,8 +133,8 @@ screen screen0(
.hsync(hsync),
.blink(blink),
.read(screen_read),
.load(screen_load),
.fetch(screen_fetch),
.loading(screen_loading),
.attr_next(attr_next),
.up_en(up_en),
@ -195,7 +195,7 @@ cpucontrol cpucontrol0(
.vc(vc),
.hc(hc),
.rampage128(rampage128),
.screen_load(screen_load),
.screen_loading(screen_loading),
.turbo(turbo),
.timings(timings),
.pause(pause),
@ -270,7 +270,7 @@ ports ports0 (
.clkcpu_ck(clkcpu_ck),
.timings(timings),
.screen_load(screen_load),
.screen_loading(screen_loading),
.attr_next(attr_next),
.kd(ps2_kd),
.kempston_data({3'b000, joy_fire, joy_up, joy_down, joy_left, joy_right}),
@ -477,8 +477,8 @@ always @(posedge clk28 or negedge rst_n) begin
end
end
assign n_vrd = ((((ramreq || romreq) && bus.rd) || screen_read) && !rom2ram_ram_wren)? 1'b0 : 1'b1;
assign n_vwr = ((ramreq_wr && bus.wr && !screen_read) || rom2ram_ram_wren)? 1'b0 : 1'b1;
assign n_vrd = ((((ramreq || romreq) && bus.rd) || screen_fetch) && !rom2ram_ram_wren)? 1'b0 : 1'b1;
assign n_vwr = ((ramreq_wr && bus.wr && !screen_fetch) || rom2ram_ram_wren)? 1'b0 : 1'b1;
/* VA[18:13] map
* 00xxxx 128Kb of roms
@ -519,8 +519,8 @@ end
assign va[18:0] =
rom2ram_ram_wren? {2'b00, rom2ram_ram_address} :
screen_read && snow? {3'b111, screenpage, screen_addr[14:8], {8{1'bz}}} :
screen_read? {3'b111, screenpage, screen_addr} :
screen_fetch && snow? {3'b111, screenpage, screen_addr[14:8], {8{1'bz}}} :
screen_fetch? {3'b111, screenpage, screen_addr} :
romreq? {2'b00, rom_a[16:14], bus.a[13], {13{1'bz}}} :
{ram_a[18:13], {13{1'bz}}};