uzix/zx-sizif-xxs
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minor testbench update

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UzixLS
2021-05-06 18:57:36 +03:00
parent 11088108f7
commit 96c5875a1b
2 changed files with 41 additions and 28 deletions
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35
fpga/tb/rom.asm
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@ -2,6 +2,7 @@
ORG #0000
Start:
nop
jp Main
ORG #0038
@ -25,8 +26,8 @@ Main:
ei
ld bc, #7ffd
ld a, #11
out (c), a
ld a, #83
.200 out (c), a
//.72 nop
//ld a, 7
@ -43,16 +44,28 @@ Main:
//otir
jp #1fff
ORG #1FF8
reti
ORG #1FFA
retn
ORG #1FFF
jp #3d00
Loop:
halt
jp Loop
SAVEBIN "rom.bin",0,16384
ORG #1FF8 // DivROM exit vector
reti
ORG #1FFA // DivROM exit vector
retn
ORG #1FFF // DivROM exit vector
nop
jp #3D00
ORG #C000 // mapped #0000
DivROM_Start:
nop
ld bc, #3D00
push bc
jp #1FFF
ORG #DFFF // mapped #1FFF
nop
ORG #1D00 // mapped #3D00
jp #0000
SAVEBIN "rom.bin",0,65536

34
fpga/tb/testbench_zx_ula.v
View File

@ -103,8 +103,8 @@ zx_ula zx_ula1(
/* MEMORY */
reg [7:0] ram [0:524288];
wire [18:0] ram_addr_a = va;
reg [18:0] ram_addr_a0;
wire [15:0] ram_addr_a = va;
reg [15:0] ram_addr_a0;
wire [7:0] ram_q_a = ram[ram_addr_a0];
always @(posedge clk28) begin
@ -115,7 +115,7 @@ always @(posedge clk28) begin
end
initial begin
integer i;
for (i = 16*1024; i < 524288; i++)
for (i = 64*1024; i < 524288; i++)
ram[i] <= 0;
$readmemh("rom.mem", ram);
end
@ -138,22 +138,22 @@ assign d_cpu_i = vd;
// assign a_cpu = a_cpu_cpu;
/* CPU SIGNALS (Z84C0020 timings) */
//assign #400 n_rd = n_rd_cpu; //TdCf(RDf)
//assign #400 n_wr = n_wr_cpu; //TdCf(WRf)
//assign #400 n_iorq = n_iorq_cpu; //TdCr(IORQf)
//assign #400 n_mreq = n_mreq_cpu; //TdCf(MREQf)
//assign #450 n_m1 = n_m1_cpu; //TdCr(M1f)
//assign #600 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
//assign #570 a_cpu = a_cpu_cpu; //TdCr(A)
assign #400 n_rd = n_rd_cpu; //TdCf(RDf)
assign #400 n_wr = n_wr_cpu; //TdCf(WRf)
assign #400 n_iorq = n_iorq_cpu; //TdCr(IORQf)
assign #400 n_mreq = n_mreq_cpu; //TdCf(MREQf)
assign #450 n_m1 = n_m1_cpu; //TdCr(M1f)
assign #600 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
assign #570 a_cpu = a_cpu_cpu; //TdCr(A)
/* CPU SIGNALS (Z84C0008 timings) */
assign #700 n_rd = n_rd_cpu; //TdCf(RDf)
assign #600 n_wr = n_wr_cpu; //TdCf(WRf)
assign #550 n_iorq = n_iorq_cpu; //TdCr(IORQf)
assign #600 n_mreq = n_mreq_cpu; //TdCf(MREQf)
assign #700 n_m1 = n_m1_cpu; //TdCr(M1f)
assign #950 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
assign #800 a_cpu = a_cpu_cpu; //TdCr(A)
// assign #700 n_rd = n_rd_cpu; //TdCf(RDf)
// assign #600 n_wr = n_wr_cpu; //TdCf(WRf)
// assign #550 n_iorq = n_iorq_cpu; //TdCr(IORQf)
// assign #600 n_mreq = n_mreq_cpu; //TdCf(MREQf)
// assign #700 n_m1 = n_m1_cpu; //TdCr(M1f)
// assign #950 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
// assign #800 a_cpu = a_cpu_cpu; //TdCr(A)
/* CPU SIGNALS (Z84C0004 timings) */
// assign #850 n_rd = n_rd_cpu; //TdCf(RDf)