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significant stability improvements with 48K/128K timings

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UzixLS
2021-05-06 16:34:38 +03:00
parent 27fcb57f87
commit 0097124413
9 changed files with 110 additions and 104 deletions
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4
fpga/rtl/common.sv
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@ -14,6 +14,8 @@ interface cpu_bus();
wire rd;
wire wr;
reg [15:0] a_reg;
reg [7:0] d_reg;
wire ioreq;
wire a_valid;
wire memreq;
endinterface

11
fpga/rtl/cpucontrol.sv
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@ -5,10 +5,8 @@ module cpucontrol(
input clk14,
input clk7,
input clk35,
cpu_bus bus,
output [7:0] d_out,
output d_out_active,
cpu_bus bus,
input [8:0] vc,
input [8:0] hc,
@ -65,9 +63,6 @@ end
/* INT GENERATOR */
wire int_vector_rd = bus.iorq && bus.m1;
wire [7:0] int_vector_data = 8'hff;
localparam INT_V_S48 = 247;
localparam INT_H_S48 = 442;
localparam INT_V_S128 = 247;
@ -108,8 +103,4 @@ always @(posedge clk28 or negedge rst_n) begin
end
/* BUS CONTROLLER */
assign d_out = int_vector_data;
assign d_out_active = int_vector_rd;
endmodule

34
fpga/rtl/divmmc.sv
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@ -33,24 +33,24 @@ always @(posedge clk28 or negedge rst_n) begin
div_automap_next <= 0;
div_automap <= 0;
end
else if (bus.m1 && bus.mreq && magic_map == 0 && bus.a_valid) begin
else if (bus.m1 && bus.memreq && magic_map == 0) begin
if (sd_cd || !en || port_dffd_d4 || port_1ffd_d0) begin
div_automap_next <= 0;
end
else if (bus.a[15:3] == 13'h3FF) begin // exit vectors 1FF8-1FFF
else if (bus.a_reg[15:3] == 13'h3FF) begin // exit vectors 1FF8-1FFF
div_automap_next <= 0;
end
else if (
bus.a == 16'h0000 || // power-on/reset/rst0/software restart
bus.a == 16'h0008 || // syntax error
bus.a == 16'h0038 || // im1 interrupt/rst #38
(bus.a == 16'h0066 && !magic_mode) || // nmi routine
bus.a == 16'h04C6 || // tape save routine
bus.a == 16'h0562 // tape load and verify routine
bus.a_reg == 16'h0000 || // power-on/reset/rst0/software restart
bus.a_reg == 16'h0008 || // syntax error
bus.a_reg == 16'h0038 || // im1 interrupt/rst #38
(bus.a_reg == 16'h0066 && !magic_mode) || // nmi routine
bus.a_reg == 16'h04C6 || // tape save routine
bus.a_reg == 16'h0562 // tape load and verify routine
) begin
div_automap_next <= 1'b1;
end
else if (bus.a[15:8] == 8'h3D) begin // tr-dos mapping area
else if (bus.a_reg[15:8] == 8'h3D) begin // tr-dos mapping area
div_automap_next <= 1'b1;
div_automap <= 1'b1;
end
@ -62,9 +62,9 @@ end
reg spi_rd;
reg div_conmem, div_mapram;
wire port_e3_cs = en && bus.ioreq && bus.a[7:0] == 8'hE3;
wire port_e7_cs = en && bus.ioreq && bus.a[7:0] == 8'hE7;
wire port_eb_cs = en && bus.ioreq && bus.a[7:0] == 8'hEB;
wire port_e3_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hE3;
wire port_e7_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hE7;
wire port_eb_cs = en && bus.ioreq && bus.a_reg[7:0] == 8'hEB;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
spi_rd <= 0;
@ -76,12 +76,12 @@ always @(posedge clk28 or negedge rst_n) begin
else begin
spi_rd <= port_eb_cs && bus.rd;
if (port_e3_cs && bus.wr) begin
div_page <= bus.d[3:0];
div_mapram <= bus.d[6] | div_mapram;
div_conmem <= bus.d[7];
div_page <= bus.d_reg[3:0];
div_mapram <= bus.d_reg[6] | div_mapram;
div_conmem <= bus.d_reg[7];
end
if (port_e7_cs && bus.wr) begin
sd_cs <= bus.d[0];
sd_cs <= bus.d_reg[0];
end
end
end
@ -114,7 +114,7 @@ always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
spi_reg <= 0;
else if (port_eb_cs && bus.wr)
spi_reg <= bus.d;
spi_reg <= bus.d_reg;
else if (spi_cnt[3] == 1'b0 && ck7)
spi_reg[7:0] <= {spi_reg[6:0], sd_miso};
end

42
fpga/rtl/magic.sv
View File

@ -40,19 +40,19 @@ always @(posedge clk28 or negedge rst_n) begin
if (magic_button == 1'b1 && n_int == 1'b1 && n_int_next == 1'b0)
magic_mode <= 1'b1;
if (magic_map && bus.mreq && bus.rd && bus.a_valid && bus.a == 16'hf000 && !magic_map_next) begin
if (magic_map && bus.memreq && bus.rd && bus.a_reg == 16'hf000 && !magic_map_next) begin
magic_unmap_next <= 1'b1;
magic_mode <= 1'b0;
end
else if (magic_map && bus.mreq && bus.rd && bus.a_valid && bus.a == 16'hf008) begin
else if (magic_map && bus.memreq && bus.rd && bus.a_reg == 16'hf008) begin
magic_unmap_next <= 1'b1;
magic_map_next <= 1'b1;
end
else if (magic_unmap_next && !bus.mreq) begin
else if (magic_unmap_next && !bus.memreq) begin
magic_map <= 1'b0;
magic_unmap_next <= 1'b0;
end
else if (magic_mode && bus.m1 && bus.mreq && ((bus.a_valid && bus.a == 16'h0066) || magic_map_next)) begin
else if (magic_mode && bus.m1 && bus.memreq && (bus.a_reg == 16'h0066 || magic_map_next)) begin
magic_map <= 1'b1;
magic_map_next <= 1'b0;
end
@ -61,7 +61,7 @@ end
/* MAGIC CONFIG */
wire config_cs = magic_map && bus.ioreq && bus.a[7:0] == 8'hff;
wire config_cs = magic_map && bus.ioreq && bus.a_reg[7:0] == 8'hff;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
magic_beeper <= 0;
@ -75,22 +75,22 @@ always @(posedge clk28 or negedge rst_n) begin
joy_sinclair <= 0;
end
else if (config_cs && bus.wr) begin
if (bus.a[15:12] == 4'h0)
magic_beeper <= bus.d[0];
if (bus.a[15:12] == 4'h1)
extlock <= bus.d[0];
if (bus.a[15:12] == 4'h2)
timings <= timings_t'(bus.d[1:0]);
if (bus.a[15:12] == 4'h3)
turbo <= turbo_t'(bus.d[1:0]);
if (bus.a[15:12] == 4'h4)
{ay_mono, ay_abc} <= bus.d[1:0];
if (bus.a[15:12] == 4'h5)
rom_plus3 <= bus.d[0];
if (bus.a[15:12] == 4'h6)
rom_alt48 <= bus.d[0];
if (bus.a[15:12] == 4'h7)
joy_sinclair <= bus.d[0];
if (bus.a_reg[15:12] == 4'h0)
magic_beeper <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h1)
extlock <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h2)
timings <= timings_t'(bus.d_reg[1:0]);
if (bus.a_reg[15:12] == 4'h3)
turbo <= turbo_t'(bus.d_reg[1:0]);
if (bus.a_reg[15:12] == 4'h4)
{ay_mono, ay_abc} <= bus.d_reg[1:0];
if (bus.a_reg[15:12] == 4'h5)
rom_plus3 <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h6)
rom_alt48 <= bus.d_reg[0];
if (bus.a_reg[15:12] == 4'h7)
joy_sinclair <= bus.d_reg[0];
end
end

38
fpga/rtl/ports.sv
View File

@ -40,12 +40,12 @@ always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
port_ff_rd <= 0;
else
port_ff_rd <= bus.rd && bus.ioreq && (timings != TIMINGS_PENT || bus.a[7:0] == 8'hFF) && screen_loading;
port_ff_rd <= bus.rd && bus.ioreq && (timings != TIMINGS_PENT || bus.a_reg[7:0] == 8'hFF) && screen_loading;
end
/* PORT #FE */
wire port_fe_cs = bus.ioreq && bus.a[0] == 0;
wire port_fe_cs = bus.ioreq && bus.a_reg[0] == 0;
reg port_fe_rd;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
@ -63,9 +63,9 @@ always @(posedge clk28 or negedge rst_n) begin
border <= 0;
end
else if (port_fe_cs && bus.wr && clkcpu_ck) begin // clkcpu_ck to synchronize border
beeper <= bus.d[4];
tape_out <= bus.d[3];
border <= bus.d[2:0];
beeper <= bus.d_reg[4];
tape_out <= bus.d_reg[3];
border <= bus.d_reg[2:0];
end
end
@ -75,8 +75,8 @@ always @(posedge clk28 or negedge rst_n) begin
end
else if (en_sinclair) begin
kd0 <= kd
& (bus.a[12] == 0? {~kempston_data[1], ~kempston_data[0], ~kempston_data[2], ~kempston_data[3], ~kempston_data[4]} : 5'b11111) // 6-0 keys
& (bus.a[15] == 0? {1'b1, ~kempston_data[6], ~kempston_data[5], 2'b11} : 5'b11111 ) ; // b-space keys
& (bus.a_reg[12] == 0? {~kempston_data[1], ~kempston_data[0], ~kempston_data[2], ~kempston_data[3], ~kempston_data[4]} : 5'b11111) // 6-0 keys
& (bus.a_reg[15] == 0? {1'b1, ~kempston_data[6], ~kempston_data[5], 2'b11} : 5'b11111 ) ; // b-space keys
end
else begin
kd0 <= kd;
@ -85,7 +85,7 @@ end
/* PORT #7FFD */
wire port_7ffd_cs = en_128k && bus.ioreq && bus.a[1] == 0 && bus.a[15] == 0 && (bus.a[14] == 1'b1 || !en_plus3);
wire port_7ffd_cs = en_128k && bus.ioreq && bus.a_reg[1] == 0 && bus.a_reg[15] == 0 && (bus.a_reg[14] == 1'b1 || !en_plus3);
reg lock_7ffd;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
@ -95,16 +95,16 @@ always @(posedge clk28 or negedge rst_n) begin
lock_7ffd <= 0;
end
else if (port_7ffd_cs && bus.wr && (lock_7ffd == 0 || port_dffd_d4 == 1'b1)) begin
rampage128 <= bus.d[2:0];
screen_page <= bus.d[3];
rompage128 <= bus.d[4];
lock_7ffd <= bus.d[5];
rampage128 <= bus.d_reg[2:0];
screen_page <= bus.d_reg[3];
rompage128 <= bus.d_reg[4];
lock_7ffd <= bus.d_reg[5];
end
end
/* PORT #DFFD */
wire port_dffd_cs = en_profi && bus.ioreq && bus.a == 16'hDFFD;
wire port_dffd_cs = en_profi && bus.ioreq && bus.a_reg == 16'hDFFD;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
rampage_ext <= 0;
@ -112,21 +112,21 @@ always @(posedge clk28 or negedge rst_n) begin
port_dffd_d4 <= 0;
end
else if (port_dffd_cs && bus.wr) begin
rampage_ext <= bus.d[2:0];
port_dffd_d3 <= bus.d[3];
port_dffd_d4 <= bus.d[4];
rampage_ext <= bus.d_reg[2:0];
port_dffd_d3 <= bus.d_reg[3];
port_dffd_d4 <= bus.d_reg[4];
end
end
/* PORT #1FFD */
wire port_1ffd_cs = en_plus3 && bus.ioreq && bus.a == 16'h1FFD;
wire port_1ffd_cs = en_plus3 && bus.ioreq && bus.a_reg == 16'h1FFD;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
port_1ffd <= 0;
end
else if (port_1ffd_cs && bus.wr) begin
port_1ffd <= bus.d[2:0];
port_1ffd <= bus.d_reg[2:0];
end
end
@ -137,7 +137,7 @@ always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)
kempston_rd <= 0;
else
kempston_rd <= en_kempston && bus.ioreq && bus.rd && bus.a[7:5] == 3'b000;
kempston_rd <= en_kempston && bus.ioreq && bus.rd && bus.a_reg[7:5] == 3'b000;
end

18
fpga/rtl/soundrive.sv
View File

@ -12,11 +12,11 @@ module soundrive(
output reg [7:0] ch_r1
);
wire covox_cs = en_covox && bus.ioreq && bus.a[7:0] == 8'hFB;
wire soundrive_a_cs = en_soundrive && bus.ioreq && bus.a[7:0] == 8'h0F;
wire soundrive_b_cs = en_soundrive && bus.ioreq && bus.a[7:0] == 8'h1F;
wire soundrive_c_cs = en_soundrive && bus.ioreq && bus.a[7:0] == 8'h4F;
wire soundrive_d_cs = en_soundrive && bus.ioreq && bus.a[7:0] == 8'h5F;
wire covox_cs = en_covox && bus.ioreq && bus.a_reg[7:0] == 8'hFB;
wire soundrive_a_cs = en_soundrive && bus.ioreq && bus.a_reg[7:0] == 8'h0F;
wire soundrive_b_cs = en_soundrive && bus.ioreq && bus.a_reg[7:0] == 8'h1F;
wire soundrive_c_cs = en_soundrive && bus.ioreq && bus.a_reg[7:0] == 8'h4F;
wire soundrive_d_cs = en_soundrive && bus.ioreq && bus.a_reg[7:0] == 8'h5F;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
@ -27,13 +27,13 @@ always @(posedge clk28 or negedge rst_n) begin
end
else begin
if ((covox_cs || soundrive_a_cs) && bus.wr)
ch_l0 <= bus.d;
ch_l0 <= bus.d_reg;
if ((covox_cs || soundrive_b_cs) && bus.wr)
ch_l1 <= bus.d;
ch_l1 <= bus.d_reg;
if ((covox_cs || soundrive_c_cs) && bus.wr)
ch_r0 <= bus.d;
ch_r0 <= bus.d_reg;
if ((covox_cs || soundrive_d_cs) && bus.wr)
ch_r1 <= bus.d;
ch_r1 <= bus.d_reg;
end
end

45
fpga/rtl/top.sv
View File

@ -51,14 +51,30 @@ pll pll0(.inclk0(clk_in), .c0(clk40), .c1(clk20), .locked(rst_n));
timings_t timings;
turbo_t turbo;
wire clkwait;
wire screen_fetch;
wire screen_fetch, screen_fetch_next;
reg n_iorq_delayed, a_valid;
always @(posedge clk28) begin
n_iorq_delayed <= n_iorq;
a_valid <= screen_read == 0;
end
/* CPU BUS */
cpu_bus bus();
reg bus_memreq, bus_ioreq;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
bus_ioreq <= 0;
bus_memreq <= 0;
end
else if (!screen_fetch && !screen_fetch_next) begin
bus.a_reg <= bus.a;
bus.d_reg <= bus.d;
bus_ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1;
bus_memreq <= n_mreq == 1'b0;
end
else begin
if (n_iorq)
bus_ioreq <= 0;
if (n_mreq)
bus_memreq <= 0;
end
end
assign bus.a = {a[15:13], va[12:0]};
assign bus.d = vd;
assign bus.iorq = ~n_iorq;
@ -67,8 +83,8 @@ assign bus.m1 = ~n_m1;
assign bus.rfsh = ~n_rfsh;
assign bus.rd = ~n_rd;
assign bus.wr = ~n_wr;
assign bus.ioreq = n_m1 == 1'b1 && n_iorq == 1'b0 && a_valid;
assign bus.a_valid = a_valid;
assign bus.ioreq = bus_ioreq & ~n_iorq;
assign bus.memreq = bus_memreq & ~n_mreq;
/* KEYBOARD */
@ -84,7 +100,7 @@ ps2 #(.CLK_FREQ(28_000_000)) ps2_0(
.ps2_dat_in(ps2_dat),
.ps2_clk_out(ps2_clk_out),
.ps2_dat_out(ps2_dat_out),
.zxkb_addr(bus.a[15:8]),
.zxkb_addr(bus.a_reg[15:8]),
.zxkb_data(ps2_kd),
.key_magic(key_magic),
.key_reset(key_reset),
@ -134,6 +150,7 @@ screen screen0(
.blink(blink),
.fetch(screen_fetch),
.fetch_next(screen_fetch_next),
.loading(screen_loading),
.attr_next(attr_next),
@ -175,8 +192,6 @@ assign chroma[2] = (chroma0[2]|chroma0[1])? chroma0[0] : 1'bz;
/* CPU CONTROLLER */
reg [2:0] rampage128;
wire div_wait;
wire [7:0] cpucontrol_dout;
wire cpucontrol_dout_active;
logic n_int_next;
wire snow, clkcpu_ck;
wire init_done;
@ -189,9 +204,6 @@ cpucontrol cpucontrol0(
.bus(bus),
.d_out(cpucontrol_dout),
.d_out_active(cpucontrol_dout_active),
.vc(vc),
.hc(hc),
.rampage128(rampage128),
@ -525,13 +537,14 @@ assign va[18:0] =
{ram_a[18:13], {13{1'bz}}};
assign vd[7:0] =
~n_vrd? {8{1'bz}} :
rom2ram_ram_wren? rom2ram_dataout :
up_dout_active? up_dout :
div_dout_active? div_dout :
turbosound_dout_active? turbosound_dout :
ports_dout_active? ports_dout :
cpucontrol_dout_active? cpucontrol_dout :
{8{1'bz}};
~n_wr? {8{1'bz}} :
8'hFF;
endmodule

12
fpga/rtl/turbosound.sv
View File

@ -24,8 +24,8 @@ reg ay_bc1;
reg ay_sel;
wire ay_rd0 = bus.rd && ay_bc1 == 1'b1 && ay_bdir == 1'b0 && ay_sel == 1'b0;
wire ay_rd1 = bus.rd && ay_bc1 == 1'b1 && ay_bdir == 1'b0 && ay_sel == 1'b1;
wire port_bffd = bus.ioreq && bus.a[15] == 1'b1 && bus.a[1] == 0;
wire port_fffd = bus.ioreq && bus.a[15] == 1'b1 && bus.a[14] == 1'b1 && bus.a[1] == 0;
wire port_bffd = bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[1] == 0;
wire port_fffd = bus.ioreq && bus.a_reg[15] == 1'b1 && bus.a_reg[14] == 1'b1 && bus.a_reg[1] == 0;
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n) begin
ay_bc1 <= 0;
@ -35,8 +35,8 @@ always @(posedge clk28 or negedge rst_n) begin
else begin
ay_bc1 <= en && port_fffd;
ay_bdir <= en && port_bffd && bus.wr;
if (bus.ioreq && port_fffd && bus.wr && bus.d[7:3] == 5'b11111)
ay_sel <= bus.d[0];
if (bus.ioreq && port_fffd && bus.wr && bus.d_reg[7:3] == 5'b11111)
ay_sel <= bus.d_reg[0];
end
end
@ -58,7 +58,7 @@ YM2149 ym2149_0(
.ENA(ay_ck[1]),
.RESET_H(~rst_n),
.I_SEL_L(1'b1),
.I_DA(bus.d),
.I_DA(bus.d_reg),
.O_DA(ay_dout0),
.I_REG(1'b0),
.busctrl_addr(ay_bc1 & ay_bdir & ~ay_sel),
@ -77,7 +77,7 @@ YM2149 ym2149_1(
.ENA(ay_ck[1]),
.RESET_H(~rst_n),
.I_SEL_L(1'b1),
.I_DA(bus.d),
.I_DA(bus.d_reg),
.O_DA(ay_dout1),
.I_REG(1'b0),
.busctrl_addr(ay_bc1 & ay_bdir & ay_sel),

10
fpga/rtl/ulaplus.sv
View File

@ -15,8 +15,8 @@ module ulaplus(
);
wire port_bf3b_cs = en && bus.ioreq && bus.a == 16'hbf3b;
wire port_ff3b_cs = en && bus.ioreq && bus.a == 16'hff3b;
wire port_bf3b_cs = en && bus.ioreq && bus.a_reg == 16'hbf3b;
wire port_ff3b_cs = en && bus.ioreq && bus.a_reg == 16'hff3b;
reg port_ff3b_rd;
wire [7:0] port_ff3b_data = {7'b0000000, active};
@ -32,9 +32,9 @@ always @(posedge clk28 or negedge rst_n) begin
end
else begin
if (port_bf3b_cs && bus.wr)
addr_reg <= bus.d;
addr_reg <= bus.d_reg;
if (port_ff3b_cs && bus.wr && addr_reg == 8'b01000000)
active <= bus.d[0];
active <= bus.d_reg[0];
write_req <= {write_req[0], port_ff3b_cs && bus.wr && addr_reg[7:6] == 2'b00};
port_ff3b_rd <= port_ff3b_cs && bus.rd;
@ -46,7 +46,7 @@ wire write_req0 = write_req[0] && !write_req[1];
reg read_step;
wire [5:0] ram_a = write_req0? addr_reg[5:0] : read_step? ink_addr : paper_addr;
wire [7:0] ram_q;
ram pallete(ram_q, ram_a, bus.d, write_req0, clk28);
ram pallete(ram_q, ram_a, bus.d_reg, write_req0, clk28);
always @(posedge clk28 or negedge rst_n) begin
if (!rst_n)