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7b2b4350bf
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refactor gs register names
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2022-12-17 19:14:00 +03:00 |
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1df71c3c52
|
refactor clocks
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2022-12-17 18:02:57 +03:00 |
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1950bda9c4
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cpld: improve dac output quality
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2022-11-14 22:09:59 +03:00 |
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5c0ca93852
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cpld: fix bit 0 of GS status port
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2022-11-13 21:51:26 +03:00 |
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2b496198bb
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cpld: make additional 32Kb of RAM available for GS
|
2022-11-11 22:01:40 +03:00 |
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a01d8222c3
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fix tsfm port decoding
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2022-01-28 20:20:12 +03:00 |
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b0798eb952
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cpld: don't assert iorqge for general sound ports
For unknown reason it causes issues with 14MHz cpuclk. Further
investigation required.
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2021-10-01 20:35:10 +03:00 |
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5ae1fab818
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cpld: add ports #e?ff for configuration
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2021-07-05 22:06:24 +03:00 |
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3acc38a273
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cpld: optimize gs dacs
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2021-07-05 22:04:24 +03:00 |
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ec75088047
|
add simple testbench
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2021-07-02 21:11:02 +03:00 |
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b1495ede09
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cpld: optimize a bit
|
2021-06-23 20:02:35 +03:00 |
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a764486c8c
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fix read from bffd port
|
2021-06-23 20:02:17 +03:00 |
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2569a40172
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cpld: optimize a bit
|
2021-06-22 21:04:19 +03:00 |
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959e30724f
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top.v: fix indentation
|
2021-06-21 13:27:28 +03:00 |
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1211504d1c
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add cpld firmware
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2021-05-25 19:45:59 +03:00 |
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