mirror of
https://github.com/UzixLS/zx-sizif-512-ext.git
synced 2025-07-18 23:01:26 +03:00
301 lines
8.0 KiB
Verilog
301 lines
8.0 KiB
Verilog
module sizif512_ext(
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input rst_n,
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input clk32,
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input bus0,
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input bus1,
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input [2:0] cfg,
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input clkcpu,
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input [15:0] a,
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inout [7:0] d,
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input n_rd,
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input n_wr,
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input n_iorq,
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input n_mreq,
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input n_m1,
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input n_rfsh,
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input n_int,
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input n_nmi,
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output n_wait,
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output n_busrq,
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input n_busack,
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input n_halt,
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output n_iorqge,
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output n_romcsb,
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output aa0,
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inout [7:0] ad,
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output n_ard,
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output n_awr,
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output ym_m,
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output n_ym1_cs,
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output n_ym2_cs,
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output reg fm1_ena,
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output reg fm2_ena,
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output n_saa_cs,
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output saa_clk,
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output midi_clk,
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input [15:0] ga,
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inout [7:0] gd,
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output n_grst,
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output gclk,
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output reg n_gint,
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input n_grd,
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input n_gwr,
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input n_gm1,
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input n_gmreq,
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input n_giorq,
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output n_grom,
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output n_gram,
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output [18:15] gma,
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output gdac0,
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output gdac1,
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output gdac2,
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output gdac3
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);
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/* MAGIC CONFIGURATION */
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reg ym_ena, saa_ena, gs_ena;
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always @(posedge clkcpu or negedge rst_n) begin
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if (!rst_n) begin
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ym_ena <= cfg[0];
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saa_ena <= cfg[1];
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gs_ena <= cfg[2];
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end
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else if (bus0 && ~n_iorq && ~n_wr && a[7:0] == 8'hFF) case (a[15:8])
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8'hE1: ym_ena <= d[0];
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8'hE2: saa_ena <= d[0];
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8'hE3: gs_ena <= d[0];
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endcase
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end
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wire magic_port = bus0 && a == 16'hE0FF;
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wire [7:0] magic_port_d = {5'b00000, cfg[2:0]};
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/* TURBO SOUND FM */
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wire port_bffd = a[15:14] == 2'b10 && a[1:0] == 2'b01 && ym_ena;
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wire port_fffd = a[15:14] == 2'b11 && a[1:0] == 2'b01 && ym_ena;
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wire port_fffd_full = a[15:13] == 3'b111 && a[1:0] == 2'b01 && ym_ena; // required for compatibility with #dffd port
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reg ym_chip_sel, ym_get_stat;
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wire ym_a0 = (~n_rd & a[14] & ~ym_get_stat) | (~n_wr & ~a[14]);
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assign n_ym1_cs = ~(~ym_chip_sel && (port_bffd || port_fffd) && ~n_iorq && n_m1);
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assign n_ym2_cs = ~( ym_chip_sel && (port_bffd || port_fffd) && ~n_iorq && n_m1);
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always @(posedge clkcpu or negedge rst_n) begin
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if (!rst_n) begin
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ym_chip_sel <= 0;
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ym_get_stat <= 0;
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fm1_ena <= 0;
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fm2_ena <= 0;
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end
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else if (port_fffd && ~n_iorq && ~n_wr && d[7:3] == 5'b11111) begin
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ym_chip_sel <= ~d[0];
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ym_get_stat <= ~d[1];
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fm1_ena <= d[2]? 1'b0 : 1'bz;
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fm2_ena <= d[2]? 1'b0 : 1'bz;
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end
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end
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reg [5:0] ym_m_cnt = 0;
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assign ym_m = ym_m_cnt[5];
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always @(posedge clk32) begin
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ym_m_cnt <= ym_m_cnt + 6'd7;
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end
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/* SAA1099 */
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wire port_ff = a[7:0] == 8'hFF && saa_ena;
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assign n_saa_cs = ~(port_ff && ~n_iorq && ~n_wr);
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wire saa_a0 = a[8];
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reg [1:0] saa_clk_cnt = 0;
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assign saa_clk = saa_clk_cnt[1];
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always @(posedge clk32) begin
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saa_clk_cnt <= saa_clk_cnt + 1'b1;
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end
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/* MIDI */
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reg [2:0] midi_clk_cnt = 0;
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assign midi_clk = midi_clk_cnt[2];
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always @(posedge clk32) begin
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midi_clk_cnt <= midi_clk_cnt + 3'd3;
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end
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/* GENERAL SOUND */
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assign gclk = midi_clk;
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assign n_grst = rst_n;
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reg [8:0] g_int_cnt;
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wire g_int_reload = g_int_cnt[8:6] == 4'b101;
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always @(posedge gclk or negedge rst_n) begin
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if (!rst_n) begin
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g_int_cnt <= 0;
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n_gint <= 1'b1;
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end
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else begin
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if (g_int_reload)
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g_int_cnt <= 0;
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else
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g_int_cnt <= g_int_cnt + 1'b1;
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if (g_int_reload)
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n_gint <= 1'b0;
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else if (g_int_cnt[5])
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n_gint <= 1'b1;
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end
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end
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/* GS EXTERNAL REGISTERS */
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reg [7:0] gs_regb3, gs_regbb;
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wire port_b3 = a[7:0] == 8'hB3 && gs_ena;
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wire port_bb = a[7:0] == 8'hBB && gs_ena;
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always @(posedge clkcpu or negedge rst_n) begin
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if (!rst_n) begin
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gs_regb3 <= 0;
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gs_regbb <= 0;
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end
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else begin
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if (port_b3 && ~n_iorq && ~n_wr)
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gs_regb3 <= d;
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if (port_bb && ~n_iorq && ~n_wr)
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gs_regbb <= d;
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end
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end
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/* GS INTERNAL REGISTERS */
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reg [7:0] gs_reg00, gs_reg03;
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wire [4:0] gs_page = gs_reg00[4:0];
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reg [5:0] gs_vol0, gs_vol1, gs_vol2, gs_vol3;
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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gs_reg00 <= 0;
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gs_reg03 <= 0;
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gs_vol0 <= 0;
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gs_vol1 <= 0;
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gs_vol2 <= 0;
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gs_vol3 <= 0;
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end
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else if (~n_giorq && ~n_gwr) begin
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if (ga[3:0] == 4'h0) gs_reg00 <= gd;
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if (ga[3:0] == 4'h3) gs_reg03 <= gd;
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if (ga[3:0] == 4'h6) gs_vol0 <= gd[5:0];
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if (ga[3:0] == 4'h7) gs_vol1 <= gd[5:0];
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if (ga[3:0] == 4'h8) gs_vol2 <= gd[5:0];
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if (ga[3:0] == 4'h9) gs_vol3 <= gd[5:0];
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end
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end
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reg [7:0] gs_dac0, gs_dac1, gs_dac2, gs_dac3;
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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gs_dac0 <= 0;
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gs_dac1 <= 0;
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gs_dac2 <= 0;
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gs_dac3 <= 0;
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end
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else if (~n_gmreq && ~n_grd && ga[15:13] == 3'b011) begin
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if (ga[9:8] == 2'b00) gs_dac0 <= gd;
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if (ga[9:8] == 2'b01) gs_dac1 <= gd;
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if (ga[9:8] == 2'b10) gs_dac2 <= gd;
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if (ga[9:8] == 2'b11) gs_dac3 <= gd;
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end
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end
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/* GS STATUS REGISTER */
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reg gs_flag_cmd, gs_flag_data;
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wire [7:0] gs_status = {gs_flag_data, 6'b111111, gs_flag_cmd};
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always @(posedge clk32) begin
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if ((~n_giorq && n_gm1 && ga[3:0] == 4'h2) || (~n_iorq && ~n_rd && port_b3))
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gs_flag_data <= 1'b0;
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else if ((~n_giorq && n_gm1 && ga[3:0] == 4'h3) || (~n_iorq && ~n_wr && port_b3))
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gs_flag_data <= 1'b1;
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else if (~n_giorq && n_gm1 && ga[3:0] == 4'hA)
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gs_flag_data <= ~gs_reg00[0];
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end
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always @(posedge clk32) begin
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if (~n_giorq && n_gm1 && ga[3:0] == 4'h5)
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gs_flag_cmd <= 1'b0;
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else if (~n_iorq && ~n_wr && port_bb)
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gs_flag_cmd <= 1'b1;
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else if (~n_giorq && n_gm1 && ga[3:0] == 4'hB)
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gs_flag_cmd <= gs_vol3[5];
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end
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/* GS DAC */
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reg vol0_en, vol1_en, vol2_en, vol3_en;
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reg [5:0] vol_cnt;
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reg [8:0] dac0_cnt, dac1_cnt, dac2_cnt, dac3_cnt;
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assign gdac0 = dac0_cnt[8];
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assign gdac1 = dac1_cnt[8];
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assign gdac2 = dac2_cnt[8];
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assign gdac3 = dac3_cnt[8];
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always @(posedge clk32 or negedge rst_n) begin
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if (!rst_n) begin
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{vol0_en, vol1_en, vol2_en, vol3_en} <= 0;
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vol_cnt <= 0;
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dac0_cnt <= 0;
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dac1_cnt <= 0;
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dac2_cnt <= 0;
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dac3_cnt <= 0;
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end
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else begin
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vol_cnt <= vol_cnt + 6'd31;
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vol0_en <= vol_cnt < gs_vol0;
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vol1_en <= vol_cnt < gs_vol1;
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vol2_en <= vol_cnt < gs_vol2;
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vol3_en <= vol_cnt < gs_vol3;
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if (vol0_en) dac0_cnt <= dac0_cnt[7:0] + gs_dac0; else dac0_cnt[8] <= 0;
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if (vol1_en) dac1_cnt <= dac1_cnt[7:0] + gs_dac1; else dac1_cnt[8] <= 0;
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if (vol2_en) dac2_cnt <= dac2_cnt[7:0] + gs_dac2; else dac2_cnt[8] <= 0;
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if (vol3_en) dac3_cnt <= dac3_cnt[7:0] + gs_dac3; else dac3_cnt[8] <= 0;
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end
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end
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/* GS BUS CONTROLLER */
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assign n_grom = (~n_gmreq && ((ga[15:14] == 2'b00) || (ga[15] == 1'b1 && gs_page == 0)))? 1'b0 : 1'b1;
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assign n_gram = (~n_gmreq && n_grom)? 1'b0 : 1'b1;
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assign gma = (ga[15] == 1'b0)? 4'b0001 : gs_page[3:0];
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assign gd =
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(~n_giorq && ~n_grd && ga[3:0] == 4'h4)? gs_status :
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(~n_giorq && ~n_grd && ga[3:0] == 4'h2)? gs_regb3 :
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(~n_giorq && ~n_grd && ga[3:0] == 4'h1)? gs_regbb :
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(~n_giorq && (~n_grd || ~n_gm1))? {8{1'b1}} :
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{8{1'bz}} ;
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/* BUS CONTROLLER */
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assign n_ard = n_rd | n_iorq;
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assign n_awr = n_wr | n_iorq;
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assign aa0 = n_iorq? aa0 : a[1]? saa_a0 : ym_a0 ;
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assign ad =
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~n_awr && ~n_iorq && (port_fffd || port_bffd || port_ff)? d :
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8'bzzzzzzzz;
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assign n_romcsb = 1'bz;
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assign n_wait = 1'bz;
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assign n_busrq = 1'bz;
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assign n_iorqge = (n_m1 && (port_fffd_full || port_bffd))? 1'b1 : 1'bz;
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assign d =
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~n_rd && ~n_iorq && magic_port? magic_port_d :
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~n_rd && ~n_iorq && port_fffd_full? ad :
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~n_rd && ~n_iorq && port_b3? gs_reg03 :
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~n_rd && ~n_iorq && port_bb? gs_status :
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8'bzzzzzzzz;
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endmodule
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