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https://github.com/UzixLS/zx-sizif-512-ext.git
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cpld: fix bit 0 of GS status port
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@ -209,25 +209,25 @@ always @(posedge clk32 or negedge rst_n) begin
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end
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/* GS STATUS REGISTER */
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reg gs_status0, gs_status7;
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wire [7:0] gs_status = {gs_status7, 6'b111111, gs_status0};
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reg gs_flag_cmd, gs_flag_data;
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wire [7:0] gs_status = {gs_flag_data, 6'b111111, gs_flag_cmd};
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always @(posedge clk32) begin
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if ((~n_giorq && n_gm1 && ga[3:0] == 4'h2) || (~n_iorq && ~n_rd && port_b3))
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gs_status7 <= 1'b0;
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gs_flag_data <= 1'b0;
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else if ((~n_giorq && n_gm1 && ga[3:0] == 4'h3) || (~n_iorq && ~n_wr && port_b3))
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gs_status7 <= 1'b1;
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gs_flag_data <= 1'b1;
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else if (~n_giorq && n_gm1 && ga[3:0] == 4'hA)
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gs_status7 <= ~gs_reg00[0];
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gs_flag_data <= ~gs_reg00[0];
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end
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always @(posedge clk32) begin
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if (~n_giorq && n_gm1 && ga[3:0] == 4'h5)
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gs_status0 <= 1'b0;
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gs_flag_cmd <= 1'b0;
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else if (~n_iorq && ~n_wr && port_bb)
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gs_status0 <= 1'b1;
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gs_flag_cmd <= 1'b1;
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else if (~n_giorq && n_gm1 && ga[3:0] == 4'hB)
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gs_status0 <= gs_vol0[5];
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gs_flag_cmd <= gs_vol3[5];
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end
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/* GS DAC */
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