add cpld firmware template

cpld/clocks.sdc

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+create_clock -period 80MHz -name {clk_80mhz} [get_ports {clk}]

cpld/max.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 15:56:22  December 26, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.0"
+DATE = "15:56:22  December 26, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "max"

cpld/max.qsf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2009 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
+# Date created = 15:56:22  December 26, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		max_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY MAX3000A
+set_global_assignment -name DEVICE "EPM3128ATC100-10"
+set_global_assignment -name TOP_LEVEL_ENTITY top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:56:22  DECEMBER 26, 2019"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_87 -to clk
+set_location_assignment PIN_50 -to cy[0]
+set_location_assignment PIN_49 -to cy[1]
+set_location_assignment PIN_47 -to cy[2]
+set_location_assignment PIN_46 -to cy[3]
+set_location_assignment PIN_45 -to cy[4]
+set_location_assignment PIN_44 -to cy[5]
+set_location_assignment PIN_42 -to cy[6]
+set_location_assignment PIN_41 -to cy[7]
+set_location_assignment PIN_40 -to cy[8]
+set_location_assignment PIN_32 -to cy[9]
+set_location_assignment PIN_31 -to cy[10]
+set_location_assignment PIN_30 -to cy[11]
+set_location_assignment PIN_29 -to cy[12]
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clk_50mhz
+set_instance_assignment -name CLOCK_SETTINGS clk_50mhz -to clk
+set_global_assignment -name SDC_FILE clocks.sdc
+set_global_assignment -name VERILOG_FILE top.v
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
+set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
+set_location_assignment PIN_22 -to flash_si
+set_location_assignment PIN_27 -to flash_reset
+set_location_assignment PIN_28 -to flash_wp
+set_location_assignment PIN_24 -to flash_cs
+set_location_assignment PIN_23 -to flash_sck
+set_location_assignment PIN_68 -to cy_data0
+set_location_assignment PIN_63 -to cy_dclk
+set_location_assignment PIN_67 -to cy_nconfig
+set_location_assignment PIN_21 -to flash_so
+set_location_assignment PIN_16 -to cy_conf_done

cpld/top.v

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+module top(
+	input clk,
+
+	output flash_si,
+	output flash_reset,
+	output flash_wp,
+	output flash_cs,
+	output flash_sck,
+	input flash_so,
+	
+	output cy_dclk,
+	output cy_data0,
+	input cy_nconfig,
+	input cy_conf_done,
+
+	inout [12:0] cy
+);
+
+assign flash_si = 0;
+assign flash_reset = 0;
+assign flash_wp = 0;
+assign flash_cs = 1'b1;
+assign flash_sck = 0;
+
+assign cy_dclk = 0;
+assign cy_data0 = 0;
+
+endmodule