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29 lines
400 B
Verilog
29 lines
400 B
Verilog
module top(
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input clk,
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output flash_si,
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output flash_reset,
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output flash_wp,
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output flash_cs,
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output flash_sck,
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input flash_so,
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output cy_dclk,
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output cy_data0,
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input cy_nconfig,
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input cy_conf_done,
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inout [12:0] cy
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);
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assign flash_si = 0;
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assign flash_reset = 0;
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assign flash_wp = 0;
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assign flash_cs = 1'b1;
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assign flash_sck = 0;
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assign cy_dclk = 0;
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assign cy_data0 = 0;
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endmodule
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