mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
Adjust sound volumes. GS: some refactoring.
This commit is contained in:
sorgelig
@ -89,10 +89,10 @@ begin
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end case;
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end process;
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process(CLK, ENA, RESET)
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process(CLK)
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variable flg : std_logic := '0';
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begin
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if CLK'event and CLK = '1' then
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if rising_edge(CLK) then
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if flg /= RTC(64) then
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seconds_reg <= RTC(7 downto 0);
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minutes_reg <= RTC(15 downto 8);
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158
src/sound/gs.vhd
158
src/sound/gs.vhd
@ -82,10 +82,8 @@ Port (
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RD_n : in std_logic;
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IORQ_n : in std_logic;
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M1_n : in std_logic;
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OUTA : out std_logic_vector(13 downto 0);
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OUTB : out std_logic_vector(13 downto 0);
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OUTC : out std_logic_vector(13 downto 0);
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OUTD : out std_logic_vector(13 downto 0)
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OUTL : out std_logic_vector(14 downto 0);
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OUTR : out std_logic_vector(14 downto 0)
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);
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end gs;
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@ -160,102 +158,91 @@ port map (
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RestorePC_n => '1');
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process (CLKGS, cnt)
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-- INT#
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process (CLKGS)
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begin
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if CLKGS'event and CLKGS = '1' then
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if rising_edge(CLKGS) then
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cnt <= cnt + 1;
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if cnt = "1000110000" then -- 21MHz / 560 = 0.0375MHz = 37.5kHz
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cnt <= (others => '0');
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end if;
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end if;
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end process;
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-- INT#
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process (CLKGS, cpu_iorq_n, cpu_m1_n, cnt)
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begin
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if cpu_iorq_n = '0' and cpu_m1_n = '0' then
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int_n <= '1';
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elsif CLKGS'event and CLKGS = '1' then
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if cnt = "1000110000" then
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int_n <= '0';
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end if;
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if cpu_iorq_n = '0' and cpu_m1_n = '0' then
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int_n <= '1';
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end if;
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end if;
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end process;
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process (CLKGS, cpu_iorq_n, cpu_m1_n, cpu_a_bus, IORQ_n, RD_n, A, WR_n)
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process (CLKGS)
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begin
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if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"2") or (IORQ_n = '0' and RD_n = '0' and A(7 downto 0) = X"B3") then
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bit7_flag <= '0';
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elsif (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"3") or (IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3") then
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bit7_flag <= '1';
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elsif CLKGS'event and CLKGS = '1' then
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if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"A") then
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if rising_edge(CLKGS) then
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if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"2") or (IORQ_n = '0' and RD_n = '0' and A(7 downto 0) = X"B3") then
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bit7_flag <= '0';
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elsif (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"3") or (IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3") then
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bit7_flag <= '1';
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elsif (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"A") then
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bit7_flag <= not port_xx00_reg(0);
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end if;
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end if;
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end process;
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process (CLKGS, cpu_iorq_n, cpu_m1_n, cpu_a_bus, IORQ_n, RD_n, A, WR_n)
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process (CLKGS)
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begin
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if cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"5" then
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bit0_flag <= '0';
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elsif IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then
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bit0_flag <= '1';
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elsif CLKGS'event and CLKGS = '1' then
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if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"B") then
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bit0_flag <= port_xx06_reg(5);
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if rising_edge(CLKGS) then
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if cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"5" then
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bit0_flag <= '0';
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elsif IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then
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bit0_flag <= '1';
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elsif cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"B" then
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bit0_flag <= port_xx09_reg(5);
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end if;
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end if;
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end process;
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process (CLK, A, IORQ_n, WR_n, RESET)
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process (CLK)
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begin
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-- запись со стороны спектрума
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if RESET = '1' then
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port_xxbb_reg <= (others => '0');
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port_xxb3_reg <= (others => '0');
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elsif CLK'event and CLK = '1' then
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if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then port_xxbb_reg <= DI; end if;
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if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3" then port_xxb3_reg <= DI; end if;
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if rising_edge(CLK) then
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if RESET = '1' then
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port_xxbb_reg <= (others => '0');
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port_xxb3_reg <= (others => '0');
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else
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if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then port_xxbb_reg <= DI; end if;
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if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3" then port_xxb3_reg <= DI; end if;
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end if;
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end if;
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end process;
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process (A, bit7_flag, bit0_flag, port_xx03_reg)
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begin
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-- чтение со стороны спектрума
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if A(3) = '1' then -- port #xxBB
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DO <= bit7_flag & "111111" & bit0_flag;
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else -- port #xxB3
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DO <= port_xx03_reg;
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end if;
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end process;
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-- port #xxBB / #xxB3
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DO <= bit7_flag & "111111" & bit0_flag when A(3) = '1' else port_xx03_reg;
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process (CLKGS, RESET, cpu_a_bus, cpu_m1_n, port_xx00_reg)
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process (CLKGS)
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begin
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if RESET = '1' then
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port_xx00_reg <= (others => '0');
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port_xx03_reg <= (others => '0');
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port_xx06_reg <= (others => '0');
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port_xx07_reg <= (others => '0');
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port_xx08_reg <= (others => '0');
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port_xx09_reg <= (others => '0');
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ch_a_reg <= (others => '0');
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ch_b_reg <= (others => '0');
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ch_c_reg <= (others => '0');
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ch_d_reg <= (others => '0');
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elsif CLKGS'event and CLKGS = '1' then
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"0" then port_xx00_reg <= cpu_do_bus; end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"3" then port_xx03_reg <= cpu_do_bus; end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"6" then port_xx06_reg <= cpu_do_bus(5 downto 0); end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"7" then port_xx07_reg <= cpu_do_bus(5 downto 0); end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"8" then port_xx08_reg <= cpu_do_bus(5 downto 0); end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"9" then port_xx09_reg <= cpu_do_bus(5 downto 0); end if;
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if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "00" then ch_a_reg <= ram1_do; end if;
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if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "01" then ch_b_reg <= ram1_do; end if;
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if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "10" then ch_c_reg <= ram1_do; end if;
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if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "11" then ch_d_reg <= ram1_do; end if;
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if rising_edge(CLKGS) then
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if RESET = '1' then
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port_xx00_reg <= (others => '0');
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port_xx03_reg <= (others => '0');
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port_xx06_reg <= (others => '0');
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port_xx07_reg <= (others => '0');
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port_xx08_reg <= (others => '0');
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port_xx09_reg <= (others => '0');
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ch_a_reg <= (others => '0');
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ch_b_reg <= (others => '0');
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ch_c_reg <= (others => '0');
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ch_d_reg <= (others => '0');
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else
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"0" then port_xx00_reg <= cpu_do_bus; end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"3" then port_xx03_reg <= cpu_do_bus; end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"6" then port_xx06_reg <= cpu_do_bus(5 downto 0); end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"7" then port_xx07_reg <= cpu_do_bus(5 downto 0); end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"8" then port_xx08_reg <= cpu_do_bus(5 downto 0); end if;
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if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"9" then port_xx09_reg <= cpu_do_bus(5 downto 0); end if;
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if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "00" then ch_a_reg <= ram1_do; end if;
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if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "01" then ch_b_reg <= ram1_do; end if;
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if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "10" then ch_c_reg <= ram1_do; end if;
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if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "11" then ch_d_reg <= ram1_do; end if;
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end if;
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end if;
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end process;
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@ -267,11 +254,6 @@ cpu_di_bus <=
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port_xxb3_reg when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(3 downto 0) = X"2") else
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"11111111";
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OUTA <= ch_a_reg * port_xx06_reg;
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OUTB <= ch_b_reg * port_xx07_reg;
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OUTC <= ch_c_reg * port_xx08_reg;
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OUTD <= ch_d_reg * port_xx09_reg;
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ram_en <= '1' when cpu_a_bus(15 downto 14) = "01" or (cpu_a_bus(15) = '1' and port_xx00_reg(3 downto 0) /= "0000") else '0';
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ram_we <= not cpu_wr_n and not cpu_mreq_n and ram_en;
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@ -327,4 +309,22 @@ port map
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q => ram2_do
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);
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end gs_unit;
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process (CLKGS)
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begin
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if rising_edge(CLKGS) then
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out_a <= ch_a_reg * port_xx06_reg;
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out_b <= ch_b_reg * port_xx07_reg;
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out_c <= ch_c_reg * port_xx08_reg;
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out_d <= ch_d_reg * port_xx09_reg;
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end if;
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end process;
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process (CLKGS)
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begin
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if rising_edge(CLKGS) then
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OUTL <= ('0'&out_a) + ('0'&out_b);
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OUTR <= ('0'&out_c) + ('0'&out_d);
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end if;
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end process;
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end gs_unit;
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@ -347,10 +347,8 @@ signal hdmi_d1_sig : std_logic;
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signal mouse_do : std_logic_vector(7 downto 0);
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-- General Sound
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signal gs_a : std_logic_vector(13 downto 0);
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signal gs_b : std_logic_vector(13 downto 0);
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signal gs_c : std_logic_vector(13 downto 0);
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signal gs_d : std_logic_vector(13 downto 0);
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signal gs_l : std_logic_vector(14 downto 0);
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signal gs_r : std_logic_vector(14 downto 0);
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signal gs_do_bus : std_logic_vector(7 downto 0);
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-- SAA1099
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@ -1403,10 +1401,8 @@ port map (
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RD_n => cpu_rd_n,
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IORQ_n => cpu_iorq_n,
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M1_n => cpu_m1_n,
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OUTA => gs_a,
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OUTB => gs_b,
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OUTC => gs_c,
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OUTD => gs_d);
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OUTL => gs_l,
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OUTR => gs_r);
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U16: saa1099
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port map(
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@ -1491,7 +1487,7 @@ SD_CS_N <= sdcs_n_TS;
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-- SAA1099
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saa_wr_n <= '0' when (cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(7 downto 0) = "11111111" and dos = '0') else '1';
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SOUND_L <= ("0000" & port_xxfe_reg(4) & "0000000000") + ("0000" & ssg_cn0_a & "000") + ("0000" & ssg_cn0_b & "000") + ("0000" & ssg_cn1_a & "000") + ("0000" & ssg_cn1_b & "000") + ("0000" & covox_a & "000") + ("0000" & covox_b & "000") + ("00" & gs_a) + ("00" & gs_b) + ("0000" & saa_out_l & "000");
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SOUND_R <= ("0000" & port_xxfe_reg(4) & "0000000000") + ("0000" & ssg_cn0_c & "000") + ("0000" & ssg_cn0_b & "000") + ("0000" & ssg_cn1_c & "000") + ("0000" & ssg_cn1_b & "000") + ("0000" & covox_c & "000") + ("0000" & covox_d & "000") + ("00" & gs_c) + ("00" & gs_d) + ("0000" & saa_out_r & "000");
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SOUND_L <= ("000" & port_xxfe_reg(4) & "000000000000") + ("000" & ssg_cn0_a & "00000") + ("0000" & ssg_cn0_b & "0000") + ("000" & ssg_cn1_a & "00000") + ("0000" & ssg_cn1_b & "0000") + ("00" & covox_a & "000000") + ("00" & covox_b & "000000") + ("0" & gs_l) + ("0" & saa_out_l & "0000000");
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SOUND_R <= ("000" & port_xxfe_reg(4) & "000000000000") + ("000" & ssg_cn0_c & "00000") + ("0000" & ssg_cn0_b & "0000") + ("000" & ssg_cn1_c & "00000") + ("0000" & ssg_cn1_b & "0000") + ("00" & covox_c & "000000") + ("00" & covox_d & "000000") + ("0" & gs_r) + ("0" & saa_out_r & "0000000");
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end rtl;
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