diff --git a/src/rtc/mc146818a.vhd b/src/rtc/mc146818a.vhd index 1d94ba5..f8ce701 100644 --- a/src/rtc/mc146818a.vhd +++ b/src/rtc/mc146818a.vhd @@ -89,10 +89,10 @@ begin end case; end process; - process(CLK, ENA, RESET) + process(CLK) variable flg : std_logic := '0'; begin - if CLK'event and CLK = '1' then + if rising_edge(CLK) then if flg /= RTC(64) then seconds_reg <= RTC(7 downto 0); minutes_reg <= RTC(15 downto 8); diff --git a/src/sound/gs.vhd b/src/sound/gs.vhd index b188d3f..1e2f218 100644 --- a/src/sound/gs.vhd +++ b/src/sound/gs.vhd @@ -82,10 +82,8 @@ Port ( RD_n : in std_logic; IORQ_n : in std_logic; M1_n : in std_logic; - OUTA : out std_logic_vector(13 downto 0); - OUTB : out std_logic_vector(13 downto 0); - OUTC : out std_logic_vector(13 downto 0); - OUTD : out std_logic_vector(13 downto 0) + OUTL : out std_logic_vector(14 downto 0); + OUTR : out std_logic_vector(14 downto 0) ); end gs; @@ -160,102 +158,91 @@ port map ( RestorePC_n => '1'); -process (CLKGS, cnt) +-- INT# +process (CLKGS) begin - if CLKGS'event and CLKGS = '1' then + if rising_edge(CLKGS) then cnt <= cnt + 1; if cnt = "1000110000" then -- 21MHz / 560 = 0.0375MHz = 37.5kHz cnt <= (others => '0'); - end if; - end if; -end process; - --- INT# -process (CLKGS, cpu_iorq_n, cpu_m1_n, cnt) -begin - if cpu_iorq_n = '0' and cpu_m1_n = '0' then - int_n <= '1'; - elsif CLKGS'event and CLKGS = '1' then - if cnt = "1000110000" then int_n <= '0'; end if; + if cpu_iorq_n = '0' and cpu_m1_n = '0' then + int_n <= '1'; + end if; end if; end process; -process (CLKGS, cpu_iorq_n, cpu_m1_n, cpu_a_bus, IORQ_n, RD_n, A, WR_n) +process (CLKGS) begin - if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"2") or (IORQ_n = '0' and RD_n = '0' and A(7 downto 0) = X"B3") then - bit7_flag <= '0'; - elsif (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"3") or (IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3") then - bit7_flag <= '1'; - elsif CLKGS'event and CLKGS = '1' then - if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"A") then + if rising_edge(CLKGS) then + if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"2") or (IORQ_n = '0' and RD_n = '0' and A(7 downto 0) = X"B3") then + bit7_flag <= '0'; + elsif (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"3") or (IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3") then + bit7_flag <= '1'; + elsif (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"A") then bit7_flag <= not port_xx00_reg(0); end if; end if; end process; -process (CLKGS, cpu_iorq_n, cpu_m1_n, cpu_a_bus, IORQ_n, RD_n, A, WR_n) +process (CLKGS) begin - if cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"5" then - bit0_flag <= '0'; - elsif IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then - bit0_flag <= '1'; - elsif CLKGS'event and CLKGS = '1' then - if (cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"B") then - bit0_flag <= port_xx06_reg(5); + if rising_edge(CLKGS) then + if cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"5" then + bit0_flag <= '0'; + elsif IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then + bit0_flag <= '1'; + elsif cpu_iorq_n = '0' and cpu_m1_n = '1' and cpu_a_bus(3 downto 0) = X"B" then + bit0_flag <= port_xx09_reg(5); end if; end if; end process; -process (CLK, A, IORQ_n, WR_n, RESET) +process (CLK) begin -- запись со стороны спектрума - if RESET = '1' then - port_xxbb_reg <= (others => '0'); - port_xxb3_reg <= (others => '0'); - elsif CLK'event and CLK = '1' then - if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then port_xxbb_reg <= DI; end if; - if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3" then port_xxb3_reg <= DI; end if; + if rising_edge(CLK) then + if RESET = '1' then + port_xxbb_reg <= (others => '0'); + port_xxb3_reg <= (others => '0'); + else + if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"BB" then port_xxbb_reg <= DI; end if; + if IORQ_n = '0' and WR_n = '0' and A(7 downto 0) = X"B3" then port_xxb3_reg <= DI; end if; + end if; end if; end process; -process (A, bit7_flag, bit0_flag, port_xx03_reg) -begin - -- чтение со стороны спектрума - if A(3) = '1' then -- port #xxBB - DO <= bit7_flag & "111111" & bit0_flag; - else -- port #xxB3 - DO <= port_xx03_reg; - end if; -end process; +-- port #xxBB / #xxB3 +DO <= bit7_flag & "111111" & bit0_flag when A(3) = '1' else port_xx03_reg; -process (CLKGS, RESET, cpu_a_bus, cpu_m1_n, port_xx00_reg) +process (CLKGS) begin - if RESET = '1' then - port_xx00_reg <= (others => '0'); - port_xx03_reg <= (others => '0'); - port_xx06_reg <= (others => '0'); - port_xx07_reg <= (others => '0'); - port_xx08_reg <= (others => '0'); - port_xx09_reg <= (others => '0'); - ch_a_reg <= (others => '0'); - ch_b_reg <= (others => '0'); - ch_c_reg <= (others => '0'); - ch_d_reg <= (others => '0'); - - elsif CLKGS'event and CLKGS = '1' then - if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"0" then port_xx00_reg <= cpu_do_bus; end if; - if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"3" then port_xx03_reg <= cpu_do_bus; end if; - if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"6" then port_xx06_reg <= cpu_do_bus(5 downto 0); end if; - if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"7" then port_xx07_reg <= cpu_do_bus(5 downto 0); end if; - if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"8" then port_xx08_reg <= cpu_do_bus(5 downto 0); end if; - if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"9" then port_xx09_reg <= cpu_do_bus(5 downto 0); end if; - - if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "00" then ch_a_reg <= ram1_do; end if; - if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "01" then ch_b_reg <= ram1_do; end if; - if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "10" then ch_c_reg <= ram1_do; end if; - if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "11" then ch_d_reg <= ram1_do; end if; + if rising_edge(CLKGS) then + if RESET = '1' then + port_xx00_reg <= (others => '0'); + port_xx03_reg <= (others => '0'); + port_xx06_reg <= (others => '0'); + port_xx07_reg <= (others => '0'); + port_xx08_reg <= (others => '0'); + port_xx09_reg <= (others => '0'); + ch_a_reg <= (others => '0'); + ch_b_reg <= (others => '0'); + ch_c_reg <= (others => '0'); + ch_d_reg <= (others => '0'); + else + if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"0" then port_xx00_reg <= cpu_do_bus; end if; + if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"3" then port_xx03_reg <= cpu_do_bus; end if; + if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"6" then port_xx06_reg <= cpu_do_bus(5 downto 0); end if; + if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"7" then port_xx07_reg <= cpu_do_bus(5 downto 0); end if; + if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"8" then port_xx08_reg <= cpu_do_bus(5 downto 0); end if; + if cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(3 downto 0) = X"9" then port_xx09_reg <= cpu_do_bus(5 downto 0); end if; + + if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "00" then ch_a_reg <= ram1_do; end if; + if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "01" then ch_b_reg <= ram1_do; end if; + if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "10" then ch_c_reg <= ram1_do; end if; + if cpu_mreq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(15 downto 13) = "011" and cpu_a_bus(9 downto 8) = "11" then ch_d_reg <= ram1_do; end if; + end if; end if; end process; @@ -267,11 +254,6 @@ cpu_di_bus <= port_xxb3_reg when (cpu_iorq_n = '0' and cpu_rd_n = '0' and cpu_a_bus(3 downto 0) = X"2") else "11111111"; -OUTA <= ch_a_reg * port_xx06_reg; -OUTB <= ch_b_reg * port_xx07_reg; -OUTC <= ch_c_reg * port_xx08_reg; -OUTD <= ch_d_reg * port_xx09_reg; - ram_en <= '1' when cpu_a_bus(15 downto 14) = "01" or (cpu_a_bus(15) = '1' and port_xx00_reg(3 downto 0) /= "0000") else '0'; ram_we <= not cpu_wr_n and not cpu_mreq_n and ram_en; @@ -327,4 +309,22 @@ port map q => ram2_do ); -end gs_unit; \ No newline at end of file +process (CLKGS) +begin + if rising_edge(CLKGS) then + out_a <= ch_a_reg * port_xx06_reg; + out_b <= ch_b_reg * port_xx07_reg; + out_c <= ch_c_reg * port_xx08_reg; + out_d <= ch_d_reg * port_xx09_reg; + end if; +end process; + +process (CLKGS) +begin + if rising_edge(CLKGS) then + OUTL <= ('0'&out_a) + ('0'&out_b); + OUTR <= ('0'&out_c) + ('0'&out_d); + end if; +end process; + +end gs_unit; diff --git a/src/tsconf.vhd b/src/tsconf.vhd index 199ade1..9ee6690 100644 --- a/src/tsconf.vhd +++ b/src/tsconf.vhd @@ -347,10 +347,8 @@ signal hdmi_d1_sig : std_logic; signal mouse_do : std_logic_vector(7 downto 0); -- General Sound -signal gs_a : std_logic_vector(13 downto 0); -signal gs_b : std_logic_vector(13 downto 0); -signal gs_c : std_logic_vector(13 downto 0); -signal gs_d : std_logic_vector(13 downto 0); +signal gs_l : std_logic_vector(14 downto 0); +signal gs_r : std_logic_vector(14 downto 0); signal gs_do_bus : std_logic_vector(7 downto 0); -- SAA1099 @@ -1403,10 +1401,8 @@ port map ( RD_n => cpu_rd_n, IORQ_n => cpu_iorq_n, M1_n => cpu_m1_n, - OUTA => gs_a, - OUTB => gs_b, - OUTC => gs_c, - OUTD => gs_d); + OUTL => gs_l, + OUTR => gs_r); U16: saa1099 port map( @@ -1491,7 +1487,7 @@ SD_CS_N <= sdcs_n_TS; -- SAA1099 saa_wr_n <= '0' when (cpu_iorq_n = '0' and cpu_wr_n = '0' and cpu_a_bus(7 downto 0) = "11111111" and dos = '0') else '1'; -SOUND_L <= ("0000" & port_xxfe_reg(4) & "0000000000") + ("0000" & ssg_cn0_a & "000") + ("0000" & ssg_cn0_b & "000") + ("0000" & ssg_cn1_a & "000") + ("0000" & ssg_cn1_b & "000") + ("0000" & covox_a & "000") + ("0000" & covox_b & "000") + ("00" & gs_a) + ("00" & gs_b) + ("0000" & saa_out_l & "000"); -SOUND_R <= ("0000" & port_xxfe_reg(4) & "0000000000") + ("0000" & ssg_cn0_c & "000") + ("0000" & ssg_cn0_b & "000") + ("0000" & ssg_cn1_c & "000") + ("0000" & ssg_cn1_b & "000") + ("0000" & covox_c & "000") + ("0000" & covox_d & "000") + ("00" & gs_c) + ("00" & gs_d) + ("0000" & saa_out_r & "000"); +SOUND_L <= ("000" & port_xxfe_reg(4) & "000000000000") + ("000" & ssg_cn0_a & "00000") + ("0000" & ssg_cn0_b & "0000") + ("000" & ssg_cn1_a & "00000") + ("0000" & ssg_cn1_b & "0000") + ("00" & covox_a & "000000") + ("00" & covox_b & "000000") + ("0" & gs_l) + ("0" & saa_out_l & "0000000"); +SOUND_R <= ("000" & port_xxfe_reg(4) & "000000000000") + ("000" & ssg_cn0_c & "00000") + ("0000" & ssg_cn0_b & "0000") + ("000" & ssg_cn1_c & "00000") + ("0000" & ssg_cn1_b & "0000") + ("00" & covox_c & "000000") + ("00" & covox_d & "000000") + ("0" & gs_r) + ("0" & saa_out_r & "0000000"); end rtl;