uzix/TSConf_MiST
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OSD option to switch CPU type NMOS/CMOS.

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This commit is contained in:
sorgelig
2018-08-22 00:59:57 +08:00
parent 75557d8fd3
commit dfa92d61b0
5 changed files with 63 additions and 51 deletions
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2
TSConf.sv
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@ -115,6 +115,7 @@ localparam CONF_STR = {
"O34,Stereo mix,None,25%,50%,100%;", "O34,Stereo mix,None,25%,50%,100%;",
"OST,General Sound,512KB,1MB,2MB;", "OST,General Sound,512KB,1MB,2MB;",
"-;", "-;",
"OU,CPU Type,NMOS,CMOS;",
"O67,CPU Speed,3.5MHz,7MHz,14MHz;", "O67,CPU Speed,3.5MHz,7MHz,14MHz;",
"O8,CPU Cache,On,Off;", "O8,CPU Cache,On,Off;",
"O9A,#7FFD span,128K,128K Auto,1024K,512K;", "O9A,#7FFD span,128K,128K Auto,1024K,512K;",
@ -294,6 +295,7 @@ tsconf tsconf
.WARM_RESET(buttons[1]), .WARM_RESET(buttons[1]),
.RESET_OUT(reset), .RESET_OUT(reset),
.RTC(RTC), .RTC(RTC),
.OUT0(status[30]),
.CMOSCfg(CMOSCfg), .CMOSCfg(CMOSCfg),

7
src/t80/T80.vhd
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@ -118,6 +118,7 @@ entity T80 is
IntCycle_n : out std_logic; IntCycle_n : out std_logic;
IntE : out std_logic; IntE : out std_logic;
Stop : out std_logic; Stop : out std_logic;
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
); );
end T80; end T80;
@ -971,7 +972,11 @@ begin
when "1101" => when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8)); BusB <= std_logic_vector(PC(15 downto 8));
when "1110" => when "1110" =>
BusB <= "00000000"; if IR = x"71" and out0 = '1' then
BusB <= "11111111";
else
BusB <= "00000000";
end if;
when others => when others =>
BusB <= "--------"; BusB <= "--------";
end case; end case;

1
src/t80/T80_Pack.vhd
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@ -106,6 +106,7 @@ package T80_Pack is
TS : out std_logic_vector(2 downto 0); TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic; IntCycle_n : out std_logic;
IntE : out std_logic; IntE : out std_logic;
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
Stop : out std_logic; Stop : out std_logic;
REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
); );

2
src/t80/T80s.vhd
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@ -92,6 +92,7 @@ entity T80s is
RFSH_n : out std_logic; RFSH_n : out std_logic;
HALT_n : out std_logic; HALT_n : out std_logic;
BUSAK_n : out std_logic; BUSAK_n : out std_logic;
OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
A : out std_logic_vector(15 downto 0); A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0); DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0) DO : out std_logic_vector(7 downto 0)
@ -135,6 +136,7 @@ begin
DO => DO, DO => DO,
MC => MCycle, MC => MCycle,
TS => TState, TS => TState,
OUT0 => OUT0,
IntCycle_n => IntCycle_n IntCycle_n => IntCycle_n
); );

98
src/tsconf.v
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@ -55,61 +55,62 @@
module tsconf module tsconf
( (
// Clocks // Clocks
input clk_84mhz, input clk_84mhz,
input clk_28mhz, input clk_28mhz,
// SDRAM (32MB 16x16bit) // SDRAM (32MB 16x16bit)
inout [15:0] SDRAM_DQ, inout [15:0] SDRAM_DQ,
output [12:0] SDRAM_A, output [12:0] SDRAM_A,
output [1:0] SDRAM_BA, output [1:0] SDRAM_BA,
output SDRAM_DQML, output SDRAM_DQML,
output SDRAM_DQMH, output SDRAM_DQMH,
output SDRAM_WE_N, output SDRAM_WE_N,
output SDRAM_CAS_N, output SDRAM_CAS_N,
output SDRAM_RAS_N, output SDRAM_RAS_N,
output SDRAM_CKE, output SDRAM_CKE,
output SDRAM_CS_N, output SDRAM_CS_N,
// VGA // VGA
output [7:0] VGA_R, output [7:0] VGA_R,
output [7:0] VGA_G, output [7:0] VGA_G,
output [7:0] VGA_B, output [7:0] VGA_B,
output VGA_HS, output VGA_HS,
output VGA_VS, output VGA_VS,
output VGA_HBLANK, output VGA_HBLANK,
output VGA_VBLANK, output VGA_VBLANK,
output VGA_CEPIX, output VGA_CEPIX,
// SD/MMC Memory Card // SD/MMC Memory Card
input SD_SO, input SD_SO,
output SD_SI, output SD_SI,
output SD_CLK, output SD_CLK,
output SD_CS_N, output SD_CS_N,
// General Sound // General Sound
output [20:0] GS_ADDR, output [20:0] GS_ADDR,
output [7:0] GS_DI, output [7:0] GS_DI,
input [7:0] GS_DO, input [7:0] GS_DO,
output GS_RD, output GS_RD,
output GS_WR, output GS_WR,
input GS_WAIT, input GS_WAIT,
// Audio // Audio
output [15:0] SOUND_L, output [15:0] SOUND_L,
output [15:0] SOUND_R, output [15:0] SOUND_R,
// External I/O // Misc. I/O
input COLD_RESET, input COLD_RESET,
input WARM_RESET, input WARM_RESET,
output RESET_OUT, output RESET_OUT,
input [64:0] RTC, input [64:0] RTC,
input [31:0] CMOSCfg, input [31:0] CMOSCfg,
input OUT0,
// PS/2 Keyboard // PS/2 Keyboard
input [10:0] PS2_KEY, input [10:0] PS2_KEY,
input [24:0] PS2_MOUSE, input [24:0] PS2_MOUSE,
input [5:0] joystick, input [5:0] joystick,
input [15:0] loader_addr, input [15:0] loader_addr,
input [7:0] loader_data, input [7:0] loader_data,
@ -340,6 +341,7 @@ T80s CPU
.RD_n(cpu_rd_n), .RD_n(cpu_rd_n),
.WR_n(cpu_wr_n), .WR_n(cpu_wr_n),
.RFSH_n(cpu_rfsh_n), .RFSH_n(cpu_rfsh_n),
.OUT0(OUT0),
.A(cpu_a_bus), .A(cpu_a_bus),
.DI(cpu_di_bus), .DI(cpu_di_bus),
.DO(cpu_do_bus) .DO(cpu_do_bus)