mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
961 lines
22 KiB
Verilog
961 lines
22 KiB
Verilog
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/* ----------------------------------------------------------------[02.11.2014]
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u16-TSConf Version 0.2.9
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DEVBOARD ReVerSE-U16 By MVV
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----------------------------------------------------------------------------
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V0.1.0 27.07.2014 первая версия
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V0.2.0 31.07.2014 добавлен транслятор PS/2, HDMI
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V0.2.1 03.08.2014 добавлен Delta-Sigma DAC, I2C
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V0.2.3 11.08.2014 добавлен enc424j600
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V0.2.4 24.08.2014 добавлена поддержка IDE Video DAC (zports.v, video_out.v)
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V0.2.5 07.09.2014 добавлен порт #0001=key_scan, изменения в keyboard.vhd
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V0.2.6 09.09.2014 исправлен вывод палитры в (lut.vhd)
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V0.2.7 13.09.2014 дрожание мультиколора на tv80s, заменил на t80s
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V0.2.8 19.10.2014 инвентирован CLK в модулях video_tmbuf, video_sfile и добавлены регистры на выходе
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V0.2.9 02.11.2014 замена t80s, исправления в zint.v, zports.v, delta-sigma (приводит к намагничиванию динамиков)
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WXEDA 10.03.2015 порт на девборду WXEDA
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http://tslabs.info/forum/viewtopic.php?f=31&t=401
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http://zx-pk.ru/showthread.php?t=23528
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Copyright (c) 2014 MVV, TS-Labs, dsp, waybester, palsw
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All rights reserved
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Redistribution and use in source and synthezised forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in synthesized form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the author nor the names of other contributors may
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be used to endorse or promote products derived from this software without
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specific prior written agreement from the author.
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* License is granted for non-commercial use only. A fee may not be charged
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for redistributions as source code or in synthesized/hardware form without
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specific prior written agreement from the author.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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module tsconf
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(
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// Clocks
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input clk_84mhz,
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input clk_28mhz,
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// SDRAM (32MB 16x16bit)
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inout [15:0] SDRAM_DQ,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_WE_N,
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output SDRAM_CAS_N,
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output SDRAM_RAS_N,
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output SDRAM_CKE,
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output SDRAM_CS_N,
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// VGA
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_HBLANK,
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output VGA_VBLANK,
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output VGA_CEPIX,
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// SD/MMC Memory Card
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input SD_SO,
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output SD_SI,
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output SD_CLK,
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output SD_CS_N,
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// General Sound
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output [20:0] GS_ADDR,
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output [7:0] GS_DI,
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input [7:0] GS_DO,
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output GS_RD,
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output GS_WR,
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input GS_WAIT,
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// Audio
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output [15:0] SOUND_L,
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output [15:0] SOUND_R,
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// Misc. I/O
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input COLD_RESET,
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input WARM_RESET,
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output RESET_OUT,
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input [64:0] RTC,
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input [31:0] CMOSCfg,
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input OUT0,
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// PS/2 Keyboard
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input [10:0] PS2_KEY,
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input [24:0] PS2_MOUSE,
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input [5:0] joystick,
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input [15:0] loader_addr,
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input [7:0] loader_data,
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input loader_wr
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);
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// CPU0
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wire [15:0] cpu_a_bus;
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wire [7:0] cpu_do_bus;
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wire [7:0] cpu_di_bus;
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wire cpu_mreq_n;
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wire cpu_iorq_n;
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wire cpu_wr_n;
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wire cpu_rd_n;
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wire cpu_int_n_TS;
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wire cpu_m1_n;
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wire cpu_rfsh_n;
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wire [1:0] turbo;
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wire [7:0] im2vect;
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// zsignal
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wire cpu_stall; // zmem -> zclock
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wire cpu_req; // zmem -> arbiter
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wire cpu_wrbsel; // zmem -> arbiter
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wire cpu_next; // arbiter -> zmem
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wire cpu_current; // arbiter -> zmem
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wire cpu_strobe; // arbiter -> zmem
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wire cpu_latch; // arbiter -> zmem
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wire [23:0] cpu_addr;
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wire [20:0] cpu_addr_20;
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wire csvrom;
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wire curr_cpu;
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// SDRAM
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wire [7:0] sdr_do_bus;
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wire [15:0] sdr_do_bus_16;
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wire [15:0] sdr2cpu_do_bus_16;
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wire sdr_wr;
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wire sdr_rd;
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wire req;
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wire rnw;
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wire [23:0] dram_addr;
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wire [1:0] dram_bsel;
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wire [15:0] dram_wrdata;
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wire dram_req;
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wire dram_rnw;
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wire dos;
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wire [7:0] gluclock_addr;
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// clock
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wire f0;
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wire f1;
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wire h0;
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wire h1;
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wire c0;
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wire c1;
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wire c2;
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wire c3;
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wire zclk;
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wire zpos;
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wire zneg;
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wire vdos;
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wire pre_vdos;
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wire vdos_off;
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wire vdos_on;
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wire dos_change;
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wire m1;
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wire rd;
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wire wr;
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wire iorq;
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wire mreq;
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wire rdwr;
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wire iord;
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wire iowr;
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wire iorw;
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wire memrd;
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wire memwr;
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wire opfetch;
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wire intack;
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wire iorq_s;
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wire iord_s;
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wire iowr_s;
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wire iorw_s;
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wire memwr_s;
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wire opfetch_s;
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// zports OUT
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wire [7:0] dout_ports;
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wire ena_ports;
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wire [31:0] xt_page;
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wire [4:0] fmaddr;
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wire [7:0] sysconf;
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wire [7:0] memconf;
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wire [7:0] intmask;
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wire [8:0] dmaport_wr;
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wire go_arbiter;
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wire [3:0] cacheconf;
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// z80
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wire [15:0] zmd;
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wire [7:0] zma;
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wire cram_we;
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wire sfile_we;
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wire zborder_wr;
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wire border_wr;
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wire zvpage_wr;
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wire vpage_wr;
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wire vconf_wr;
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wire gx_offsl_wr;
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wire gx_offsh_wr;
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wire gy_offsl_wr;
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wire gy_offsh_wr;
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wire t0x_offsl_wr;
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wire t0x_offsh_wr;
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wire t0y_offsl_wr;
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wire t0y_offsh_wr;
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wire t1x_offsl_wr;
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wire t1x_offsh_wr;
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wire t1y_offsl_wr;
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wire t1y_offsh_wr;
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wire tsconf_wr;
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wire palsel_wr;
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wire tmpage_wr;
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wire t0gpage_wr;
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wire t1gpage_wr;
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wire sgpage_wr;
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wire hint_beg_wr;
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wire vint_begl_wr;
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wire vint_begh_wr;
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// ZX controls
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wire res;
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wire int_start_frm;
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wire int_start_lin;
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// DRAM interface
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wire [20:0] video_addr;
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wire [4:0] video_bw;
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wire video_go;
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wire video_next;
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wire video_pre_next;
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wire next_video;
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wire video_strobe;
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wire video_next_strobe;
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// TS
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wire [20:0] ts_addr;
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wire ts_req;
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wire ts_z80_lp;
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// IN
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wire ts_pre_next;
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wire ts_next;
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// TM
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wire [20:0] tm_addr;
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wire tm_req;
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wire tm_next;
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// DMA
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wire dma_rnw;
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wire dma_req;
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wire dma_z80_lp;
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wire [15:0] dma_wrdata;
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wire [20:0] dma_addr;
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wire dma_next;
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wire dma_act;
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wire dma_cram_we;
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wire dma_sfile_we;
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// zmap
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wire [15:0] dma_data;
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wire [7:0] dma_wraddr;
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wire int_start_dma;
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// SPI
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wire spi_stb;
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wire spi_start;
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wire dma_spi_req;
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wire [7:0] dma_spi_din;
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wire cpu_spi_req;
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wire [7:0] cpu_spi_din;
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wire [7:0] spi_dout;
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wire [7:0] mouse_do;
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clock TS01
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(
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.clk(clk_28mhz),
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.f0(f0),
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.f1(f1),
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.h0(h0),
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.h1(h1),
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.c0(c0),
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.c1(c1),
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.c2(c2),
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.c3(c3)
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);
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zclock TS02
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(
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.clk(clk_28mhz),
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.c1(c1),
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.c3(c3),
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.c14Mhz(c1),
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.zclk_out(zclk),
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.zpos(zpos),
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.zneg(zneg),
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.iorq_s(iorq_s),
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.dos_on(dos_change),
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.vdos_off(vdos_off),
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.cpu_stall(cpu_stall),
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.ide_stall(0),
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.external_port(0),
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.turbo(turbo)
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);
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T80s CPU
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(
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.RESET_n(~reset),
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.CLK_n(zclk),
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.INT_n(cpu_int_n_TS),
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.M1_n(cpu_m1_n),
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.MREQ_n(cpu_mreq_n),
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.IORQ_n(cpu_iorq_n),
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.RD_n(cpu_rd_n),
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.WR_n(cpu_wr_n),
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.RFSH_n(cpu_rfsh_n),
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.OUT0(OUT0),
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.A(cpu_a_bus),
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.DI(cpu_di_bus),
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.DO(cpu_do_bus)
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);
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zsignals TS04
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(
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.clk(clk_28mhz),
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.zpos(zpos),
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.iorq_n(cpu_iorq_n),
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.mreq_n(cpu_mreq_n),
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.m1_n(cpu_m1_n),
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.rfsh_n(cpu_rfsh_n),
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.rd_n(cpu_rd_n),
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.wr_n(cpu_wr_n),
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.rd(rd),
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.wr(wr),
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.iorq(iorq),
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.mreq(mreq),
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.rdwr(rdwr),
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.iord(iord),
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.iowr(iowr),
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.iorw(iorw),
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.memrd(memrd),
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.memwr(memwr),
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.opfetch(opfetch),
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.intack(intack),
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.iorq_s(iorq_s),
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.iord_s(iord_s),
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.iowr_s(iowr_s),
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.iorw_s(iorw_s),
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.memwr_s(memwr_s),
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.opfetch_s(opfetch_s)
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);
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zports TS05
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(
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.zclk(zclk),
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.clk(clk_28mhz),
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.din(cpu_do_bus),
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.dout(dout_ports),
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.dataout(ena_ports),
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.a(cpu_a_bus),
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.rst(reset),
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.loader(0), //loader, -- for load ROM, SPI should be enable
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.opfetch(opfetch), // from zsignals
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.rd(rd),
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.wr(wr),
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.rdwr(rdwr),
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.iorq(iorq),
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.iorq_s(iorq_s),
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.iord(iord),
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.iord_s(iord_s),
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.iowr(iowr),
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.iowr_s(iowr_s),
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.iorw(iorw),
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.iorw_s(iorw_s),
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.external_port(), // asserts for AY and VG93 accesses
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.zborder_wr(zborder_wr),
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.border_wr(border_wr),
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.zvpage_wr(zvpage_wr),
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.vpage_wr(vpage_wr),
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.vconf_wr(vconf_wr),
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.gx_offsl_wr(gx_offsl_wr),
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.gx_offsh_wr(gx_offsh_wr),
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.gy_offsl_wr(gy_offsl_wr),
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.gy_offsh_wr(gy_offsh_wr),
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.t0x_offsl_wr(t0x_offsl_wr),
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.t0x_offsh_wr(t0x_offsh_wr),
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.t0y_offsl_wr(t0y_offsl_wr),
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.t0y_offsh_wr(t0y_offsh_wr),
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.t1x_offsl_wr(t1x_offsl_wr),
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.t1x_offsh_wr(t1x_offsh_wr),
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.t1y_offsl_wr(t1y_offsl_wr),
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.t1y_offsh_wr(t1y_offsh_wr),
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.tsconf_wr(tsconf_wr),
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.palsel_wr(palsel_wr),
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.tmpage_wr(tmpage_wr),
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.t0gpage_wr(t0gpage_wr),
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.t1gpage_wr(t1gpage_wr),
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.sgpage_wr(sgpage_wr),
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.hint_beg_wr(hint_beg_wr),
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.vint_begl_wr(vint_begl_wr),
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.vint_begh_wr(vint_begh_wr),
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.xt_page(xt_page),
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.fmaddr(fmaddr),
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.sysconf(sysconf),
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.memconf(memconf),
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.cacheconf(cacheconf),
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.intmask(intmask),
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.dmaport_wr(dmaport_wr), // dmaport_wr
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.dma_act(dma_act), // from DMA (status of DMA)
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.dos(dos),
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.vdos(vdos),
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.vdos_on(vdos_on),
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.vdos_off(vdos_off),
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.rstrom(2'b11),
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.tape_read(1),
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.keys_in(kb_do_bus), // keys (port FE)
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.mus_in(mouse_do), // mouse (xxDF)
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.kj_in(joystick),
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.vg_intrq(0),
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.vg_drq(0), // from vg93 module - drq + irq read
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.sdcs_n(SD_CS_N), // to SD card
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.sd_start(cpu_spi_req), // to SPI
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.sd_datain(cpu_spi_din), // to SPI(7 downto 0);
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.sd_dataout(spi_dout), // from SPI(7 downto 0);
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.gluclock_addr(gluclock_addr),
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.wait_read(mc146818a_do_bus),
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.com_data_rx(8'b00000000), //uart_do_bus,
|
|
.com_status(8'b10010000), //'1' & uart_tx_empty & uart_tx_fifo_empty & "1000" & uart_rx_avail,
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//com_status=> '0' & uart_tx_empty & uart_tx_fifo_empty & "0000" & '1',
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.lock_conf(1)
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);
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zmem TS06
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(
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.clk(clk_28mhz),
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.c0(c0),
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.c1(c1),
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.c2(c2),
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.c3(c3),
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.zneg(zneg),
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.zpos(zpos),
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.rst(reset), // PLL locked
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.za(cpu_a_bus), // from CPU
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.zd_out(sdr_do_bus), // output to Z80 bus 8bit ==>
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.zd_ena(), // output to Z80 bus enable
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.opfetch(opfetch), // from zsignals
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.opfetch_s(opfetch_s), // from zsignals
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.mreq(mreq), // from zsignals
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.memrd(memrd), // from zsignals
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.memwr(memwr), // from zsignals
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.memwr_s(memwr_s), // from zsignals
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.turbo(turbo),
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.cache_en(cacheconf), // from zport
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|
.memconf(memconf[3:0]),
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.xt_page(xt_page),
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.csvrom(csvrom),
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.dos(dos),
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.dos_change(dos_change),
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.vdos(vdos),
|
|
.pre_vdos(pre_vdos),
|
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.vdos_on(vdos_on),
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|
.vdos_off(vdos_off),
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.cpu_req(cpu_req),
|
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.cpu_addr(cpu_addr_20),
|
|
.cpu_wrbsel(cpu_wrbsel), // for 16bit data
|
|
.cpu_rddata(sdr2cpu_do_bus_16),
|
|
.cpu_next(cpu_next),
|
|
.cpu_strobe(cpu_strobe), // from ARBITER ACTIVE=HI
|
|
.cpu_latch(cpu_latch),
|
|
.cpu_stall(cpu_stall), // for Zclock if HI-> STALL (ZCLK)
|
|
.loader(0), // ROM for loader active
|
|
.testkey(1),
|
|
.intt(0)
|
|
);
|
|
|
|
arbiter TS07
|
|
(
|
|
.clk(clk_28mhz),
|
|
.c0(c0),
|
|
.c1(c1),
|
|
.c2(c2),
|
|
.c3(c3),
|
|
.dram_addr(dram_addr),
|
|
.dram_req(dram_req),
|
|
.dram_rnw(dram_rnw),
|
|
.dram_bsel(dram_bsel),
|
|
.dram_wrdata(dram_wrdata), // data to be written
|
|
.video_addr({3'b000, video_addr}), // during access block, only when video_strobe==1
|
|
.go(go_arbiter), // start video access blocks
|
|
.video_bw(video_bw), // ZX="11001", [4:3] -total cycles: 11 = 8 / 01 = 4 / 00 = 2
|
|
.video_pre_next(video_pre_next),
|
|
.video_next(video_next), // (c2) at this signal video_addr may be changed; it is one clock leading the video_strobe
|
|
.video_strobe(video_strobe), // (c3) one-cycle strobe meaning that video_data is available
|
|
.video_next_strobe(video_next_strobe),
|
|
.next_vid(next_video), // used for TM prefetch
|
|
.cpu_addr({csvrom, 2'b00, cpu_addr_20}),
|
|
.cpu_wrdata(cpu_do_bus),
|
|
.cpu_req(cpu_req),
|
|
.cpu_rnw(rd),
|
|
.cpu_wrbsel(cpu_wrbsel),
|
|
.cpu_next(cpu_next), // next cycle is allowed to be used by CPU
|
|
.cpu_strobe(cpu_strobe), // c2 strobe
|
|
.cpu_latch(cpu_latch), // c2-c3 strobe
|
|
.curr_cpu_o(curr_cpu),
|
|
.dma_addr({3'b000, dma_addr}),
|
|
.dma_wrdata(dma_wrdata),
|
|
.dma_req(dma_req),
|
|
.dma_z80_lp(dma_z80_lp),
|
|
.dma_rnw(dma_rnw),
|
|
.dma_next(dma_next),
|
|
.ts_addr({3'b000, ts_addr}),
|
|
.ts_req(ts_req),
|
|
.ts_z80_lp(ts_z80_lp),
|
|
.ts_pre_next(ts_pre_next),
|
|
.ts_next(ts_next),
|
|
.tm_addr({3'b000, tm_addr}),
|
|
.tm_req(tm_req),
|
|
.tm_next(tm_next)
|
|
);
|
|
|
|
video_top TS08
|
|
(
|
|
.clk(clk_28mhz),
|
|
.f0(f0),
|
|
.f1(f1),
|
|
.h0(h0),
|
|
.h1(h1),
|
|
.c0(c0),
|
|
.c1(c1),
|
|
.c2(c2),
|
|
.c3(c3),
|
|
.vred(VGA_R),
|
|
.vgrn(VGA_G),
|
|
.vblu(VGA_B),
|
|
.hsync(VGA_HS),
|
|
.vsync(VGA_VS),
|
|
.hblank(VGA_HBLANK),
|
|
.vblank(VGA_VBLANK),
|
|
.pix_stb(VGA_CEPIX),
|
|
.a(cpu_a_bus),
|
|
.d(cpu_do_bus),
|
|
.zmd(zmd),
|
|
.zma(zma),
|
|
.cram_we(cram_we),
|
|
.sfile_we(sfile_we),
|
|
.zborder_wr(zborder_wr),
|
|
.border_wr(border_wr),
|
|
.zvpage_wr(zvpage_wr),
|
|
.vpage_wr(vpage_wr),
|
|
.vconf_wr(vconf_wr),
|
|
.gx_offsl_wr(gx_offsl_wr),
|
|
.gx_offsh_wr(gx_offsh_wr),
|
|
.gy_offsl_wr(gy_offsl_wr),
|
|
.gy_offsh_wr(gy_offsh_wr),
|
|
.t0x_offsl_wr(t0x_offsl_wr),
|
|
.t0x_offsh_wr(t0x_offsh_wr),
|
|
.t0y_offsl_wr(t0y_offsl_wr),
|
|
.t0y_offsh_wr(t0y_offsh_wr),
|
|
.t1x_offsl_wr(t1x_offsl_wr),
|
|
.t1x_offsh_wr(t1x_offsh_wr),
|
|
.t1y_offsl_wr(t1y_offsl_wr),
|
|
.t1y_offsh_wr(t1y_offsh_wr),
|
|
.tsconf_wr(tsconf_wr),
|
|
.palsel_wr(palsel_wr),
|
|
.tmpage_wr(tmpage_wr),
|
|
.t0gpage_wr(t0gpage_wr),
|
|
.t1gpage_wr(t1gpage_wr),
|
|
.sgpage_wr(sgpage_wr),
|
|
.hint_beg_wr(hint_beg_wr),
|
|
.vint_begl_wr(vint_begl_wr),
|
|
.vint_begh_wr(vint_begh_wr),
|
|
.res(reset),
|
|
.int_start(int_start_frm),
|
|
.line_start_s(int_start_lin),
|
|
.video_addr(video_addr),
|
|
.video_bw(video_bw),
|
|
.video_go(go_arbiter),
|
|
.dram_rdata(sdr_do_bus_16), // raw, should be latched by c2 (video_next)
|
|
.video_next(video_next),
|
|
.video_pre_next(video_pre_next),
|
|
.next_video(next_video),
|
|
.video_strobe(video_strobe),
|
|
.video_next_strobe(video_next_strobe),
|
|
.ts_addr(ts_addr),
|
|
.ts_req(ts_req),
|
|
.ts_z80_lp(ts_z80_lp),
|
|
.ts_pre_next(ts_pre_next),
|
|
.ts_next(ts_next),
|
|
.tm_addr(tm_addr),
|
|
.tm_req(tm_req),
|
|
.tm_next(tm_next),
|
|
.cfg_60hz(1), // 0-60Hz, 1-48Hz
|
|
.sync_pol(0), // 0-positive, 1-negative
|
|
.vga_on(0) // 1-31kHZ
|
|
);
|
|
|
|
dma TS09
|
|
(
|
|
.clk(clk_28mhz),
|
|
.c2(c2),
|
|
.reset(reset),
|
|
.dmaport_wr(dmaport_wr),
|
|
.dma_act(dma_act),
|
|
.data(dma_data),
|
|
.wraddr(dma_wraddr),
|
|
.int_start(int_start_dma),
|
|
.zdata(cpu_do_bus),
|
|
.dram_addr(dma_addr),
|
|
.dram_rddata(sdr_do_bus_16),
|
|
.dram_wrdata(dma_wrdata),
|
|
.dram_req(dma_req),
|
|
.dma_z80_lp(dma_z80_lp),
|
|
.dram_rnw(dma_rnw),
|
|
.dram_next(dma_next),
|
|
.spi_rddata(spi_dout),
|
|
.spi_wrdata(dma_spi_din),
|
|
.spi_req(dma_spi_req),
|
|
.spi_stb(spi_stb),
|
|
.spi_start(spi_start),
|
|
.ide_in(0),
|
|
.ide_stb(0),
|
|
.cram_we(dma_cram_we),
|
|
.sfile_we(dma_sfile_we)
|
|
);
|
|
|
|
zmaps TS10
|
|
(
|
|
.clk(clk_28mhz),
|
|
.memwr_s(memwr_s),
|
|
.a(cpu_a_bus),
|
|
.d(cpu_do_bus),
|
|
.fmaddr(fmaddr),
|
|
.zmd(zmd),
|
|
.zma(zma),
|
|
.dma_data(dma_data),
|
|
.dma_wraddr(dma_wraddr),
|
|
.dma_cram_we(dma_cram_we),
|
|
.dma_sfile_we(dma_sfile_we),
|
|
.cram_we(cram_we),
|
|
.sfile_we(sfile_we)
|
|
);
|
|
|
|
spi TS11
|
|
(
|
|
.clk(clk_28mhz),
|
|
.sck(SD_CLK),
|
|
.sdo(SD_SI),
|
|
.sdi(SD_SO),
|
|
.stb(spi_stb),
|
|
.start(spi_start),
|
|
.dma_req(dma_spi_req),
|
|
.dma_din(dma_spi_din),
|
|
.cpu_req(cpu_spi_req),
|
|
.cpu_din(cpu_spi_din),
|
|
.dout(spi_dout),
|
|
.speed(0)
|
|
);
|
|
|
|
zint TS13
|
|
(
|
|
.clk(clk_28mhz),
|
|
.zclk(zclk),
|
|
.res(reset),
|
|
.int_start_frm(int_start_frm), //< N1 VIDEO
|
|
.int_start_lin(int_start_lin), //< N2 VIDEO
|
|
.int_start_dma(int_start_dma), //< N3 DMA
|
|
.vdos(pre_vdos), // vdos,--pre_vdos
|
|
.intack(intack), //< zsignals === (intack ? im2vect : 8'hFF)));
|
|
.intmask(intmask), //< ZPORT (7 downto 0);
|
|
.im2vect(im2vect), //> CPU Din (2 downto 0);
|
|
.int_n(cpu_int_n_TS)
|
|
);
|
|
|
|
// BIOS
|
|
wire [7:0] bios_do_bus;
|
|
dpram #(.ADDRWIDTH(16), .MEM_INIT_FILE("tsbios.mif")) BIOS
|
|
(
|
|
.clock(clk_28mhz),
|
|
.address_a({cpu_addr_20[14:0],cpu_wrbsel}),
|
|
.q_a(bios_do_bus),
|
|
|
|
.address_b(loader_addr),
|
|
.data_b(loader_data),
|
|
.wren_b(loader_wr)
|
|
);
|
|
|
|
// SDRAM Controller
|
|
sdram SE4
|
|
(
|
|
.clk(clk_84mhz),
|
|
.clk_28mhz(clk_28mhz),
|
|
.c0(c0),
|
|
.c3(c3),
|
|
.curr_cpu(curr_cpu), // from arbiter for luch DO_cpu
|
|
.loader(0), // loader = 1: wr to ROM
|
|
.bsel(dram_bsel),
|
|
.a(dram_addr),
|
|
.di(dram_wrdata),
|
|
.do(sdr_do_bus_16),
|
|
.do_cpu(sdr2cpu_do_bus_16),
|
|
.req(dram_req),
|
|
.rnw(dram_rnw),
|
|
.cke(SDRAM_CKE),
|
|
.ras_n(SDRAM_RAS_N),
|
|
.cas_n(SDRAM_CAS_N),
|
|
.we_n(SDRAM_WE_N),
|
|
.cs_n(SDRAM_CS_N),
|
|
.ba(SDRAM_BA),
|
|
.ma(SDRAM_A),
|
|
.dq(SDRAM_DQ[15:0]),
|
|
.dqml(SDRAM_DQML),
|
|
.dqmh(SDRAM_DQMH)
|
|
);
|
|
|
|
|
|
// PS/2 Keyboard
|
|
wire [4:0] kb_do_bus;
|
|
wire key_reset;
|
|
wire [7:0] key_scancode;
|
|
|
|
keyboard SE5
|
|
(
|
|
.clk(clk_28mhz),
|
|
.reset(COLD_RESET | WARM_RESET),
|
|
.a(cpu_a_bus[15:8]),
|
|
.keyb(kb_do_bus),
|
|
.KEY_RESET(key_reset),
|
|
.scancode(key_scancode),
|
|
.ps2_key(PS2_KEY)
|
|
);
|
|
|
|
kempston_mouse KM
|
|
(
|
|
.clk_sys(clk_28mhz),
|
|
.reset(reset),
|
|
.ps2_mouse(PS2_MOUSE),
|
|
.addr(cpu_a_bus[10:8]),
|
|
.dout(mouse_do)
|
|
);
|
|
|
|
// MC146818A,RTC
|
|
wire mc146818a_wr = port_bff7 && ~cpu_wr_n;
|
|
wire [7:0] mc146818a_do_bus;
|
|
wire port_bff7 = ~cpu_iorq_n && cpu_a_bus == 16'hBFF7 && cpu_m1_n && port_eff7_reg[7];
|
|
|
|
reg ena_0_4375mhz;
|
|
always @(negedge clk_28mhz) begin
|
|
reg [5:0] div;
|
|
div <= div + 1'd1;
|
|
ena_0_4375mhz <= !div; //28MHz/64
|
|
end
|
|
|
|
reg [7:0] port_eff7_reg;
|
|
always @(posedge clk_28mhz) begin
|
|
if (reset) port_eff7_reg <= 0;
|
|
else if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus == 16'hEFF7) port_eff7_reg <= cpu_do_bus; //for RTC
|
|
end
|
|
|
|
mc146818a SE9
|
|
(
|
|
.RESET(reset),
|
|
.CLK(clk_28mhz),
|
|
.ENA(ena_0_4375mhz),
|
|
.CS(1),
|
|
.KEYSCANCODE(key_scancode),
|
|
.RTC(RTC),
|
|
.CMOSCfg(CMOSCfg),
|
|
.WR(mc146818a_wr),
|
|
.A(gluclock_addr[7:0]),
|
|
.DI(cpu_do_bus),
|
|
.DO(mc146818a_do_bus)
|
|
);
|
|
|
|
|
|
// Soundrive
|
|
wire [7:0] covox_a;
|
|
wire [7:0] covox_b;
|
|
wire [7:0] covox_c;
|
|
wire [7:0] covox_d;
|
|
|
|
soundrive SE10
|
|
(
|
|
.reset(reset),
|
|
.clk(clk_28mhz),
|
|
.cs(1),
|
|
.wr_n(cpu_wr_n),
|
|
.a(cpu_a_bus[7:0]),
|
|
.di(cpu_do_bus),
|
|
.iorq_n(cpu_iorq_n),
|
|
.dos(dos),
|
|
.outa(covox_a),
|
|
.outb(covox_b),
|
|
.outc(covox_c),
|
|
.outd(covox_d)
|
|
);
|
|
|
|
// Turbosound FM
|
|
reg ce_ym, ce_cpu;
|
|
always @(posedge clk_28mhz) begin
|
|
reg [1:0] div;
|
|
|
|
div <= div + 1'd1;
|
|
ce_ym <= !div;
|
|
|
|
ce_cpu <= zclk;
|
|
if(ce_cpu) ce_cpu <= 0;
|
|
end
|
|
|
|
wire ts_enable = ~cpu_iorq_n & cpu_a_bus[0] & cpu_a_bus[15] & ~cpu_a_bus[1];
|
|
wire ts_we = ts_enable & ~cpu_wr_n;
|
|
|
|
wire [11:0] ts_l, ts_r;
|
|
wire [7:0] ts_do;
|
|
|
|
turbosound SE12
|
|
(
|
|
.RESET(reset),
|
|
|
|
.CLK(clk_28mhz),
|
|
.CE_CPU(ce_cpu),
|
|
.CE_YM(ce_ym),
|
|
.BDIR(ts_we),
|
|
.BC(cpu_a_bus[14]),
|
|
.DI(cpu_do_bus),
|
|
.DO(ts_do),
|
|
.CHANNEL_L(ts_l),
|
|
.CHANNEL_R(ts_r)
|
|
);
|
|
|
|
|
|
// General Sound
|
|
reg ce_gs;
|
|
always @(posedge clk_84mhz) begin
|
|
ce_gs <= clk_28mhz;
|
|
if(ce_gs) ce_gs <= 0;
|
|
end
|
|
|
|
wire [14:0] gs_l;
|
|
wire [14:0] gs_r;
|
|
wire [7:0] gs_do_bus;
|
|
wire gs_sel = ~cpu_iorq_n & cpu_m1_n & (cpu_a_bus[7:4] == 'hB && cpu_a_bus[2:0] == 'h3);
|
|
|
|
gs #("src/sound/gs105b.mif") U15
|
|
(
|
|
.RESET(reset),
|
|
.CLK(clk_84mhz),
|
|
.CE(ce_gs),
|
|
|
|
.A(cpu_a_bus[3]),
|
|
.DI(cpu_do_bus),
|
|
.DO(gs_do_bus),
|
|
.CS_n(cpu_iorq_n | ~gs_sel),
|
|
.WR_n(cpu_wr_n),
|
|
.RD_n(cpu_rd_n),
|
|
|
|
.MEM_ADDR(GS_ADDR),
|
|
.MEM_DI(GS_DI),
|
|
.MEM_DO(GS_DO),
|
|
.MEM_RD(GS_RD),
|
|
.MEM_WR(GS_WR),
|
|
.MEM_WAIT(GS_WAIT),
|
|
|
|
.OUTL(gs_l),
|
|
.OUTR(gs_r)
|
|
);
|
|
|
|
|
|
// SAA1099
|
|
wire [7:0] saa_out_l;
|
|
wire [7:0] saa_out_r;
|
|
wire saa_wr_n = ~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFF && ~dos;
|
|
|
|
reg ce_saa;
|
|
always @(posedge clk_28mhz) begin
|
|
reg [2:0] div;
|
|
|
|
div <= div + 1'd1;
|
|
if(div == 6) div <= 0;
|
|
|
|
ce_saa <= (div == 0 || div == 3);
|
|
end
|
|
|
|
saa1099 U16
|
|
(
|
|
.clk_sys(clk_28mhz),
|
|
.ce(ce_saa),
|
|
.rst_n(~reset),
|
|
.cs_n(0),
|
|
.a0(cpu_a_bus[8]), // 0=data, 1=address
|
|
.wr_n(saa_wr_n),
|
|
.din(cpu_do_bus),
|
|
.out_l(saa_out_l),
|
|
.out_r(saa_out_r)
|
|
);
|
|
|
|
wire [11:0] audio_l = ts_l + {gs_l[14], gs_l[14:4]} + {2'b00, covox_a, 2'b00} + {2'b00, covox_b, 2'b00} + {1'b0, saa_out_l, 3'b000} + {3'b000, port_xxfe_reg[4], 8'b00000000};
|
|
wire [11:0] audio_r = ts_r + {gs_r[14], gs_r[14:4]} + {2'b00, covox_c, 2'b00} + {2'b00, covox_d, 2'b00} + {1'b0, saa_out_r, 3'b000} + {3'b000, port_xxfe_reg[4], 8'b00000000};
|
|
|
|
compressor compressor
|
|
(
|
|
clk_28mhz,
|
|
audio_l, audio_r,
|
|
SOUND_L, SOUND_R
|
|
);
|
|
|
|
|
|
//-----------------------------------------------------------------------------
|
|
// Global
|
|
//-----------------------------------------------------------------------------
|
|
wire reset = COLD_RESET | WARM_RESET | key_reset;
|
|
assign RESET_OUT = reset;
|
|
|
|
// CPU interface
|
|
assign cpu_di_bus =
|
|
(csvrom && ~cpu_mreq_n && ~cpu_rd_n) ? bios_do_bus : // BIOS
|
|
(~cpu_mreq_n && ~cpu_rd_n) ? sdr_do_bus : // SDRAM
|
|
(intack) ? im2vect :
|
|
(port_bff7 && port_eff7_reg[7] && ~cpu_iorq_n && ~cpu_rd_n) ? mc146818a_do_bus : // MC146818A
|
|
(gs_sel && ~cpu_rd_n) ? gs_do_bus : // General Sound
|
|
(ts_enable && ~cpu_rd_n) ? ts_do : // TurboSound
|
|
(cpu_a_bus == 16'h0001 && ~cpu_iorq_n && ~cpu_rd_n) ? key_scancode :
|
|
(ena_ports) ? dout_ports :
|
|
8'b11111111;
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// TURBO
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assign turbo = sysconf[1:0];
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reg [7:0] port_xxfe_reg;
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always @(posedge clk_28mhz) begin
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if (reset) port_xxfe_reg <= 0;
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else if (~cpu_iorq_n && ~cpu_wr_n && cpu_a_bus[7:0] == 8'hFE) port_xxfe_reg <= cpu_do_bus;
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end
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endmodule
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