mirror of
https://github.com/UzixLS/TSConf_MiST.git
synced 2025-07-18 14:51:25 +03:00
OSD option to switch CPU type NMOS/CMOS.
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@ -115,6 +115,7 @@ localparam CONF_STR = {
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"O34,Stereo mix,None,25%,50%,100%;",
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"O34,Stereo mix,None,25%,50%,100%;",
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"OST,General Sound,512KB,1MB,2MB;",
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"OST,General Sound,512KB,1MB,2MB;",
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"-;",
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"-;",
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"OU,CPU Type,NMOS,CMOS;",
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"O67,CPU Speed,3.5MHz,7MHz,14MHz;",
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"O67,CPU Speed,3.5MHz,7MHz,14MHz;",
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"O8,CPU Cache,On,Off;",
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"O8,CPU Cache,On,Off;",
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"O9A,#7FFD span,128K,128K Auto,1024K,512K;",
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"O9A,#7FFD span,128K,128K Auto,1024K,512K;",
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@ -294,6 +295,7 @@ tsconf tsconf
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.WARM_RESET(buttons[1]),
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.WARM_RESET(buttons[1]),
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.RESET_OUT(reset),
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.RESET_OUT(reset),
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.RTC(RTC),
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.RTC(RTC),
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.OUT0(status[30]),
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.CMOSCfg(CMOSCfg),
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.CMOSCfg(CMOSCfg),
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@ -118,6 +118,7 @@ entity T80 is
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IntCycle_n : out std_logic;
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IntCycle_n : out std_logic;
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IntE : out std_logic;
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IntE : out std_logic;
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Stop : out std_logic;
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Stop : out std_logic;
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out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
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REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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);
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);
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end T80;
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end T80;
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@ -971,7 +972,11 @@ begin
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when "1101" =>
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when "1101" =>
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BusB <= std_logic_vector(PC(15 downto 8));
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BusB <= std_logic_vector(PC(15 downto 8));
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when "1110" =>
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when "1110" =>
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if IR = x"71" and out0 = '1' then
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BusB <= "11111111";
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else
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BusB <= "00000000";
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BusB <= "00000000";
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end if;
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when others =>
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when others =>
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BusB <= "--------";
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BusB <= "--------";
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end case;
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end case;
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@ -106,6 +106,7 @@ package T80_Pack is
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TS : out std_logic_vector(2 downto 0);
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TS : out std_logic_vector(2 downto 0);
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IntCycle_n : out std_logic;
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IntCycle_n : out std_logic;
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IntE : out std_logic;
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IntE : out std_logic;
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out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
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Stop : out std_logic;
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Stop : out std_logic;
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REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
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);
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);
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@ -92,6 +92,7 @@ entity T80s is
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RFSH_n : out std_logic;
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RFSH_n : out std_logic;
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HALT_n : out std_logic;
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HALT_n : out std_logic;
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BUSAK_n : out std_logic;
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BUSAK_n : out std_logic;
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OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
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A : out std_logic_vector(15 downto 0);
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A : out std_logic_vector(15 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0)
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DO : out std_logic_vector(7 downto 0)
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@ -135,6 +136,7 @@ begin
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DO => DO,
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DO => DO,
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MC => MCycle,
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MC => MCycle,
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TS => TState,
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TS => TState,
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OUT0 => OUT0,
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IntCycle_n => IntCycle_n
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IntCycle_n => IntCycle_n
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);
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);
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@ -99,12 +99,13 @@ module tsconf
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output [15:0] SOUND_L,
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output [15:0] SOUND_L,
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output [15:0] SOUND_R,
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output [15:0] SOUND_R,
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// External I/O
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// Misc. I/O
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input COLD_RESET,
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input COLD_RESET,
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input WARM_RESET,
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input WARM_RESET,
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output RESET_OUT,
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output RESET_OUT,
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input [64:0] RTC,
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input [64:0] RTC,
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input [31:0] CMOSCfg,
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input [31:0] CMOSCfg,
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input OUT0,
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// PS/2 Keyboard
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// PS/2 Keyboard
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input [10:0] PS2_KEY,
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input [10:0] PS2_KEY,
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@ -340,6 +341,7 @@ T80s CPU
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.RD_n(cpu_rd_n),
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.RD_n(cpu_rd_n),
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.WR_n(cpu_wr_n),
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.WR_n(cpu_wr_n),
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.RFSH_n(cpu_rfsh_n),
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.RFSH_n(cpu_rfsh_n),
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.OUT0(OUT0),
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.A(cpu_a_bus),
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.A(cpu_a_bus),
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.DI(cpu_di_bus),
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.DI(cpu_di_bus),
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.DO(cpu_do_bus)
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.DO(cpu_do_bus)
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