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Add OUT0 signal to T80pa.

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sorgelig
2018-08-22 20:20:10 +08:00
parent 76ca22dbbc
commit d3814c856e
1 changed files with 2 additions and 0 deletions
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2
src/t80/T80pa.vhd
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@ -79,6 +79,7 @@ entity T80pa is
RFSH_n : out std_logic; RFSH_n : out std_logic;
HALT_n : out std_logic; HALT_n : out std_logic;
BUSAK_n : out std_logic; BUSAK_n : out std_logic;
OUT0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
A : out std_logic_vector(15 downto 0); A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0); DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0); DO : out std_logic_vector(7 downto 0);
@ -134,6 +135,7 @@ begin
REG => REG, REG => REG,
MC => MCycle, MC => MCycle,
TS => TState, TS => TState,
OUT0 => OUT0,
IntCycle_n => IntCycle_n IntCycle_n => IntCycle_n
); );