From d3814c856e3669d08b6d210d28fbf0afc3711557 Mon Sep 17 00:00:00 2001
From: sorgelig <pour.garbage@gmail.com>
Date: Wed, 22 Aug 2018 20:20:10 +0800
Subject: [PATCH] Add OUT0 signal to T80pa.

---
 src/t80/T80pa.vhd | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/t80/T80pa.vhd b/src/t80/T80pa.vhd
index cb3d146..bacbc60 100644
--- a/src/t80/T80pa.vhd
+++ b/src/t80/T80pa.vhd
@@ -79,6 +79,7 @@ entity T80pa is
 		RFSH_n		: out std_logic;
 		HALT_n		: out std_logic;
 		BUSAK_n		: out std_logic;
+		OUT0        : in  std_logic := '0';  -- 0 => OUT(C),0, 1 => OUT(C),255
 		A				: out std_logic_vector(15 downto 0);
 		DI				: in  std_logic_vector(7 downto 0);
 		DO				: out std_logic_vector(7 downto 0);
@@ -134,6 +135,7 @@ begin
 			REG     => REG,
 			MC      => MCycle,
 			TS      => TState,
+			OUT0    => OUT0,
 			IntCycle_n => IntCycle_n
 		);