Initial commit.

sys/ip/avalon_combiner.v

@@ -0,0 +1,60 @@
+// avalon_combiner.v
+
+`timescale 1 ps / 1 ps
+module avalon_combiner
+(
+	input  wire        clk,                //      clock.clk
+	input  wire        rst,                //      reset.reset
+
+	output wire [6:0]  mixer_address,      //  ctl_mixer.address
+	output wire [3:0]  mixer_byteenable,   //           .byteenable
+	output wire        mixer_write,        //           .write
+	output wire [31:0] mixer_writedata,    //           .writedata
+	input  wire        mixer_waitrequest,  //           .waitrequest
+
+	output wire [6:0]  scaler_address,     // ctl_scaler.address
+	output wire [3:0]  scaler_byteenable,  //           .byteenable
+	input  wire        scaler_waitrequest, //           .waitrequest
+	output wire        scaler_write,       //           .write
+	output wire [31:0] scaler_writedata,   //           .writedata
+
+	output wire [7:0]  video_address,      //  ctl_video.address
+	output wire [3:0]  video_byteenable,   //           .byteenable
+	input  wire        video_waitrequest,  //           .waitrequest
+	output wire        video_write,        //           .write
+	output wire [31:0] video_writedata,    //           .writedata
+
+	output wire        clock,              //    control.clock
+	output wire        reset,              //           .reset
+	input  wire [8:0]  address,            //           .address
+	input  wire        write,              //           .write
+	input  wire [31:0] writedata,          //           .writedata
+	output wire        waitrequest         //           .waitrequest
+);
+
+assign clock = clk;
+assign reset = rst;
+
+assign mixer_address  = address[6:0];
+assign scaler_address = address[6:0];
+assign video_address  = address[7:0];
+
+assign mixer_byteenable  = 4'b1111;
+assign scaler_byteenable = 4'b1111;
+assign video_byteenable  = 4'b1111;
+
+wire   en_scaler = (address[8:7] == 0);
+wire   en_mixer  = (address[8:7] == 1);
+wire   en_video  =  address[8];
+
+assign mixer_write  = en_mixer  & write;
+assign scaler_write = en_scaler & write;
+assign video_write  = en_video  & write;
+
+assign mixer_writedata  = writedata;
+assign scaler_writedata = writedata;
+assign video_writedata  = writedata;
+
+assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);
+
+endmodule

sys/ip/avalon_combiner_hw.tcl

@@ -0,0 +1,204 @@
+# TCL File Generated by Component Editor 17.0
+# Wed Dec 13 01:40:49 CST 2017
+# DO NOT MODIFY
+
+
+# 
+# avalon_combiner "avalon_combiner" v17.0
+# sorgelig 2017.12.13.01:40:49
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module avalon_combiner
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME avalon_combiner
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR sorgelig
+set_module_property DISPLAY_NAME avalon_combiner
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset rst reset Input 1
+
+
+# 
+# connection point ctl_mixer
+# 
+add_interface ctl_mixer avalon start
+set_interface_property ctl_mixer addressUnits WORDS
+set_interface_property ctl_mixer associatedClock clock
+set_interface_property ctl_mixer associatedReset reset
+set_interface_property ctl_mixer bitsPerSymbol 8
+set_interface_property ctl_mixer burstOnBurstBoundariesOnly false
+set_interface_property ctl_mixer burstcountUnits WORDS
+set_interface_property ctl_mixer doStreamReads false
+set_interface_property ctl_mixer doStreamWrites false
+set_interface_property ctl_mixer holdTime 0
+set_interface_property ctl_mixer linewrapBursts false
+set_interface_property ctl_mixer maximumPendingReadTransactions 0
+set_interface_property ctl_mixer maximumPendingWriteTransactions 0
+set_interface_property ctl_mixer readLatency 0
+set_interface_property ctl_mixer readWaitTime 1
+set_interface_property ctl_mixer setupTime 0
+set_interface_property ctl_mixer timingUnits Cycles
+set_interface_property ctl_mixer writeWaitTime 0
+set_interface_property ctl_mixer ENABLED true
+set_interface_property ctl_mixer EXPORT_OF ""
+set_interface_property ctl_mixer PORT_NAME_MAP ""
+set_interface_property ctl_mixer CMSIS_SVD_VARIABLES ""
+set_interface_property ctl_mixer SVD_ADDRESS_GROUP ""
+
+add_interface_port ctl_mixer mixer_address address Output 7
+add_interface_port ctl_mixer mixer_byteenable byteenable Output 4
+add_interface_port ctl_mixer mixer_write write Output 1
+add_interface_port ctl_mixer mixer_writedata writedata Output 32
+add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1
+
+
+# 
+# connection point ctl_scaler
+# 
+add_interface ctl_scaler avalon start
+set_interface_property ctl_scaler addressUnits WORDS
+set_interface_property ctl_scaler associatedClock clock
+set_interface_property ctl_scaler associatedReset reset
+set_interface_property ctl_scaler bitsPerSymbol 8
+set_interface_property ctl_scaler burstOnBurstBoundariesOnly false
+set_interface_property ctl_scaler burstcountUnits WORDS
+set_interface_property ctl_scaler doStreamReads false
+set_interface_property ctl_scaler doStreamWrites false
+set_interface_property ctl_scaler holdTime 0
+set_interface_property ctl_scaler linewrapBursts false
+set_interface_property ctl_scaler maximumPendingReadTransactions 0
+set_interface_property ctl_scaler maximumPendingWriteTransactions 0
+set_interface_property ctl_scaler readLatency 0
+set_interface_property ctl_scaler readWaitTime 1
+set_interface_property ctl_scaler setupTime 0
+set_interface_property ctl_scaler timingUnits Cycles
+set_interface_property ctl_scaler writeWaitTime 0
+set_interface_property ctl_scaler ENABLED true
+set_interface_property ctl_scaler EXPORT_OF ""
+set_interface_property ctl_scaler PORT_NAME_MAP ""
+set_interface_property ctl_scaler CMSIS_SVD_VARIABLES ""
+set_interface_property ctl_scaler SVD_ADDRESS_GROUP ""
+
+add_interface_port ctl_scaler scaler_address address Output 7
+add_interface_port ctl_scaler scaler_byteenable byteenable Output 4
+add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1
+add_interface_port ctl_scaler scaler_write write Output 1
+add_interface_port ctl_scaler scaler_writedata writedata Output 32
+
+
+# 
+# connection point ctl_video
+# 
+add_interface ctl_video avalon start
+set_interface_property ctl_video addressUnits WORDS
+set_interface_property ctl_video associatedClock clock
+set_interface_property ctl_video associatedReset reset
+set_interface_property ctl_video bitsPerSymbol 8
+set_interface_property ctl_video burstOnBurstBoundariesOnly false
+set_interface_property ctl_video burstcountUnits WORDS
+set_interface_property ctl_video doStreamReads false
+set_interface_property ctl_video doStreamWrites false
+set_interface_property ctl_video holdTime 0
+set_interface_property ctl_video linewrapBursts false
+set_interface_property ctl_video maximumPendingReadTransactions 0
+set_interface_property ctl_video maximumPendingWriteTransactions 0
+set_interface_property ctl_video readLatency 0
+set_interface_property ctl_video readWaitTime 1
+set_interface_property ctl_video setupTime 0
+set_interface_property ctl_video timingUnits Cycles
+set_interface_property ctl_video writeWaitTime 0
+set_interface_property ctl_video ENABLED true
+set_interface_property ctl_video EXPORT_OF ""
+set_interface_property ctl_video PORT_NAME_MAP ""
+set_interface_property ctl_video CMSIS_SVD_VARIABLES ""
+set_interface_property ctl_video SVD_ADDRESS_GROUP ""
+
+add_interface_port ctl_video video_address address Output 8
+add_interface_port ctl_video video_byteenable byteenable Output 4
+add_interface_port ctl_video video_waitrequest waitrequest Input 1
+add_interface_port ctl_video video_write write Output 1
+add_interface_port ctl_video video_writedata writedata Output 32
+
+
+# 
+# connection point control
+# 
+add_interface control conduit end
+set_interface_property control associatedClock clock
+set_interface_property control associatedReset reset
+set_interface_property control ENABLED true
+set_interface_property control EXPORT_OF ""
+set_interface_property control PORT_NAME_MAP ""
+set_interface_property control CMSIS_SVD_VARIABLES ""
+set_interface_property control SVD_ADDRESS_GROUP ""
+
+add_interface_port control address address Input 9
+add_interface_port control write write Input 1
+add_interface_port control writedata writedata Input 32
+add_interface_port control waitrequest waitrequest Output 1
+add_interface_port control clock clock Output 1
+add_interface_port control reset reset Output 1
+

sys/ip/in_split.v

@@ -0,0 +1,52 @@
+// in_split.v
+
+
+`timescale 1 ps / 1 ps
+module in_split (
+		input  wire        clk,                //  input.clk
+		input  wire        ce,                 //       .ce
+		input  wire        de,                 //       .de
+		input  wire        h_sync,             //       .h_sync
+		input  wire        v_sync,             //       .v_sync
+		input  wire        f,                  //       .f
+		input  wire [23:0] data,               //       .data
+		output wire        vid_clk,            // Output.vid_clk
+		output reg         vid_datavalid,      //       .vid_datavalid
+		output reg  [1:0]  vid_de,             //       .vid_de
+		output reg  [1:0]  vid_f,              //       .vid_f
+		output reg  [1:0]  vid_h_sync,         //       .vid_h_sync
+		output reg  [1:0]  vid_v_sync,         //       .vid_v_sync
+		output reg  [47:0] vid_data,           //       .vid_data
+		output wire        vid_locked,         //       .vid_locked
+		output wire [7:0]  vid_color_encoding, //       .vid_color_encoding
+		output wire [7:0]  vid_bit_width,      //       .vid_bit_width
+		input  wire        clipping,           //       .clipping
+		input  wire        overflow,           //       .overflow
+		input  wire        sof,                //       .sof
+		input  wire        sof_locked,         //       .sof_locked
+		input  wire        refclk_div,         //       .refclk_div
+		input  wire        padding             //       .padding
+	);
+
+	assign vid_bit_width = 0;
+	assign vid_color_encoding = 0;
+	assign vid_locked = 1;
+	assign vid_clk = clk;
+
+	always @(posedge clk) begin
+		reg odd = 0;
+		
+		vid_datavalid <= 0;
+		if(ce) begin
+			vid_de[odd] <= de;
+			vid_f[odd] <= f;
+			vid_h_sync[odd] <= h_sync;
+			vid_v_sync[odd] <= v_sync;
+			if(odd) vid_data[47:24] <= data;
+				else vid_data[23:0] <= data;
+			
+			odd <= ~odd;
+			vid_datavalid <= odd;
+		end
+	end
+endmodule

sys/ip/in_split_hw.tcl

@@ -0,0 +1,104 @@
+# TCL File Generated by Component Editor 17.0
+# Thu Jan 25 18:50:29 CST 2018
+# DO NOT MODIFY
+
+
+# 
+# in_split "Input Splitter" v17.0
+# Sorgelig 2018.01.25.18:50:29
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module in_split
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME in_split
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR Sorgelig
+set_module_property DISPLAY_NAME "Input Splitter"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point input
+# 
+add_interface input conduit end
+set_interface_property input associatedClock ""
+set_interface_property input associatedReset ""
+set_interface_property input ENABLED true
+set_interface_property input EXPORT_OF ""
+set_interface_property input PORT_NAME_MAP ""
+set_interface_property input CMSIS_SVD_VARIABLES ""
+set_interface_property input SVD_ADDRESS_GROUP ""
+
+add_interface_port input clk clk Input 1
+add_interface_port input ce ce Input 1
+add_interface_port input de de Input 1
+add_interface_port input h_sync h_sync Input 1
+add_interface_port input v_sync v_sync Input 1
+add_interface_port input f f Input 1
+add_interface_port input data data Input 24
+
+
+# 
+# connection point Output
+# 
+add_interface Output conduit end
+set_interface_property Output associatedClock ""
+set_interface_property Output associatedReset ""
+set_interface_property Output ENABLED true
+set_interface_property Output EXPORT_OF ""
+set_interface_property Output PORT_NAME_MAP ""
+set_interface_property Output CMSIS_SVD_VARIABLES ""
+set_interface_property Output SVD_ADDRESS_GROUP ""
+
+add_interface_port Output vid_clk vid_clk Output 1
+add_interface_port Output vid_datavalid vid_datavalid Output 1
+add_interface_port Output vid_de vid_de Output 2
+add_interface_port Output vid_f vid_f Output 2
+add_interface_port Output vid_h_sync vid_h_sync Output 2
+add_interface_port Output vid_v_sync vid_v_sync Output 2
+add_interface_port Output vid_data vid_data Output 48
+add_interface_port Output vid_locked vid_locked Output 1
+add_interface_port Output vid_color_encoding vid_color_encoding Output 8
+add_interface_port Output vid_bit_width vid_bit_width Output 8
+add_interface_port Output clipping clipping Input 1
+add_interface_port Output overflow overflow Input 1
+add_interface_port Output sof sof Input 1
+add_interface_port Output sof_locked sof_locked Input 1
+add_interface_port Output refclk_div refclk_div Input 1
+add_interface_port Output padding padding Input 1
+

sys/ip/out_mix.v

@@ -0,0 +1,44 @@
+// out_mix.v
+
+`timescale 1 ps / 1 ps
+module out_mix (
+		input  wire        clk,             // Output.clk
+		output reg         de,              //       .de
+		output reg         h_sync,          //       .h_sync
+		output reg         v_sync,          //       .v_sync
+		output reg  [23:0] data,            //       .data
+		output reg         vid_clk,         //  input.vid_clk
+		input  wire [1:0]  vid_datavalid,   //       .vid_datavalid
+		input  wire [1:0]  vid_h_sync,      //       .vid_h_sync
+		input  wire [1:0]  vid_v_sync,      //       .vid_v_sync
+		input  wire [47:0] vid_data,        //       .vid_data
+		input  wire        underflow,       //       .underflow
+		input  wire        vid_mode_change, //       .vid_mode_change
+		input  wire [1:0]  vid_std,         //       .vid_std
+		input  wire [1:0]  vid_f,           //       .vid_f
+		input  wire [1:0]  vid_h,           //       .vid_h
+		input  wire [1:0]  vid_v            //       .vid_v
+	);
+
+	reg        r_de;
+	reg        r_h_sync;
+	reg        r_v_sync;
+	reg [23:0] r_data;
+	
+	always @(posedge clk) begin
+		vid_clk <= ~vid_clk;
+		
+		if(~vid_clk) begin
+			{r_de,de} <= vid_datavalid;
+			{r_h_sync, h_sync} <= vid_h_sync;
+			{r_v_sync, v_sync} <= vid_v_sync;
+			{r_data, data} <= vid_data;
+		end else begin
+			de <= r_de;
+			h_sync <= r_h_sync;
+			v_sync <= r_v_sync;
+			data <= r_data;
+		end
+	end
+
+endmodule

sys/ip/out_mix_hw.tcl

@@ -0,0 +1,97 @@
+# TCL File Generated by Component Editor 17.0
+# Thu Jan 25 06:51:26 CST 2018
+# DO NOT MODIFY
+
+
+# 
+# out_mix "Output Mixer" v1.0
+# Sorgelig 2018.01.25.06:51:26
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module out_mix
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME out_mix
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR Sorgelig
+set_module_property DISPLAY_NAME "Output Mixer"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point Output
+# 
+add_interface Output conduit end
+set_interface_property Output associatedClock ""
+set_interface_property Output associatedReset ""
+set_interface_property Output ENABLED true
+set_interface_property Output EXPORT_OF ""
+set_interface_property Output PORT_NAME_MAP ""
+set_interface_property Output CMSIS_SVD_VARIABLES ""
+set_interface_property Output SVD_ADDRESS_GROUP ""
+
+add_interface_port Output clk clk Input 1
+add_interface_port Output de de Output 1
+add_interface_port Output h_sync h_sync Output 1
+add_interface_port Output v_sync v_sync Output 1
+add_interface_port Output data data Output 24
+
+
+# 
+# connection point input
+# 
+add_interface input conduit end
+set_interface_property input associatedClock ""
+set_interface_property input associatedReset ""
+set_interface_property input ENABLED true
+set_interface_property input EXPORT_OF ""
+set_interface_property input PORT_NAME_MAP ""
+set_interface_property input CMSIS_SVD_VARIABLES ""
+set_interface_property input SVD_ADDRESS_GROUP ""
+
+add_interface_port input vid_clk vid_clk Output 1
+add_interface_port input vid_datavalid vid_datavalid Input 2
+add_interface_port input vid_h_sync vid_h_sync Input 2
+add_interface_port input vid_v_sync vid_v_sync Input 2
+add_interface_port input vid_data vid_data Input 48
+add_interface_port input underflow underflow Input 1
+add_interface_port input vid_mode_change vid_mode_change Input 1
+add_interface_port input vid_std vid_std Input 2
+add_interface_port input vid_f vid_f Input 2
+add_interface_port input vid_h vid_h Input 2
+add_interface_port input vid_v vid_v Input 2
+

sys/ip/reset_source.v

@@ -0,0 +1,50 @@
+// reset_source.v
+
+// This file was auto-generated as a prototype implementation of a module
+// created in component editor.  It ties off all outputs to ground and
+// ignores all inputs.  It needs to be edited to make it do something
+// useful.
+// 
+// This file will not be automatically regenerated.  You should check it in
+// to your version control system if you want to keep it.
+
+`timescale 1 ps / 1 ps
+module reset_source
+(
+	input  wire  clk,        //      clock.clk
+	input  wire  reset_hps,  //  reset_hps.reset
+	output wire  reset_sys,  //  reset_sys.reset
+	output wire  reset_cold, // reset_cold.reset
+	input  wire  cold_req,   //  reset_ctl.cold_req
+	output wire  reset,      //           .reset
+	input  wire  reset_req,  //           .reset_req
+	input  wire  reset_vip,  //           .reset_vip
+	input  wire  warm_req,   //           .warm_req
+	output wire  reset_warm  // reset_warm.reset
+);
+
+assign reset_cold = cold_req;
+assign reset_warm = warm_req;
+
+wire   reset_m    = sys_reset | reset_hps | reset_req;
+assign reset      = reset_m;
+assign reset_sys  = reset_m | reset_vip;
+
+reg  sys_reset = 1;
+always @(posedge clk) begin
+	integer timeout = 0;
+	reg reset_lock = 0;
+
+	reset_lock <= reset_lock | cold_req;
+
+	if(timeout < 2000000) begin
+		sys_reset <= 1;
+		timeout <= timeout + 1;
+		reset_lock <= 0;
+	end
+	else begin 
+		sys_reset <= reset_lock;
+	end
+end
+
+endmodule

sys/ip/reset_source_hw.tcl

@@ -0,0 +1,152 @@
+# TCL File Generated by Component Editor 17.0
+# Tue Feb 20 07:55:55 CST 2018
+# DO NOT MODIFY
+
+
+# 
+# reset_source "reset_source" v17.0
+# Sorgelig 2018.02.20.07:55:55
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module reset_source
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME reset_source
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR Sorgelig
+set_module_property DISPLAY_NAME reset_source
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset_hps
+# 
+add_interface reset_hps reset end
+set_interface_property reset_hps associatedClock ""
+set_interface_property reset_hps synchronousEdges NONE
+set_interface_property reset_hps ENABLED true
+set_interface_property reset_hps EXPORT_OF ""
+set_interface_property reset_hps PORT_NAME_MAP ""
+set_interface_property reset_hps CMSIS_SVD_VARIABLES ""
+set_interface_property reset_hps SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_hps reset_hps reset Input 1
+
+
+# 
+# connection point reset_sys
+# 
+add_interface reset_sys reset start
+set_interface_property reset_sys associatedClock ""
+set_interface_property reset_sys associatedDirectReset ""
+set_interface_property reset_sys associatedResetSinks ""
+set_interface_property reset_sys synchronousEdges NONE
+set_interface_property reset_sys ENABLED true
+set_interface_property reset_sys EXPORT_OF ""
+set_interface_property reset_sys PORT_NAME_MAP ""
+set_interface_property reset_sys CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sys SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sys reset_sys reset Output 1
+
+
+# 
+# connection point reset_ctl
+# 
+add_interface reset_ctl conduit end
+set_interface_property reset_ctl associatedClock ""
+set_interface_property reset_ctl associatedReset ""
+set_interface_property reset_ctl ENABLED true
+set_interface_property reset_ctl EXPORT_OF ""
+set_interface_property reset_ctl PORT_NAME_MAP ""
+set_interface_property reset_ctl CMSIS_SVD_VARIABLES ""
+set_interface_property reset_ctl SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_ctl cold_req cold_req Input 1
+add_interface_port reset_ctl reset reset Output 1
+add_interface_port reset_ctl reset_req reset_req Input 1
+add_interface_port reset_ctl warm_req warm_req Input 1
+add_interface_port reset_ctl reset_vip reset_vip Input 1
+
+
+# 
+# connection point reset_warm
+# 
+add_interface reset_warm reset start
+set_interface_property reset_warm associatedClock ""
+set_interface_property reset_warm associatedDirectReset ""
+set_interface_property reset_warm associatedResetSinks ""
+set_interface_property reset_warm synchronousEdges NONE
+set_interface_property reset_warm ENABLED true
+set_interface_property reset_warm EXPORT_OF ""
+set_interface_property reset_warm PORT_NAME_MAP ""
+set_interface_property reset_warm CMSIS_SVD_VARIABLES ""
+set_interface_property reset_warm SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_warm reset_warm reset Output 1
+
+
+# 
+# connection point reset_cold
+# 
+add_interface reset_cold reset start
+set_interface_property reset_cold associatedClock ""
+set_interface_property reset_cold associatedDirectReset ""
+set_interface_property reset_cold associatedResetSinks ""
+set_interface_property reset_cold synchronousEdges NONE
+set_interface_property reset_cold ENABLED true
+set_interface_property reset_cold EXPORT_OF ""
+set_interface_property reset_cold PORT_NAME_MAP ""
+set_interface_property reset_cold CMSIS_SVD_VARIABLES ""
+set_interface_property reset_cold SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_cold reset_cold reset Output 1
+