mirror of
https://github.com/UzixLS/TSConf_MiST.git
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a1d17ed38add8056339b0910eb6193ecad0970c1
Description
TSConf for MiST FPGA (forked from https://github.com/MiSTer-devel/TSConf_MiSTer.git)
26 MiB
Languages
Verilog
66.4%
VHDL
28.9%
SystemVerilog
4%
Tcl
0.6%
Batchfile
0.1%