2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
2018-08-16 05:21:32 +08:00
Description
TSConf for MiST FPGA (forked from https://github.com/MiSTer-devel/TSConf_MiSTer.git)
26 MiB
Languages
Verilog 66.4%
VHDL 28.9%
SystemVerilog 4%
Tcl 0.6%
Batchfile 0.1%