uzix/TSConf_MiST
1
0
Fork 0
mirror of https://github.com/UzixLS/TSConf_MiST.git synced 2025-07-18 23:01:37 +03:00
Code Issues Packages Projects Releases Wiki Activity

add gs support

Browse Source
This commit is contained in:
Eugene Lozovoy
2024-09-14 16:41:57 +03:00
parent 53d662a574
commit 66bfce85d5
12 changed files with 415 additions and 1580 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
rtl/dram/arbiter.v
View File

@ -58,7 +58,7 @@ module arbiter
input wire cyc,
// dram.v interface
output wire [21:0] dram_addr, // address for dram access
output wire [22:0] dram_addr, // address for dram access
output wire dram_req, // dram request
output wire dram_rnw, // Read-NotWrite
output wire [ 1:0] dram_bsel, // byte select: bsel[1] for wrdata[15:8], bsel[0] for wrdata[7:0]
@ -108,7 +108,9 @@ module arbiter
input wire loader_clk,
input wire [15:0] loader_addr,
input wire [7:0] loader_data,
input wire loader_wr
input wire loader_wr,
input wire loader_cs_rom_main,
input wire loader_cs_rom_gs
);
localparam CYCLES = 6;
@ -182,10 +184,12 @@ module arbiter
reg loader_wr0;
reg [7:0] loader_data0;
reg [1:0] loader_hiaddr;
always @(posedge loader_clk) begin
if (loader_wr) begin
if (loader_wr && (loader_cs_rom_main || loader_cs_rom_gs)) begin
loader_wr0 <= 1'd1;
loader_data0 <= loader_data;
loader_hiaddr <= { loader_cs_rom_gs, loader_cs_rom_main };
end
else if (cyc) begin
loader_wr0 <= 1'd0;
@ -230,12 +234,12 @@ module arbiter
assign dram_bsel[1:0] = next_loader? {loader_addr[0], ~loader_addr[0]} : next_dma ? 2'b11 : {cpu_wrbsel, ~cpu_wrbsel};
assign dram_req = |next_cycle;
assign dram_rnw = next_loader? 1'b0 : next_cpu ? cpu_rnw : (next_dma ? dma_rnw : 1'b1);
assign dram_addr = {22{next_loader}} & { 1'b1, 6'b000000, loader_addr[15:1] }
| {22{next_cpu}} & { cpu_csrom, {6{~cpu_csrom}} & cpu_addr[20:15], cpu_addr[14:0] }
| {22{next_vid}} & { 1'b0, video_addr }
| {22{next_ts}} & { 1'b0, ts_addr }
| {22{next_tm}} & { 1'b0, tm_addr }
| {22{next_dma}} & { 1'b0, dma_addr };
assign dram_addr = {23{next_loader}} & { loader_hiaddr, 6'b000000, loader_addr[15:1] }
| {23{next_cpu}} & { 1'b0, cpu_csrom, {6{~cpu_csrom}} & cpu_addr[20:15], cpu_addr[14:0] }
| {23{next_vid}} & { 2'b0, video_addr }
| {23{next_ts}} & { 2'b0, ts_addr }
| {23{next_tm}} & { 2'b0, tm_addr }
| {23{next_dma}} & { 2'b0, dma_addr };
reg cpu_rnw_r;
always @(posedge clk) if (c3)

304
rtl/dram/sdram.v
View File

@ -1,46 +1,71 @@
// READ 25 26 27 21 22 23 24
// RAS CAS read
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// T0 T1 T2 T3 T4 T5 T6
// 5.95ns ACT READ DQDQDQDQD
// tAC=6 tOH=3
// 25 26 27 28 29 30 31 20 21 22 23 24 25
// cpu_strobe ________________________________________________________________/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\_______________________________________________________________
// cyc ‾‾‾‾\_____________________________________________________________________________________________________________/‾‾‾‾‾‾‾‾‾\____
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// 5.95ns
//
// WRITE 25 26 27 22 23 24
// RAS CASWEDQ
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// T0 T1 T2 T3 T4 T5
// 5.95ns ACT WRITE
// REFRESH RASCAS
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// REFRSH
//
// READ+NOP RAS CAS latch set do
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// ACT READ DQDQDQDQD
//
// WRITE+NOP RAS CASWEDQ
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// ACT WRITE
//
// NOP+READ RAS CAS latch set do
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// ACT READ DQDQDQDQD
//
// NOP+WRITE RAS CASWEDQ
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// ACT WRITE
//
module sdram
(
// Memory port
input clk,
input cyc,
input clk,
input cyc,
input curr_cpu,
input [1:0] bsel, // Active HI
input [23:0] A,
input [15:0] DI,
output reg [15:0] DO,
output reg [15:0] DO_cpu,
input REQ,
input RNW,
// Memory port 1
input port1_curr_cpu,
input [1:0] port1_bsel,
input [23:0] port1_a,
input [15:0] port1_di,
output reg [15:0] port1_do,
output reg [15:0] port1_do_cpu,
input port1_req,
input port1_rnw,
// SDRAM Pin
inout reg [15:0] SDRAM_DQ,
output reg [12:0] SDRAM_A,
output reg [1:0] SDRAM_BA,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
output SDRAM_CKE,
output SDRAM_CLK
// Memory port 2
input [1:0] port2_bsel,
input [23:0] port2_a,
input [15:0] port2_di,
output reg [15:0] port2_do,
input port2_req,
input port2_rnw,
output reg port2_ack = 0,
// SDRAM Pin
inout reg [15:0] SDRAM_DQ,
output reg [12:0] SDRAM_A = 0,
output reg [1:0] SDRAM_BA = 0,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
output SDRAM_CKE,
output SDRAM_CLK
);
reg [2:0] sdr_cmd;
@ -48,88 +73,127 @@ reg [2:0] sdr_cmd;
localparam SdrCmd_xx = 3'b111; // no operation
localparam SdrCmd_ac = 3'b011; // activate
localparam SdrCmd_rd = 3'b101; // read
localparam SdrCmd_wr = 3'b100; // write
localparam SdrCmd_wr = 3'b100; // write
localparam SdrCmd_pr = 3'b010; // precharge all
localparam SdrCmd_re = 3'b001; // refresh
localparam SdrCmd_ms = 3'b000; // mode regiser set
reg [5:0] state = 0;
reg [15:0] data;
reg [8:0] col;
reg [23:0] Ar1, Ar2;
reg [1:0] dqm1, dqm2;
reg rq1, rq2;
reg rd1, rd2 = 0;
always @(posedge clk) begin
reg [4:0] state;
reg rd;
reg [8:0] col;
reg [1:0] dqm;
reg [15:0] data;
reg [23:0] Ar;
reg rq;
sdr_cmd <= SdrCmd_xx;
data <= SDRAM_DQ;
SDRAM_DQ <= 16'bZ;
state <= state + 1'd1;
port2_ack <= 1'b0;
sdr_cmd <= SdrCmd_xx;
data <= SDRAM_DQ;
SDRAM_DQ <= 16'bZ;
state <= state + 1'd1;
case (state)
case (state)
// Init
0: begin
sdr_cmd <= SdrCmd_pr; // PRECHARGE
end
// Init
0: begin
sdr_cmd <= SdrCmd_pr; // PRECHARGE
SDRAM_A <= 0;
SDRAM_BA <= 0;
end
// REFRESH
3,10: begin
sdr_cmd <= SdrCmd_re;
end
// REFRESH
3,10: begin
sdr_cmd <= SdrCmd_re;
end
// LOAD MODE REGISTER
17: begin
sdr_cmd <= SdrCmd_ms;
SDRAM_A <= {3'b000, 1'b1, 2'b00, 3'b010, 1'b0, 3'b000};
end
// LOAD MODE REGISTER
17: begin
sdr_cmd <= SdrCmd_ms;
SDRAM_A <= {3'b000, 1'b1, 2'b00, 3'b010, 1'b0, 3'b000};
end
// Idle
24: begin
state <= state;
Ar1 <= port1_a;
Ar2 <= port2_a;
dqm1 <= port1_rnw ? 2'b00 : ~port1_bsel;
dqm2 <= port2_rnw ? 2'b00 : ~port2_bsel;
rq1 <= port1_req;
rd1 <= port1_req & port1_rnw;
rq2 <= port2_req;
rd2 <= port2_req & port2_rnw;
if (cyc)
state <= state + 1'd1;
end
// Idle
24: begin
if (rd) begin
DO <= data;
if (curr_cpu) DO_cpu <= data;
end
// Start - activate (port1) or refresh
25: begin
if (rq1) begin
{SDRAM_BA,SDRAM_A,col} <= Ar1;
sdr_cmd <= SdrCmd_ac;
end
else if (rq2) begin
// start at state 28
end
else begin
sdr_cmd <= SdrCmd_re;
state <= 19;
end
end
state <= state;
Ar <= A;
dqm <= RNW ? 2'b00 : ~bsel;
rd <= 0;
// Single read/write (port1) - with auto precharge
27: begin
SDRAM_A <= {dqm1, 2'b1x, col};
if (rq1) begin
if (rd1) begin
sdr_cmd <= SdrCmd_rd;
end
else begin
sdr_cmd <= SdrCmd_wr;
SDRAM_DQ <= port1_di;
end
end
end
if(cyc) begin
rq <= REQ;
rd <= REQ & RNW;
state <= state + 1'd1;
end
end
// Start - activate (port2) or refresh
28: begin
if (rq2) begin
{SDRAM_BA,SDRAM_A,col} <= Ar2;
sdr_cmd <= SdrCmd_ac;
end
end
// Start
25: begin
if (rq) begin
{SDRAM_A,SDRAM_BA,col} <= Ar;
sdr_cmd <= SdrCmd_ac;
end else begin
sdr_cmd <= SdrCmd_re;
state <= 19;
end
end
// Latch read (port 1) and Single read/write (port2) - with auto precharge
31: begin
if (rd1) begin
port1_do <= data;
if (port1_curr_cpu) port1_do_cpu <= data;
end
// Single read/write - with auto precharge
27: begin
SDRAM_A <= {dqm, 2'b10, col};
state <= 21;
if (rd) sdr_cmd <= SdrCmd_rd;
else begin
sdr_cmd <= SdrCmd_wr;
SDRAM_DQ <= DI;
state <= 22;
end
end
SDRAM_A <= {dqm2, 2'b1x, col};
if (rq2) begin
if (rd2) begin
sdr_cmd <= SdrCmd_rd;
end
else begin
sdr_cmd <= SdrCmd_wr;
SDRAM_DQ <= port2_di;
port2_ack <= 1'b1;
end
end
endcase
state <= 20;
end
// Latch read (port 2)
23: begin
if (rd2) begin
port2_do <= data;
port2_ack <= 1'b1;
end
end
endcase
end
assign SDRAM_CKE = 1;
@ -142,27 +206,27 @@ assign SDRAM_DQMH = SDRAM_A[12];
altddio_out
#(
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone III"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1)
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone III"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1)
)
sdramclk_ddr
(
.datain_h(1'b0),
.datain_l(1'b1),
.outclock(clk),
.dataout(SDRAM_CLK),
.aclr(1'b0),
.aset(1'b0),
.oe(1'b1),
.outclocken(1'b1),
.sclr(1'b0),
.sset(1'b0)
.datain_h(1'b0),
.datain_l(1'b1),
.outclock(clk),
.dataout(SDRAM_CLK),
.aclr(1'b0),
.aset(1'b0),
.oe(1'b1),
.outclocken(1'b1),
.sclr(1'b0),
.sset(1'b0)
);
endmodule