uzix/TSConf_MiST
1
0
Fork 0
mirror of https://github.com/UzixLS/TSConf_MiST.git synced 2025-07-18 14:51:25 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix trdos entering

Browse Source
This commit is contained in:
Eugene Lozovoy
2024-09-13 15:20:03 +03:00
parent 64b6ab3cdb
commit 53d662a574
2 changed files with 40 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
rtl/z80/trdos504T_3DXX.mif Normal file
View File

@ -0,0 +1,21 @@
-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec_cat -o --mif
--
DEPTH = 256;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 18 2E 00 18 14 00 C3 EF 25 C3 4A 24 00 18 FA 00 18 E7 00 18 E7 00 C3;
0018: 69 2F CD 21 3D E5 C3 6C 01 CD F3 31 00 00 DC 4C 3D 21 C2 5C C9 00 00 00;
0030: C9 CD 21 3D E5 C3 39 02 AF D3 F7 DB F7 FE 1E 28 03 FE 1F C0 CF 31 3E 01;
0048: 32 EF 5C C9 AF D3 FF DB F6 21 38 3D 11 92 5C 01 14 00 ED B0 21 67 3D E5;
0060: 21 2F 3D E5 C3 92 5C 21 90 2F E5 21 2F 3D E5 21 55 16 E5 21 FF 5B E5 36;
0078: C9 21 B5 5C 01 70 00 C9 3E 0D E5 C5 D5 F5 CD F1 20 F1 CD 94 3D CD F1 20;
0090: D1 C1 E1 C9 E7 10 00 C9 3E 08 D3 1F E5 E7 54 1F 38 03 E7 7B 1B E1 DB FF;
00A8: E6 80 28 F0 C9 3E 08 CD 9A 3D 11 00 00 DB 1F E6 02 47 DB 1F E6 02 B8 C0;
00C0: 13 7B B2 20 F5 C3 E7 3E 3A 19 5D 32 F6 5C 21 16 5D 4F 3E 3C B1 D3 FF 77;
00D8: CD 08 3E E6 80 28 1B CD AD 3D CD 16 3E CD 11 3E FE FF 28 0E E5 CD CA 1F;
00F0: E1 FE 50 3E 00 20 02 3E 80 77 CD 36 1E 3E 50 0E;
END;

24
rtl/z80/zmem.v
View File

@ -86,7 +86,7 @@ module zmem
assign dos_on = win0 && opfetch_s && (za[13:8]==6'h3D) && rom128 && !w0_map_n;
assign dos_off = !win0 && opfetch_s && !vdos;
assign dos = (dos_on || dos_off) ^^ dos_r; // to make dos appear 1 clock earlier than dos_r
assign dos = dos_on ? 1'b1 : (dos_off ? 1'b0 : dos_r); // to make dos appear 1 clock earlier than dos_r
always @(posedge clk)
if (rst)
@ -127,7 +127,7 @@ module zmem
assign cpu_wrbsel = za[0];
assign cpu_addr[20:0] = {page, za[13:1]};
wire [15:0] mem_d = cpu_latch ? cpu_rddata : cache_d;
assign zd_out = ~cpu_wrbsel ? mem_d[7:0] : mem_d[15:8];
assign zd_out = trdos_3dxx_hit ? trdos_3dxx_do : ~cpu_wrbsel ? mem_d[7:0] : mem_d[15:8];
// Z80 controls
@ -207,8 +207,8 @@ module zmem
stall14_fin <= 1'b1;
// cache
wire [12:0] cache_a;
wire [12:0] cpu_hi_addr = {page[7:0], za[13:9]};
wire [13:0] cache_a;
wire [13:0] cpu_hi_addr = {rom_n_ram, page[7:0], za[13:9]};
// wire cache_hit = (ch_addr[7:2] != 6'b011100) && (cpu_hi_addr == cache_a) && cache_v; // debug for BM
wire cache_hit = (cpu_hi_addr == cache_a) && cache_v; // asynchronous signal meaning that address requested by CPU is cached and valid
assign cache_hit_en = cache_hit && cache_en[win];
@ -229,7 +229,7 @@ module zmem
.q_b(cache_d)
);
dpram #(.DATAWIDTH(14), .ADDRWIDTH(8)) cache_addr
dpram #(.DATAWIDTH(15), .ADDRWIDTH(8)) cache_addr
(
.clock(clk),
.address_a(ch_addr),
@ -318,4 +318,18 @@ module zmem
assign romwe_n = !(memwr && w0_we);
assign rompg = xtpage[0][4:0];
// XXX ugly workarround
// There are SDRAM latency-related issues with fetching opcode from correct page when entering DOS
// With current HDL design ROM page number isn't valid at moment of cpu_req asserting
// That is, there is a chance that SDRAM controller will start read cycle with an incorrect address
wire [7:0] trdos_3dxx_do;
wire trdos_3dxx_hit = dos && csrom && rompg==5'h1 && za[13:8]==6'h3D;
dpram #(.DATAWIDTH(8), .ADDRWIDTH(8), .MEM_INIT_FILE("rtl/z80/trdos504T_3DXX.mif")) trdos_3dxx
(
.clock (clk),
.address_a (za[7:0]),
.q_a (trdos_3dxx_do)
);
endmodule