uzix/TSConf_MiST
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add gs support

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This commit is contained in:
Eugene Lozovoy
2024-09-14 16:41:57 +03:00
parent 53d662a574
commit 66bfce85d5
12 changed files with 415 additions and 1580 deletions
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4
TSConf.sdc
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@ -43,5 +43,5 @@ set_multicycle_path -to {tsconf|CPU|*} -hold 1
set_multicycle_path -to {tsconf|saa1099|*} -setup 2
set_multicycle_path -to {tsconf|saa1099|*} -hold 1
set_multicycle_path -to {tsconf|gs|*} -setup 2
set_multicycle_path -to {tsconf|gs|*} -hold 1
set_multicycle_path -to {tsconf|gs_top|gs|CPU|*} -setup 2
set_multicycle_path -to {tsconf|gs_top|gs|CPU|*} -hold 1

6
TSConf.sv
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@ -342,8 +342,10 @@ tsconf tsconf
.loader_addr(ioctl_addr[15:0]),
.loader_do(ioctl_dout),
.loader_di(ioctl_din),
.loader_wr_rom(ioctl_wr && ioctl_download && !ioctl_index && !ioctl_addr[24:16]),
.loader_wr_cmos(ioctl_wr && ioctl_download && ioctl_index == 6'h3f)
.loader_wr(ioctl_wr),
.loader_cs_rom_main(ioctl_index == 6'h0),
.loader_cs_rom_gs(ioctl_index == 6'h1),
.loader_cs_cmos(ioctl_index == 6'h3f)
);

1
files.qip
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@ -15,6 +15,7 @@ set_global_assignment -name QIP_FILE rtl/sound/jt12/jt03.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/turbosound.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/saa1099.sv
set_global_assignment -name VERILOG_FILE rtl/sound/gs.v
set_global_assignment -name VERILOG_FILE rtl/sound/gs_top.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sound/compressor.sv
set_global_assignment -name VERILOG_FILE rtl/video/video_ts_render.v
set_global_assignment -name VERILOG_FILE rtl/video/video_ts.v

2
roms/README.txt Normal file
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@ -0,0 +1,2 @@
tsconf.rom - TSConf main BIOS - https://github.com/tslabs/zx-evo/blob/83afbba6f5d366f96297028aa3d64512fa254a51/pentevo/rom/bin/ts-bios.rom
tsconf.r01 - General Sound ROM v1.05a

BIN
roms/tsconf.r01 Normal file
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Binary file not shown.

0
rtl/tsconf.rom → roms/tsconf.rom
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22
rtl/dram/arbiter.v
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@ -58,7 +58,7 @@ module arbiter
input wire cyc,
// dram.v interface
output wire [21:0] dram_addr, // address for dram access
output wire [22:0] dram_addr, // address for dram access
output wire dram_req, // dram request
output wire dram_rnw, // Read-NotWrite
output wire [ 1:0] dram_bsel, // byte select: bsel[1] for wrdata[15:8], bsel[0] for wrdata[7:0]
@ -108,7 +108,9 @@ module arbiter
input wire loader_clk,
input wire [15:0] loader_addr,
input wire [7:0] loader_data,
input wire loader_wr
input wire loader_wr,
input wire loader_cs_rom_main,
input wire loader_cs_rom_gs
);
localparam CYCLES = 6;
@ -182,10 +184,12 @@ module arbiter
reg loader_wr0;
reg [7:0] loader_data0;
reg [1:0] loader_hiaddr;
always @(posedge loader_clk) begin
if (loader_wr) begin
if (loader_wr && (loader_cs_rom_main || loader_cs_rom_gs)) begin
loader_wr0 <= 1'd1;
loader_data0 <= loader_data;
loader_hiaddr <= { loader_cs_rom_gs, loader_cs_rom_main };
end
else if (cyc) begin
loader_wr0 <= 1'd0;
@ -230,12 +234,12 @@ module arbiter
assign dram_bsel[1:0] = next_loader? {loader_addr[0], ~loader_addr[0]} : next_dma ? 2'b11 : {cpu_wrbsel, ~cpu_wrbsel};
assign dram_req = |next_cycle;
assign dram_rnw = next_loader? 1'b0 : next_cpu ? cpu_rnw : (next_dma ? dma_rnw : 1'b1);
assign dram_addr = {22{next_loader}} & { 1'b1, 6'b000000, loader_addr[15:1] }
| {22{next_cpu}} & { cpu_csrom, {6{~cpu_csrom}} & cpu_addr[20:15], cpu_addr[14:0] }
| {22{next_vid}} & { 1'b0, video_addr }
| {22{next_ts}} & { 1'b0, ts_addr }
| {22{next_tm}} & { 1'b0, tm_addr }
| {22{next_dma}} & { 1'b0, dma_addr };
assign dram_addr = {23{next_loader}} & { loader_hiaddr, 6'b000000, loader_addr[15:1] }
| {23{next_cpu}} & { 1'b0, cpu_csrom, {6{~cpu_csrom}} & cpu_addr[20:15], cpu_addr[14:0] }
| {23{next_vid}} & { 2'b0, video_addr }
| {23{next_ts}} & { 2'b0, ts_addr }
| {23{next_tm}} & { 2'b0, tm_addr }
| {23{next_dma}} & { 2'b0, dma_addr };
reg cpu_rnw_r;
always @(posedge clk) if (c3)

304
rtl/dram/sdram.v
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@ -1,46 +1,71 @@
// READ 25 26 27 21 22 23 24
// RAS CAS read
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// T0 T1 T2 T3 T4 T5 T6
// 5.95ns ACT READ DQDQDQDQD
// tAC=6 tOH=3
// 25 26 27 28 29 30 31 20 21 22 23 24 25
// cpu_strobe ________________________________________________________________/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\_______________________________________________________________
// cyc ‾‾‾‾\_____________________________________________________________________________________________________________/‾‾‾‾‾‾‾‾‾\____
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// 5.95ns
//
// WRITE 25 26 27 22 23 24
// RAS CASWEDQ
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// T0 T1 T2 T3 T4 T5
// 5.95ns ACT WRITE
// REFRESH RASCAS
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// REFRSH
//
// READ+NOP RAS CAS latch set do
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// ACT READ DQDQDQDQD
//
// WRITE+NOP RAS CASWEDQ
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// ACT WRITE
//
// NOP+READ RAS CAS latch set do
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// ACT READ DQDQDQDQD
//
// NOP+WRITE RAS CASWEDQ
// clk_sys ____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾
// clk_ram ‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____/‾‾‾‾\____
// ACT WRITE
//
module sdram
(
// Memory port
input clk,
input cyc,
input clk,
input cyc,
input curr_cpu,
input [1:0] bsel, // Active HI
input [23:0] A,
input [15:0] DI,
output reg [15:0] DO,
output reg [15:0] DO_cpu,
input REQ,
input RNW,
// Memory port 1
input port1_curr_cpu,
input [1:0] port1_bsel,
input [23:0] port1_a,
input [15:0] port1_di,
output reg [15:0] port1_do,
output reg [15:0] port1_do_cpu,
input port1_req,
input port1_rnw,
// SDRAM Pin
inout reg [15:0] SDRAM_DQ,
output reg [12:0] SDRAM_A,
output reg [1:0] SDRAM_BA,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
output SDRAM_CKE,
output SDRAM_CLK
// Memory port 2
input [1:0] port2_bsel,
input [23:0] port2_a,
input [15:0] port2_di,
output reg [15:0] port2_do,
input port2_req,
input port2_rnw,
output reg port2_ack = 0,
// SDRAM Pin
inout reg [15:0] SDRAM_DQ,
output reg [12:0] SDRAM_A = 0,
output reg [1:0] SDRAM_BA = 0,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
output SDRAM_CKE,
output SDRAM_CLK
);
reg [2:0] sdr_cmd;
@ -48,88 +73,127 @@ reg [2:0] sdr_cmd;
localparam SdrCmd_xx = 3'b111; // no operation
localparam SdrCmd_ac = 3'b011; // activate
localparam SdrCmd_rd = 3'b101; // read
localparam SdrCmd_wr = 3'b100; // write
localparam SdrCmd_wr = 3'b100; // write
localparam SdrCmd_pr = 3'b010; // precharge all
localparam SdrCmd_re = 3'b001; // refresh
localparam SdrCmd_ms = 3'b000; // mode regiser set
reg [5:0] state = 0;
reg [15:0] data;
reg [8:0] col;
reg [23:0] Ar1, Ar2;
reg [1:0] dqm1, dqm2;
reg rq1, rq2;
reg rd1, rd2 = 0;
always @(posedge clk) begin
reg [4:0] state;
reg rd;
reg [8:0] col;
reg [1:0] dqm;
reg [15:0] data;
reg [23:0] Ar;
reg rq;
sdr_cmd <= SdrCmd_xx;
data <= SDRAM_DQ;
SDRAM_DQ <= 16'bZ;
state <= state + 1'd1;
port2_ack <= 1'b0;
sdr_cmd <= SdrCmd_xx;
data <= SDRAM_DQ;
SDRAM_DQ <= 16'bZ;
state <= state + 1'd1;
case (state)
case (state)
// Init
0: begin
sdr_cmd <= SdrCmd_pr; // PRECHARGE
end
// Init
0: begin
sdr_cmd <= SdrCmd_pr; // PRECHARGE
SDRAM_A <= 0;
SDRAM_BA <= 0;
end
// REFRESH
3,10: begin
sdr_cmd <= SdrCmd_re;
end
// REFRESH
3,10: begin
sdr_cmd <= SdrCmd_re;
end
// LOAD MODE REGISTER
17: begin
sdr_cmd <= SdrCmd_ms;
SDRAM_A <= {3'b000, 1'b1, 2'b00, 3'b010, 1'b0, 3'b000};
end
// LOAD MODE REGISTER
17: begin
sdr_cmd <= SdrCmd_ms;
SDRAM_A <= {3'b000, 1'b1, 2'b00, 3'b010, 1'b0, 3'b000};
end
// Idle
24: begin
state <= state;
Ar1 <= port1_a;
Ar2 <= port2_a;
dqm1 <= port1_rnw ? 2'b00 : ~port1_bsel;
dqm2 <= port2_rnw ? 2'b00 : ~port2_bsel;
rq1 <= port1_req;
rd1 <= port1_req & port1_rnw;
rq2 <= port2_req;
rd2 <= port2_req & port2_rnw;
if (cyc)
state <= state + 1'd1;
end
// Idle
24: begin
if (rd) begin
DO <= data;
if (curr_cpu) DO_cpu <= data;
end
// Start - activate (port1) or refresh
25: begin
if (rq1) begin
{SDRAM_BA,SDRAM_A,col} <= Ar1;
sdr_cmd <= SdrCmd_ac;
end
else if (rq2) begin
// start at state 28
end
else begin
sdr_cmd <= SdrCmd_re;
state <= 19;
end
end
state <= state;
Ar <= A;
dqm <= RNW ? 2'b00 : ~bsel;
rd <= 0;
// Single read/write (port1) - with auto precharge
27: begin
SDRAM_A <= {dqm1, 2'b1x, col};
if (rq1) begin
if (rd1) begin
sdr_cmd <= SdrCmd_rd;
end
else begin
sdr_cmd <= SdrCmd_wr;
SDRAM_DQ <= port1_di;
end
end
end
if(cyc) begin
rq <= REQ;
rd <= REQ & RNW;
state <= state + 1'd1;
end
end
// Start - activate (port2) or refresh
28: begin
if (rq2) begin
{SDRAM_BA,SDRAM_A,col} <= Ar2;
sdr_cmd <= SdrCmd_ac;
end
end
// Start
25: begin
if (rq) begin
{SDRAM_A,SDRAM_BA,col} <= Ar;
sdr_cmd <= SdrCmd_ac;
end else begin
sdr_cmd <= SdrCmd_re;
state <= 19;
end
end
// Latch read (port 1) and Single read/write (port2) - with auto precharge
31: begin
if (rd1) begin
port1_do <= data;
if (port1_curr_cpu) port1_do_cpu <= data;
end
// Single read/write - with auto precharge
27: begin
SDRAM_A <= {dqm, 2'b10, col};
state <= 21;
if (rd) sdr_cmd <= SdrCmd_rd;
else begin
sdr_cmd <= SdrCmd_wr;
SDRAM_DQ <= DI;
state <= 22;
end
end
SDRAM_A <= {dqm2, 2'b1x, col};
if (rq2) begin
if (rd2) begin
sdr_cmd <= SdrCmd_rd;
end
else begin
sdr_cmd <= SdrCmd_wr;
SDRAM_DQ <= port2_di;
port2_ack <= 1'b1;
end
end
endcase
state <= 20;
end
// Latch read (port 2)
23: begin
if (rd2) begin
port2_do <= data;
port2_ack <= 1'b1;
end
end
endcase
end
assign SDRAM_CKE = 1;
@ -142,27 +206,27 @@ assign SDRAM_DQMH = SDRAM_A[12];
altddio_out
#(
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone III"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1)
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone III"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1)
)
sdramclk_ddr
(
.datain_h(1'b0),
.datain_l(1'b1),
.outclock(clk),
.dataout(SDRAM_CLK),
.aclr(1'b0),
.aset(1'b0),
.oe(1'b1),
.outclocken(1'b1),
.sclr(1'b0),
.sset(1'b0)
.datain_h(1'b0),
.datain_l(1'b1),
.outclock(clk),
.dataout(SDRAM_CLK),
.aclr(1'b0),
.aset(1'b0),
.oe(1'b1),
.outclocken(1'b1),
.sclr(1'b0),
.sset(1'b0)
);
endmodule

76
rtl/sound/gs.v
View File

@ -6,6 +6,7 @@
18.08.2018 Reworked first verilog version
19.08.2018 Produce proper signed output
20.08.2018 Use external SDR/DDR RAM for page 2 and up
21.05.2020 Use external SDR/DDR RAM for all ROM/RAM
CPU: Z80 @ 28MHz
ROM: 32K
@ -68,31 +69,33 @@
module gs
(
input RESET,
input CLK,
input CE,
input RESET,
input CLK,
input CE,
input A,
input [7:0] DI,
output [7:0] DO,
input CS_n,
input WR_n,
input RD_n,
input A,
input [7:0] DI,
output [7:0] DO,
input CS_n,
input WR_n,
input RD_n,
output [20:0] MEM_ADDR,
output [7:0] MEM_DI,
input [7:0] MEM_DO,
output MEM_RD,
output MEM_WR,
input MEM_WAIT,
output MEM_ROM,
output [20:0] MEM_ADDR,
output [7:0] MEM_DI,
input [7:0] MEM_DO,
output MEM_RD,
output MEM_WR,
input MEM_WAIT,
output MEM_ROM,
output [14:0] OUTL,
output [14:0] OUTR
output [14:0] OUTL,
output [14:0] OUTR
);
parameter INT_DIV = 291;
// port #xxBB : #xxB3
assign DO = A ? {bit7, 6'b111111, bit0} : port_03;
assign DO = A ? {flag_data, 6'b111111, flag_cmd} : port_03;
// CPU
reg int_n;
@ -104,7 +107,7 @@ wire cpu_wr_n;
wire [15:0] cpu_a_bus;
wire [7:0] cpu_do_bus;
T80pa cpu
T80pa CPU
(
.RESET_n(~RESET),
.CLK(CLK),
@ -124,9 +127,12 @@ T80pa cpu
always @(posedge CLK) begin
reg [9:0] cnt;
if(CE) begin
if (RESET) begin
cnt <= 0;
int_n <= 1;
end else if(CE) begin
cnt <= cnt + 1'b1;
if (cnt == 746) begin // 37.48kHz
if (cnt == INT_DIV) begin // 37.48kHz
cnt <= 0;
int_n <= 0;
end
@ -136,22 +142,22 @@ always @(posedge CLK) begin
end
reg bit7;
reg bit0;
reg flag_data;
reg flag_cmd;
always @(posedge CLK) begin
if (~cpu_iorq_n & cpu_m1_n) begin
case(cpu_a_bus[3:0])
'h2: bit7 <= 0;
'h3: bit7 <= 1;
'h5: bit0 <= 0;
'hA: bit7 <= ~port_00[0];
'hB: bit0 <= port_09[5];
'h2: flag_data <= 0;
'h3: flag_data <= 1;
'h5: flag_cmd <= 0;
'hA: flag_data <= ~port_00[0];
'hB: flag_cmd <= port_09[5];
endcase
end
else if (~CS_n) begin
if (~A & ~RD_n) bit7 <= 0;
if (~A & ~WR_n) bit7 <= 1;
if ( A & ~WR_n) bit0 <= 1;
if (~CS_n) begin
if (~A & ~RD_n) flag_data <= 0;
if (~A & ~WR_n) flag_data <= 1;
if ( A & ~WR_n) flag_cmd <= 1;
end
end
@ -171,7 +177,7 @@ end
reg [5:0] port_00;
reg [7:0] port_03;
reg signed [6:0] port_06 = 0, port_07 = 0, port_08 = 0, port_09 = 0;
reg signed [6:0] port_06, port_07, port_08, port_09;
reg signed [7:0] ch_a, ch_b, ch_c, ch_d;
always @(posedge CLK) begin
@ -206,7 +212,7 @@ wire [7:0] cpu_di_bus =
(~cpu_mreq_n && ~cpu_rd_n) ? MEM_DO :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 1) ? port_BB :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 2) ? port_B3 :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 4) ? {bit7, 6'b111111, bit0} :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 4) ? {flag_data, 6'b111111, flag_cmd} :
8'hFF;

1383
rtl/sound/gs105b.mif
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File diff suppressed because it is too large Load Diff

125
rtl/sound/gs_top.v Normal file
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@ -0,0 +1,125 @@
module gs_top
(
input RESET,
input CLK,
input A,
input [7:0] DI,
output [7:0] DO,
input CS_n,
input WR_n,
input RD_n,
output [23:0] DRAM_ADDR,
output [2:0] DRAM_BSEL,
output [15:0] DRAM_DI,
input [15:0] DRAM_DO,
output DRAM_REQ,
output DRAM_RNW,
input DRAM_ACK,
output [14:0] OUTL,
output [14:0] OUTR,
input ROM_INITING
);
wire [20:0] mem_addr;
assign DRAM_ADDR = {4'b0100, mem_addr[20:1]};
assign DRAM_BSEL = {mem_addr[0], ~mem_addr[0]};
wire [15:0] mem_do16 = cache_hit? cache_do : DRAM_DO;
wire [7:0] mem_do = mem_addr[0]? mem_do16[15:8] : mem_do16[7:0];
wire [7:0] mem_di;
assign DRAM_DI = {mem_di, mem_di};
wire mem_rd;
wire mem_wr;
assign DRAM_RNW = ~mem_wr;
reg dram_req = 0;
assign DRAM_REQ = dram_req && !DRAM_ACK;
reg mem_rdwr = 0;
always @(posedge CLK) begin
if (((mem_rd && !cache_hit) || mem_wr) && !mem_rdwr)
dram_req <= 1'b1;
else if (DRAM_ACK)
dram_req <= 1'b0;
mem_rdwr <= mem_rd || mem_wr;
end
wire [7:0] cache_al = mem_addr[8:1];
wire [11:0] cache_ah = mem_addr[20:9];
wire [15:0] cache_do;
wire [11:0] cache_rd_ah;
wire cache_rd_v;
wire cache_hit = (cache_ah == cache_rd_ah) && cache_rd_v;
wire cache_inv = (cache_ah == cache_rd_ah) && mem_wr;
dpram #(.DATAWIDTH(16), .ADDRWIDTH(8)) cache_data
(
.clock(CLK),
.address_a(cache_al),
.data_a(DRAM_DO),
.wren_a(DRAM_ACK && mem_rd),
.address_b(cache_al),
.q_b(cache_do)
);
dpram #(.DATAWIDTH(13), .ADDRWIDTH(8)) cache_addr
(
.clock(CLK),
.address_a(cache_al),
.data_a({~cache_inv, cache_ah}),
.wren_a(DRAM_ACK && (mem_rd || cache_inv)),
.address_b(cache_al),
.q_b({cache_rd_v, cache_rd_ah})
);
reg rom_inited = 1'b0, rom_initing = 1'b0;
always @(posedge CLK) begin
if (!ROM_INITING && rom_initing)
rom_inited <= 1'b1;
rom_initing <= ROM_INITING;
end
reg reset;
always @(posedge CLK)
reset <= RESET || !rom_inited;
reg ce_14m;
always @(negedge CLK) begin
reg [2:0] div;
div <= div + 1'd1;
if(div == 5) div <= 0;
ce_14m <= !div;
end
gs #(.INT_DIV(373)) gs
(
.RESET(reset),
.CLK(CLK),
.CE(ce_14m),
.A(A),
.DI(DI),
.DO(DO),
.CS_n(CS_n),
.WR_n(WR_n),
.RD_n(RD_n),
.MEM_ADDR(mem_addr),
.MEM_DI(mem_di),
.MEM_DO(mem_do),
.MEM_RD(mem_rd),
.MEM_WR(mem_wr),
.MEM_WAIT(DRAM_REQ),
.OUTL(OUTL),
.OUTR(OUTR)
);
endmodule

72
rtl/tsconf.v
View File

@ -61,8 +61,10 @@ module tsconf
input [15:0] loader_addr,
input [7:0] loader_do,
output [7:0] loader_di,
input loader_wr_rom,
input loader_wr_cmos
input loader_wr,
input loader_cs_rom_main,
input loader_cs_rom_gs,
input loader_cs_cmos
);
wire f0, f1, h0, h1, c0, c1, c2, c3;
@ -159,7 +161,7 @@ module tsconf
wire vdos_on, vdos_off;
wire dos_on, dos_off;
wire [21:0] daddr;
wire [22:0] daddr;
wire dreq;
wire drnw;
wire [15:0] dram_rd_r;
@ -440,14 +442,21 @@ module tsconf
(
.clk(clk),
.cyc(ce&c3),
.curr_cpu(curr_cpu),
.bsel(dbsel),
.A(daddr),
.DI(dram_wrdata),
.DO(dram_do),
.DO_cpu(dram_docpu),
.REQ(dreq),
.RNW(drnw),
.port1_curr_cpu(curr_cpu),
.port1_bsel(dbsel),
.port1_a(daddr),
.port1_di(dram_wrdata),
.port1_do(dram_do),
.port1_do_cpu(dram_docpu),
.port1_req(dreq),
.port1_rnw(drnw),
.port2_bsel(gs_dram_bsel),
.port2_a(gs_dram_addr),
.port2_di(gs_dram_di),
.port2_do(gs_dram_do),
.port2_req(gs_dram_req),
.port2_rnw(gs_dram_rnw),
.port2_ack(gs_dram_ack),
.SDRAM_DQ(SDRAM_DQ),
.SDRAM_A(SDRAM_A),
.SDRAM_BA(SDRAM_BA),
@ -505,7 +514,9 @@ module tsconf
.loader_clk(clk),
.loader_addr(loader_addr),
.loader_data(loader_do),
.loader_wr(loader_wr_rom)
.loader_wr(loader_wr),
.loader_cs_rom_main(loader_cs_rom_main),
.loader_cs_rom_gs(loader_cs_rom_gs)
);
video_top video_top
@ -952,7 +963,7 @@ module tsconf
.A(wait_addr),
.DI(d),
.DO(wait_read),
.loader_WR(loader_wr_cmos),
.loader_WR(loader_wr && loader_cs_cmos),
.loader_A(loader_addr[7:0]),
.loader_DI(loader_do),
.loader_DO(loader_di)
@ -1012,23 +1023,23 @@ module tsconf
// General Sound
wire [20:0] gs_mem_addr;
wire [7:0] gs_mem_di;
wire [7:0] gs_mem_do;
wire gs_mem_rd;
wire gs_mem_wr;
wire gs_mem_wait;
wire [23:0] gs_dram_addr;
wire [1:0] gs_dram_bsel;
wire [15:0] gs_dram_di;
wire [15:0] gs_dram_do;
wire gs_dram_req;
wire gs_dram_rnw;
wire gs_dram_ack;
wire [14:0] gs_l;
wire [14:0] gs_r;
wire [7:0] gs_do_bus;
wire gs_sel = ~iorq_n & m1_n & (a[7:4] == 'hB && a[2:0] == 'h3);
gs gs
gs_top gs_top
(
.RESET(rst | 1'b1),
.RESET(rst),
.CLK(clk),
.CE(ce),
.A(a[3]),
.DI(d),
@ -1037,15 +1048,18 @@ module tsconf
.WR_n(wr_n),
.RD_n(rd_n),
.MEM_ADDR(gs_mem_addr),
.MEM_DI(gs_mem_di),
.MEM_DO(gs_mem_do),
.MEM_RD(gs_mem_rd),
.MEM_WR(gs_mem_wr),
.MEM_WAIT(gs_mem_wait),
.DRAM_ADDR(gs_dram_addr),
.DRAM_BSEL(gs_dram_bsel),
.DRAM_DI(gs_dram_di),
.DRAM_DO(gs_dram_do),
.DRAM_REQ(gs_dram_req),
.DRAM_RNW(gs_dram_rnw),
.DRAM_ACK(gs_dram_ack),
.OUTL(gs_l),
.OUTR(gs_r)
.OUTR(gs_r),
.ROM_INITING(loader_act && loader_cs_rom_gs)
);