uzix/zx-tsid
1
0
Fork 0
mirror of https://github.com/UzixLS/zx-tsid.git synced 2025-07-19 07:11:16 +03:00
Code Issues Projects Releases Wiki Activity

cpld: improve AY port decoding

Browse Source
This commit is contained in:
UzixLS
2020-10-20 21:20:30 +03:00
parent 7d9fbfc928
commit 7189873a6d
1 changed files with 4 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
cpld/top.v
View File

@ -55,8 +55,8 @@ always @* sid_cs <= 1'b1;
/* AY */ /* AY */
`ifdef AY_ENABLE `ifdef AY_ENABLE
wire port_bffd = a15 == 1'b1 && a[1] == 0 ; wire port_bffd = a15 == 1'b1 && a == 8'hFD;
wire port_fffd = a15 == 1'b1 && a14 == 1'b1 && a[1] == 0; wire port_fffd = a15 == 1'b1 && a14 == 1'b1 && a == 8'hFD;
reg ay_sel; reg ay_sel;
always @(negedge clk or negedge n_rst) begin always @(negedge clk or negedge n_rst) begin
if (!n_rst) begin if (!n_rst) begin
@ -65,10 +65,8 @@ always @(negedge clk or negedge n_rst) begin
ay_sel <= 1'b1; ay_sel <= 1'b1;
end end
else begin else begin
if (ay_sel) begin ay_bc1 <= ay_sel && ioreq && port_fffd;
ay_bc1 <= ioreq && port_fffd; ay_bdir <= ay_sel && ioreq && port_bffd && n_wr == 1'b0;
ay_bdir <= ioreq && port_bffd && n_wr == 1'b0;
end
if (ioreq && port_fffd && n_wr == 1'b0 && d[7:1] == 7'b1111111) if (ioreq && port_fffd && n_wr == 1'b0 && d[7:1] == 7'b1111111)
ay_sel <= d[0] == 1'b0; ay_sel <= d[0] == 1'b0;
end end