mirror of
https://github.com/UzixLS/zx-tsid.git
synced 2025-07-19 07:11:16 +03:00
147 lines
2.8 KiB
Verilog
147 lines
2.8 KiB
Verilog
`define AY_ENABLE
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`define SID_ENABLE
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`define DAC_ENABLE
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//`define BEEPER_ENABLE
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module top(
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input n_rst,
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input clk,
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input [7:0] a,
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input a14,
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input a15,
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input [7:0] d,
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input n_wr,
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input n_m1,
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input n_iorq,
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output reg n_iorqge,
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output dac,
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output reg ay_bc1,
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output reg ay_bdir,
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output reg ay_clk,
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output reg sid_cs,
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output sid_clk
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);
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wire ioreq = n_iorq == 0 && n_m1 == 1'b1;
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/* SID */
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`ifdef SID_ENABLE
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wire port_cf = a == 8'hCF;
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always @(negedge clk or negedge n_rst) begin
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if (!n_rst)
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sid_cs <= 1'b1;
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else
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sid_cs <= (ioreq && port_cf)? 1'b0 : 1'b1;
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end
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reg [1:0] sid_clk0;
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assign sid_clk = sid_clk0[1];
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always @(negedge clk or negedge n_rst) begin
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if (!n_rst)
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sid_clk0 <= 0;
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else
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sid_clk0 <= sid_clk0 + 1'b1;
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end
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`else /* SID_ENABLE */
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wire port_cf = 0;
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always @* sid_clk <= 0;
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always @* sid_cs <= 1'b1;
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`endif /* SID_ENABLE */
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/* AY */
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`ifdef AY_ENABLE
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wire port_bffd = a15 == 1'b1 && a == 8'hFD;
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wire port_fffd = a15 == 1'b1 && a14 == 1'b1 && a == 8'hFD;
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reg ay_sel;
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always @(negedge clk or negedge n_rst) begin
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if (!n_rst) begin
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ay_bc1 <= 0;
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ay_bdir <= 0;
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ay_sel <= 1'b1;
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end
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else begin
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ay_bc1 <= ay_sel && ioreq && port_fffd;
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ay_bdir <= ay_sel && ioreq && port_bffd && n_wr == 1'b0;
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if (ioreq && port_fffd && n_wr == 1'b0 && d[7:1] == 7'b1111111)
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ay_sel <= d[0] == 1'b0;
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end
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end
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always @(negedge clk or negedge n_rst) begin
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if (!n_rst)
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ay_clk <= 0;
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else
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ay_clk <= ~ay_clk;
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end
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`else /* AY_ENABLE */
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wire port_fffd = 0;
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wire port_bffd = 0;
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wire ay_sel = 0;
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always @* ay_bc1 <= 0;
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always @* ay_bdir <= 0;
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`endif /* AY_ENABLE */
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/* BEEPER & TAPE OUT */
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`ifdef BEEPER_ENABLE
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wire port_fe = a[0] == 0;
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reg beeper, tape_out;
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always @(negedge clk or negedge n_rst) begin
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if (!n_rst) begin
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beeper <= 1'b0;
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tape_out <= 1'b0;
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end
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else if (ioreq && port_fe && n_wr == 1'b0) begin
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beeper <= d[4];
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tape_out <= d[3];
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end
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end
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`else /* BEEPER_ENABLE */
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wire beeper = 0;
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wire tape_out = 0;
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`endif /* BEEPER_ENABLE */
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`ifdef DAC_ENABLE
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/* COVOX */
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reg [7:0] covox_data;
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wire port_fb = a == 8'hFB;
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always @(negedge clk or negedge n_rst) begin
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if (!n_rst)
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covox_data <= 0;
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else if (ioreq && port_fb && n_wr == 1'b0)
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covox_data <= d;
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end
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reg [8:0] dac_acc;
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assign dac = dac_acc[8];
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wire [8:0] dac_acc_next = covox_data + {1'b0, beeper, tape_out, 5'b00000};
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always @(negedge clk or negedge n_rst) begin
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if (!n_rst)
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dac_acc <= 0;
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else
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dac_acc <= dac_acc[7:0] + dac_acc_next[8:1];
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end
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`else /* DAC_ENABLE */
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wire port_fb = 0;
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assign dac = 1'bz;
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`endif /* DAC_ENABLE */
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/* BUS CONTROL */
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always @(posedge clk)
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n_iorqge <= (port_cf || port_fb || ((port_bffd || port_fffd) && ay_sel))? 1'b1 : 1'bz;
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endmodule
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