uzix/zx-tsid
1
0
Fork 0
mirror of https://github.com/UzixLS/zx-tsid.git synced 2025-07-18 23:01:33 +03:00
Code Issues Projects Releases Wiki Activity

wip

Browse Source
This commit is contained in:
UzixLS
2020-05-17 11:48:26 +03:00
parent 029de031a3
commit 15ff6cea5b
12 changed files with 9853 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
LICENSE Normal file
View File

@ -0,0 +1,21 @@
MIT License
Copyright (c) 2020 Eugene Lozovoy
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

23
README.md Normal file
View File

@ -0,0 +1,23 @@
## ZX-TSid
Sound card for ZX Spectrum edge connector (ZX-BUS). Contains MOS SID, YM2149 (AY-3-8910) and covox.
### Current status
Work in progress, both pcb and firmware isn't finished yet and may contain serious issues.
### SID
MOS-6581 or MOS-8580 may be installed, but with some cautions. This addon doesn't contain buffers between SID and bus connector, and that may cause SID's damage by ESD if no luck. As I have no real SID, I've checked this addon only with SwinSID.
SID accessible via #xxCF port, where xx - SID's register number.
### YM2149 (AY-3-8910)
Accessible by TurboSound standard as a second sound chip. ABC or ACB stereo panning selectable with onboard jumpers.
### Covox
Monophonic covox accessible via #xxFB port (Pentagon standard).
### Line input
You may connect your ZX Spectrum audio output to second 3.5mm jack and it will be mixed in sound card output signal.
### Compatibility
SID and Covox (theoretically) should work with any ZX Spectrum containing edge connector (48K, 128K, +3, clones, etc.).
YM2149 uses IORQGE signal, which is incompletely implemented in original ZX Spectrums and most clones (such as Harlequin). Sizif-512 and Karabas-128 clones implements IORQGE in right way.

4
cpld/clocks.sdc Normal file
View File

@ -0,0 +1,4 @@
create_clock -period 7.2MHz -name {clk} [get_ports {clk}]
derive_clock_uncertainty
derive_clocks -period 7.2MHz

149
cpld/top.v Normal file
View File

@ -0,0 +1,149 @@
`define AY_ENABLE
`define AY_TURBOSOUND_MODE
`define SID_ENABLE
`define DAC_ENABLE
`define BEEPER_ENABLE
module top(
input n_rst,
input clk,
input [7:0] a,
input a14,
input a15,
input [7:0] d,
input n_wr,
input n_m1,
input n_iorq,
output reg n_iorqge,
output dac,
output reg ay_bc1,
output reg ay_bdir,
output reg ay_clk,
output reg sid_cs,
output sid_clk
);
wire ioreq = n_iorq == 0 && n_m1 == 1'b1;
/* SID */
`ifdef SID_ENABLE
wire port_cf = a == 8'hCF;
always @(posedge clk)
sid_cs <= ioreq && port_cf;
reg [1:0] sid_clk0;
assign sid_clk = sid_clk0[1];
always @(posedge clk or negedge n_rst) begin
if (!n_rst)
sid_clk0 <= 0;
else
sid_clk0 <= sid_clk0 + 1'b1;
end
`else /* SID_ENABLE */
wire port_cf = 0;
always @* sid_clk <= 0;
always @* sid_cs <= 0;
`endif /* SID_ENABLE */
/* AY */
`ifdef AY_ENABLE
wire port_fffd = a15 == 1'b1 && a[1] == 0 ;
wire port_bffd = a15 == 1'b1 && a14 == 1'b1 && a[1] == 0;
reg ay_sel;
always @(posedge clk or negedge n_rst) begin
if (!n_rst) begin
ay_bc1 <= 0;
ay_bdir <= 0;
`ifdef AY_TURBOSOUND_MODE
ay_sel <= 0;
`else
ay_sel <= 1'b1;
`endif
end
else begin
ay_bc1 <= ioreq && port_bffd;
ay_bdir <= ioreq && port_fffd && n_wr == 1'b0;
`ifdef AY_TURBOSOUND_MODE
if (ioreq && port_fffd && n_wr == 1'b0 && d[7:3] == 5'b11111)
ay_sel <= d[2:0] == 3'b001;
`endif
end
end
always @(posedge clk or negedge n_rst) begin
if (!n_rst)
ay_clk <= 0;
else
ay_clk <= ~ay_clk;
end
`else /* AY_ENABLE */
wire port_fffd = 0;
wire port_bffd = 0;
wire ay_sel = 0;
always @* ay_bc1 <= 0;
always @* ay_bdir <= 0;
`endif /* AY_ENABLE */
/* BEEPER & TAPE OUT */
`ifdef BEEPER_ENABLE
wire port_fe = a[0] == 0;
reg beeper, tape_out;
always @(posedge clk or negedge n_rst) begin
if (!n_rst) begin
beeper <= 1'b0;
tape_out <= 1'b0;
end
else if (ioreq && port_fe && n_wr == 1'b0) begin
beeper <= d[4];
tape_out <= d[3];
end
end
`else /* BEEPER_ENABLE */
wire beeper = 0;
wire tape_out = 0;
`endif /* BEEPER_ENABLE */
`ifdef DAC_ENABLE
/* COVOX */
reg [7:0] covox_data;
wire port_fb = a == 8'hFB;
always @(posedge clk or negedge n_rst) begin
if (!n_rst)
covox_data <= 0;
else if (ioreq && port_fb && n_wr == 0)
covox_data <= d;
end
reg [8:0] dac_acc;
assign dac = dac_acc[8];
wire [8:0] dac_acc_next = covox_data + {1'b0, beeper, tape_out, 5'b00000};
always @(posedge clk or negedge n_rst) begin
if (!n_rst)
dac_acc <= 0;
else
dac_acc <= dac_acc[7:0] + dac_acc_next[8:1];
end
`else /* DAC_ENABLE */
wire port_fb = 0;
assign dac <= 1'bz;
`endif /* DAC_ENABLE */
/* BUS CONTROL */
always @(posedge clk)
n_iorqge <= (port_cf || port_fb || ((port_bffd || port_fffd) && ay_sel))? 1'b1 : 1'bz;
endmodule

30
cpld/zx-tsid.qpf Normal file
View File

@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 13:37:37 May 16, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "13:37:37 May 16, 2020"
# Revisions
PROJECT_REVISION = "zx-tsid"

86
cpld/zx-tsid.qsf Normal file
View File

@ -0,0 +1,86 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 13:37:37 May 16, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx-tsid_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3064ATC44-10"
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:37:37 MAY 16, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_8 -to a[0]
set_location_assignment PIN_10 -to d[7]
set_location_assignment PIN_12 -to a15
set_location_assignment PIN_13 -to a14
set_location_assignment PIN_14 -to d[0]
set_location_assignment PIN_15 -to d[1]
set_location_assignment PIN_18 -to d[2]
set_location_assignment PIN_19 -to dac
set_location_assignment PIN_20 -to sid_clk
set_location_assignment PIN_21 -to sid_cs
set_location_assignment PIN_22 -to ay_clk
set_location_assignment PIN_37 -to clk
set_location_assignment PIN_23 -to ay_bdir
set_location_assignment PIN_25 -to ay_bc1
set_location_assignment PIN_27 -to n_m1
set_location_assignment PIN_28 -to a[4]
set_location_assignment PIN_31 -to a[5]
set_location_assignment PIN_33 -to a[6]
set_location_assignment PIN_34 -to a[7]
set_location_assignment PIN_35 -to n_iorqge
set_location_assignment PIN_38 -to n_wr
set_location_assignment PIN_40 -to n_iorq
set_location_assignment PIN_2 -to a[2]
set_location_assignment PIN_3 -to d[5]
set_location_assignment PIN_5 -to a[1]
set_location_assignment PIN_6 -to d[6]
set_location_assignment PIN_42 -to d[4]
set_location_assignment PIN_43 -to a[3]
set_location_assignment PIN_44 -to d[3]
set_location_assignment PIN_39 -to n_rst

BIN
out/pcb3d-bottom.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 628 KiB

BIN
out/pcb3d-top.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 846 KiB

555
pcb/zx-tsid-cache.lib Normal file
View File

@ -0,0 +1,555 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 65xx_8580
#
DEF 65xx_8580 U 0 40 Y Y 1 F N
F0 "U" -400 1300 50 H V L CNN
F1 "65xx_8580" 0 0 50 V V C CIB
F2 "" 0 150 50 H I C CNN
F3 "" 0 150 50 H I C CNN
ALIAS 8580
$FPLIST
DIP-28_W15.24mm*
$ENDFPLIST
DRAW
S -400 1250 400 -1250 0 1 0 f
X CAP1A 1 600 -600 200 L 50 50 1 1 P
X A1 10 -600 300 200 R 50 50 1 1 I
X A2 11 -600 200 200 R 50 50 1 1 I
X A3 12 -600 100 200 R 50 50 1 1 I
X A4 13 -600 0 200 R 50 50 1 1 I
X GND 14 0 -1450 200 U 50 50 1 1 W
X D0 15 -600 -400 200 R 50 50 1 1 B
X D1 16 -600 -500 200 R 50 50 1 1 B
X D2 17 -600 -600 200 R 50 50 1 1 B
X D3 18 -600 -700 200 R 50 50 1 1 B
X D4 19 -600 -800 200 R 50 50 1 1 B
X CAP1B 2 600 -700 200 L 50 50 1 1 P
X D5 20 -600 -900 200 R 50 50 1 1 B
X D6 21 -600 -1000 200 R 50 50 1 1 B
X D7 22 -600 -1100 200 R 50 50 1 1 B
X POT_Y 23 600 0 200 L 50 50 1 1 I
X POT_X 24 600 100 200 L 50 50 1 1 I
X +5V 25 0 1450 200 D 50 50 1 1 W
X EXT_IN 26 600 600 200 L 50 50 1 1 I
X AUDIO_OUT 27 600 800 200 L 50 50 1 1 O
X +9V 28 100 1450 200 D 50 50 1 1 W
X CAP2A 3 600 -1000 200 L 50 50 1 1 P
X CAP2B 4 600 -1100 200 L 50 50 1 1 P
X ~RES 5 -600 1100 200 R 50 50 1 1 I L
X ϕ2 6 -600 1000 200 R 50 50 1 1 I C
X R/~W 7 -600 -200 200 R 50 50 1 1 I
X ~CS 8 -600 600 200 R 50 50 1 1 I L
X A0 9 -600 400 200 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Connector_AudioJack3_SwitchTR
#
DEF Connector_AudioJack3_SwitchTR J 0 20 Y Y 1 F N
F0 "J" 0 350 50 H V C CNN
F1 "Connector_AudioJack3_SwitchTR" 0 250 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Jack*
$ENDFPLIST
DRAW
S -200 -200 -250 -300 0 1 10 F
S 100 150 -200 -400 0 1 10 f
P 2 0 1 0 20 -10 30 -30 N
P 2 0 1 0 70 -210 80 -230 N
P 4 0 1 10 0 -200 25 -225 50 -200 100 -200 N
P 4 0 1 0 100 -300 70 -300 70 -210 60 -230 N
P 4 0 1 0 100 -100 20 -100 20 -10 10 -30 N
P 5 0 1 10 -75 -200 -50 -225 -25 -200 -25 0 100 0 N
P 5 0 1 10 100 100 -100 100 -100 -200 -125 -225 -150 -200 N
X ~ R 200 0 100 L 50 50 1 1 P
X ~ RN 200 -100 100 L 50 50 1 1 P
X ~ S 200 100 100 L 50 50 1 1 P
X ~ T 200 -200 100 L 50 50 1 1 P
X ~ TN 200 -300 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x05_Odd_Even
#
DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 -200 150 L 50 50 1 1 P
X Pin_2 2 300 200 150 L 50 50 1 1 P
X Pin_3 3 -200 100 150 R 50 50 1 1 P
X Pin_4 4 300 100 150 L 50 50 1 1 P
X Pin_5 5 -200 0 150 R 50 50 1 1 P
X Pin_6 6 300 0 150 L 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 300 -100 150 L 50 50 1 1 P
X Pin_9 9 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# EPM3064A-44TQFP_EPM3128-100TQFP_EPM3064A-44TQFP
#
DEF EPM3064A-44TQFP_EPM3128-100TQFP_EPM3064A-44TQFP U 0 40 Y Y 1 F N
F0 "U" 0 0 60 H V C CNN
F1 "EPM3064A-44TQFP_EPM3128-100TQFP_EPM3064A-44TQFP" -850 1350 60 H V C CNN
F2 "" 2650 350 60 H V C CNN
F3 "" 2650 350 60 H V C CNN
DRAW
T 0 -200 -650 79 0 0 0 A Normal 1 C C
T 0 200 -650 79 0 0 0 B Normal 1 C C
T 0 200 100 79 0 0 0 C Normal 1 C C
T 0 200 800 79 0 0 0 D Normal 1 C C
S -550 1250 550 -1200 0 0 0 f
X TDI 1 -750 500 197 R 50 60 1 1 I
X I/O 10 750 -550 197 L 50 60 1 1 I
X GNDIO 11 -150 -1300 100 U 50 60 1 1 I
X I/O 12 750 -650 197 L 50 60 1 1 I
X I/O 13 750 -750 197 L 50 60 1 1 I
X I/O 14 750 -850 197 L 50 60 1 1 I
X I/O 15 750 -950 197 L 50 60 1 1 I
X GNDINT 16 150 -1300 100 U 50 60 1 1 I
X VCCINT 17 50 1350 100 D 50 60 1 1 I
X I/O 18 750 -200 197 L 50 60 1 1 I
X I/O 19 750 -100 197 L 50 60 1 1 I
X I/O 2 -750 -350 197 R 50 60 1 1 I
X I/O 20 750 0 197 L 50 60 1 1 I
X I/O 21 750 100 197 L 50 60 1 1 I
X I/O 22 750 200 197 L 50 60 1 1 I
X I/O 23 750 300 197 L 50 60 1 1 I
X GNDIO 24 -50 -1300 100 U 50 60 1 1 I
X I/O 25 750 400 197 L 50 60 1 1 I
X TCK 26 -750 300 197 R 50 60 1 1 I
X I/O 27 750 600 197 L 50 60 1 1 I
X I/O 28 750 700 197 L 50 60 1 1 I
X VCCIO 29 -50 1350 100 D 50 60 1 1 I
X I/O 3 -750 -450 197 R 50 60 1 1 I
X GNDIO 30 50 -1300 100 U 50 60 1 1 I
X I/O 31 750 800 197 L 50 60 1 1 I
X TDO 32 -750 200 197 R 50 60 1 1 I
X I/O 33 750 900 197 L 50 60 1 1 I
X I/O 34 750 1000 197 L 50 60 1 1 I
X I/O 35 750 1100 197 L 50 60 1 1 I
X GNDINT 36 250 -1300 100 U 50 60 1 1 I
X GCLK1 37 -750 1000 197 R 50 60 1 1 I
X OE1 38 -750 800 197 R 50 60 1 1 I
X GCLRn 39 -750 900 197 R 50 60 1 1 I
X GNDIO 4 -250 -1300 100 U 50 60 1 1 I
X OE2/GCLK2 40 -750 700 197 R 50 60 1 1 I
X VCCINT 41 150 1350 100 D 50 60 1 1 I
X I/O 42 -750 -750 197 R 50 60 1 1 I
X I/O 43 -750 -850 197 R 50 60 1 1 I
X I/O 44 -750 -950 197 R 50 60 1 1 I
X I/O 5 -750 -550 197 R 50 60 1 1 I
X I/O 6 -750 -650 197 R 50 60 1 1 I
X TMS 7 -750 400 197 R 50 60 1 1 I
X I/O 8 750 -450 197 L 50 60 1 1 I
X VCCIO 9 -150 1350 100 D 50 60 1 1 I
ENDDRAW
ENDDEF
#
# Jumper_Jumper_3_Open
#
DEF Jumper_Jumper_3_Open JP 0 0 Y N 1 F N
F0 "JP" -100 -100 50 H V C CNN
F1 "Jumper_Jumper_3_Open" 0 110 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SolderJumper*Open*
$ENDFPLIST
DRAW
A -65 -30 89 1282 518 0 1 0 N -120 40 -10 40
A 65 -30 89 1282 518 0 1 0 N 10 40 120 40
C -130 0 20 0 0 0 N
C 0 0 20 0 0 0 N
C 130 0 20 0 0 0 N
P 2 0 1 0 0 -20 0 -50 N
X A 1 -250 0 100 R 50 50 1 1 P
X C 2 0 -150 100 U 50 50 1 1 I
X B 3 250 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole
#
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
F0 "H" 0 200 50 H V C CNN
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*
$ENDFPLIST
DRAW
C 0 0 50 0 1 50 N
ENDDRAW
ENDDEF
#
# Regulator_Linear_AMS1117-3.3
#
DEF Regulator_Linear_AMS1117-3.3 U 0 10 Y Y 1 F N
F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_AMS1117-3.3" 0 125 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN
F3 "" 100 -250 50 H I C CNN
ALIAS AP1117-18 AP1117-25 AP1117-33 AP1117-50 LD1117S33TR_SOT223 LD1117S12TR_SOT223 LD1117S18TR_SOT223 LD1117S25TR_SOT223 LD1117S50TR_SOT223 NCP1117-12_SOT223 NCP1117-1.5_SOT223 NCP1117-1.8_SOT223 NCP1117-2.0_SOT223 NCP1117-2.5_SOT223 NCP1117-2.85_SOT223 NCP1117-3.3_SOT223 NCP1117-5.0_SOT223 AMS1117-1.5 AMS1117-1.8 AMS1117-2.5 AMS1117-2.85 AMS1117-3.3 AMS1117-5.0
$FPLIST
SOT?223*TabPin2*
$ENDFPLIST
DRAW
S -200 -200 200 75 0 1 10 f
X GND 1 0 -300 100 U 50 50 1 1 W
X VO 2 300 0 100 L 50 50 1 1 w
X VI 3 -300 0 100 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Transistor_BJT_BC847
#
DEF Transistor_BJT_BC847 Q 0 0 Y N 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "Transistor_BJT_BC847" 200 0 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23" 200 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
ALIAS BC818 BC847 BC848 BC849 BC850 MMBT3904 MMBT5550L MMBT5551L
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 25 25 100 100 N
P 3 0 1 0 25 -25 100 -100 100 -100 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
X B 1 -200 0 225 R 50 50 1 1 I
X E 2 100 -200 100 U 50 50 1 1 P
X C 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# my_YM2149
#
DEF my_YM2149 U 0 40 Y Y 1 F N
F0 "U" -400 1300 39 H V C CNN
F1 "my_YM2149" 300 1300 39 H V C CNN
F2 "" 0 1600 39 H I C CNN
F3 "" 0 1600 39 H I C CNN
DRAW
S -450 1250 450 -950 0 1 0 f
X VSS 1 0 -1100 150 U 50 50 1 1 W
X IOB3 10 600 -450 150 L 50 50 1 1 B
X IOB2 11 600 -350 150 L 50 50 1 1 B
X IOB1 12 600 -250 150 L 50 50 1 1 B
X IOB0 13 600 -150 150 L 50 50 1 1 B
X IOA7 14 600 -50 150 L 50 50 1 1 B
X IOA6 15 600 50 150 L 50 50 1 1 B
X IOA5 16 600 150 150 L 50 50 1 1 B
X IOA4 17 600 250 150 L 50 50 1 1 B
X IOA3 18 600 350 150 L 50 50 1 1 B
X IOA2 19 600 450 150 L 50 50 1 1 B
X NC 2 -600 -850 150 R 50 50 1 1 N N
X IOA1 20 600 550 150 L 50 50 1 1 B
X IOA0 21 600 650 150 L 50 50 1 1 B
X CLOCK 22 -600 -400 150 R 50 50 1 1 I C
X ~RESET~ 23 -600 -300 150 R 50 50 1 1 I I
X ~A9~ 24 -600 200 150 R 50 50 1 1 I I
X A8 25 -600 300 150 R 50 50 1 1 I
X ~SEL~ 26 -600 -500 150 R 50 50 1 1 I I
X BDIR 27 -600 50 150 R 50 50 1 1 I
X BC2 28 -600 -150 150 R 50 50 1 1 I
X BC1 29 -600 -50 150 R 50 50 1 1 I
X B 3 600 1050 150 L 50 50 1 1 O
X DA7 30 -600 450 150 R 50 50 1 1 B
X DA6 31 -600 550 150 R 50 50 1 1 B
X DA5 32 -600 650 150 R 50 50 1 1 B
X DA4 33 -600 750 150 R 50 50 1 1 B
X DA3 34 -600 850 150 R 50 50 1 1 B
X DA2 35 -600 950 150 R 50 50 1 1 B
X DA1 36 -600 1050 150 R 50 50 1 1 B
X DA0 37 -600 1150 150 R 50 50 1 1 B
X C 38 600 950 150 L 50 50 1 1 O
X TEST1 39 600 800 150 L 50 50 1 1 O
X A 4 600 1150 150 L 50 50 1 1 O
X VCC 40 0 1400 150 D 50 50 1 1 W
X NC 5 -600 -750 150 R 50 50 1 1 N N
X IOB7 6 600 -850 150 L 50 50 1 1 B
X IOB6 7 600 -750 150 L 50 50 1 1 B
X IOB5 8 600 -650 150 L 50 50 1 1 B
X IOB4 9 600 -550 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# my_zx_edge
#
DEF my_zx_edge J 0 40 Y N 1 F N
F0 "J" 50 1400 50 H V C CNN
F1 "my_zx_edge" 50 -1500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1395 0 -1405 1 1 6 N
S -50 -1295 0 -1305 1 1 6 N
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1305 0 1295 1 1 6 N
S -50 1350 150 -1450 1 1 10 f
S 150 -1395 100 -1405 1 1 6 N
S 150 -1295 100 -1305 1 1 6 N
S 150 -1195 100 -1205 1 1 6 N
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 1005 100 995 1 1 6 N
S 150 1105 100 1095 1 1 6 N
S 150 1205 100 1195 1 1 6 N
S 150 1305 100 1295 1 1 6 N
X Pin_a1 A1 -200 1300 150 R 50 50 1 1 P
X Pin_a10 A10 -200 400 150 R 50 50 1 1 P
X Pin_a11 A11 -200 300 150 R 50 50 1 1 P
X Pin_a12 A12 -200 200 150 R 50 50 1 1 P
X Pin_a13 A13 -200 100 150 R 50 50 1 1 P
X Pin_a14 A14 -200 0 150 R 50 50 1 1 P
X Pin_a15 A15 -200 -100 150 R 50 50 1 1 P
X Pin_a16 A16 -200 -200 150 R 50 50 1 1 P
X Pin_a17 A17 -200 -300 150 R 50 50 1 1 P
X Pin_a18 A18 -200 -400 150 R 50 50 1 1 P
X Pin_a19 A19 -200 -500 150 R 50 50 1 1 P
X Pin_a2 A2 -200 1200 150 R 50 50 1 1 P
X Pin_a20 A20 -200 -600 150 R 50 50 1 1 P
X Pin_a21 A21 -200 -700 150 R 50 50 1 1 P
X Pin_a22 A22 -200 -800 150 R 50 50 1 1 P
X Pin_a23 A23 -200 -900 150 R 50 50 1 1 P
X Pin_a24 A24 -200 -1000 150 R 50 50 1 1 P
X Pin_a25 A25 -200 -1100 150 R 50 50 1 1 P
X Pin_a26 A26 -200 -1200 150 R 50 50 1 1 P
X Pin_a27 A27 -200 -1300 150 R 50 50 1 1 P
X Pin_a28 A28 -200 -1400 150 R 50 50 1 1 P
X Pin_a3 A3 -200 1100 150 R 50 50 1 1 P
X Pin_a4 A4 -200 1000 150 R 50 50 1 1 P
X Pin_a6 A6 -200 800 150 R 50 50 1 1 P
X Pin_a7 A7 -200 700 150 R 50 50 1 1 P
X Pin_a8 A8 -200 600 150 R 50 50 1 1 P
X Pin_a9 A9 -200 500 150 R 50 50 1 1 P
X Pin_b1 B1 300 1300 150 L 50 50 1 1 P
X Pin_b10 B10 300 400 150 L 50 50 1 1 P
X Pin_b11 B11 300 300 150 L 50 50 1 1 P
X Pin_b12 B12 300 200 150 L 50 50 1 1 P
X Pin_b13 B13 300 100 150 L 50 50 1 1 P
X Pin_b14 B14 300 0 150 L 50 50 1 1 P
X Pin_b15 B15 300 -100 150 L 50 50 1 1 P
X Pin_b16 B16 300 -200 150 L 50 50 1 1 P
X Pin_b17 B17 300 -300 150 L 50 50 1 1 P
X Pin_b18 B18 300 -400 150 L 50 50 1 1 P
X Pin_b19 B19 300 -500 150 L 50 50 1 1 P
X Pin_b2 B2 300 1200 150 L 50 50 1 1 P
X Pin_b20 B20 300 -600 150 L 50 50 1 1 P
X Pin_b21 B21 300 -700 150 L 50 50 1 1 P
X Pin_b22 B22 300 -800 150 L 50 50 1 1 P
X Pin_b23 B23 300 -900 150 L 50 50 1 1 P
X Pin_b24 B24 300 -1000 150 L 50 50 1 1 P
X Pin_b25 B25 300 -1100 150 L 50 50 1 1 P
X Pin_b26 B26 300 -1200 150 L 50 50 1 1 P
X Pin_b27 B27 300 -1300 150 L 50 50 1 1 P
X Pin_b28 B28 300 -1400 150 L 50 50 1 1 P
X Pin_b3 B3 300 1100 150 L 50 50 1 1 P
X Pin_b4 B4 300 1000 150 L 50 50 1 1 P
X Pin_b6 B6 300 800 150 L 50 50 1 1 P
X Pin_b7 B7 300 700 150 L 50 50 1 1 P
X Pin_b8 B8 300 600 150 L 50 50 1 1 P
X Pin_b9 B9 300 500 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+12V
#
DEF power_+12V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+12V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+9V
#
DEF power_+9V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+9V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +9V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

6867
pcb/zx-tsid.kicad_pcb Normal file
View File

File diff suppressed because it is too large Load Diff

249
pcb/zx-tsid.pro Normal file
View File

@ -0,0 +1,249 @@
update=16/05/2020 10:51:25
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.4
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=E:/ws/kicad-lib/mykicadws.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

1869
pcb/zx-tsid.sch Normal file
View File

File diff suppressed because it is too large Load Diff