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add pcb rev.B

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This commit is contained in:
UzixLS
2022-02-19 20:02:42 +03:00
parent 0a88cf8a76
commit fd4794a9e7
7 changed files with 40190 additions and 6 deletions
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3
Makefile
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@ -1,11 +1,12 @@
OUTDIR=out_new OUTDIR=out_new
REV=A REV=B
.PHONY: all build_rev clean pipeline pipeline_sof .PHONY: all build_rev clean pipeline pipeline_sof
all: all:
mkdir -p ${OUTDIR}/ mkdir -p ${OUTDIR}/
${MAKE} REV=A build_rev ${MAKE} REV=A build_rev
${MAKE} REV=B build_rev
build_rev: build_rev:
${MAKE} REV=${REV} -C rom_src/ clean all ${MAKE} REV=${REV} -C rom_src/ clean all

9
README.md
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@ -47,5 +47,10 @@ Sizif have preinstalled esxDOS firmware, which provides ability to load TAP, TRD
### Changelog & current status ### Changelog & current status
* Rev.A - first release. Please note the [errata](pcb/rev.A/ERRATA.txt). * Rev.A - first release. Please note the [errata](pcb/rev.A/ERRATA.txt).
* Rev.B:
**Work in progress!** * fixed all rev.A issues
* fixed "jailbars" on video output
* 0805 footprints replaced with 0603
* tape input moved slightly away to not to interfere with wide AV jack
* 3.5 jacks replaced with THT variant for better reliability
* changed ps/2 header orientation

191
fpga/syn/rev_B.qsf Normal file
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@ -0,0 +1,191 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# rev_B_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T100C8
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:57:09 NOVEMBER 08, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32
set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8
set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name POWER_USE_PVA OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rd
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_wr
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_m1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_mreq
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rfsh
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rstcpu
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_nmi
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS4
set_location_assignment PIN_1 -to va[10]
set_location_assignment PIN_2 -to va[5]
set_location_assignment PIN_3 -to vd[4]
set_location_assignment PIN_4 -to va[12]
set_location_assignment PIN_5 -to va[11]
set_location_assignment PIN_20 -to ps2_clk
set_location_assignment PIN_21 -to ps2_dat
set_location_assignment PIN_22 -to reserv[0]
set_location_assignment PIN_23 -to reserv[1]
set_location_assignment PIN_24 -to snd_l
set_location_assignment PIN_25 -to snd_r
set_location_assignment PIN_26 -to composite[7]
set_location_assignment PIN_27 -to composite[6]
set_location_assignment PIN_28 -to composite[5]
set_location_assignment PIN_29 -to composite[4]
set_location_assignment PIN_34 -to composite[3]
set_location_assignment PIN_35 -to composite[2]
set_location_assignment PIN_36 -to composite[1]
set_location_assignment PIN_37 -to composite[0]
set_location_assignment PIN_38 -to sd_cd
set_location_assignment PIN_39 -to sd_cs
set_location_assignment PIN_40 -to sd_miso_tape_in
set_location_assignment PIN_41 -to sd_sck
set_location_assignment PIN_42 -to sd_mosi_tape_out
set_location_assignment PIN_47 -to vd[2]
set_location_assignment PIN_48 -to vd[0]
set_location_assignment PIN_49 -to vd[7]
set_location_assignment PIN_50 -to vd[1]
set_location_assignment PIN_51 -to vd[6]
set_location_assignment PIN_52 -to n_mreq
set_location_assignment PIN_54 -to n_int
set_location_assignment PIN_55 -to n_nmi
set_location_assignment PIN_56 -to va[14]
set_location_assignment PIN_57 -to n_vrd
set_location_assignment PIN_65 -to va[16]
set_location_assignment PIN_68 -to va[18]
set_location_assignment PIN_69 -to va[15]
set_location_assignment PIN_70 -to va[13]
set_location_assignment PIN_71 -to n_vwr
set_location_assignment PIN_72 -to va[17]
set_location_assignment PIN_73 -to clkcpu
set_location_assignment PIN_74 -to n_wr
set_location_assignment PIN_75 -to n_rd
set_location_assignment PIN_76 -to a[14]
set_location_assignment PIN_77 -to a[15]
set_location_assignment PIN_78 -to a[13]
set_location_assignment PIN_79 -to vd[5]
set_location_assignment PIN_84 -to n_rstcpu
set_location_assignment PIN_85 -to n_m1
set_location_assignment PIN_86 -to n_rfsh
set_location_assignment PIN_87 -to vd[3]
set_location_assignment PIN_88 -to va[0]
set_location_assignment PIN_89 -to va[1]
set_location_assignment PIN_90 -to va[2]
set_location_assignment PIN_91 -to va[3]
set_location_assignment PIN_92 -to va[4]
set_location_assignment PIN_97 -to va[6]
set_location_assignment PIN_98 -to va[7]
set_location_assignment PIN_99 -to va[8]
set_location_assignment PIN_100 -to va[9]
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_location_assignment PIN_53 -to n_iorq
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output/stp1.stp
set_global_assignment -name RTLV_GROUP_RELATED_NODES OFF
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_miso_tape_in
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_iorq
set_location_assignment PIN_10 -to clk_in
set_global_assignment -name SLD_FILE "/home/uzix/zx-sizif-xxs/fpga/rtl/stp2_auto_stripped.stp"
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[7]
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv
set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v
set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd
set_global_assignment -name VERILOG_INCLUDE_FILE ../rtl/ps2_codes.vh
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/mixer.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/soundrive.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/screen.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ports.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/magic.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/divmmc.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/cpucontrol.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/memcontrol.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/turbosound.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ulaplus.sv
set_global_assignment -name VERILOG_FILE ../rtl/ps2.v
set_global_assignment -name VERILOG_FILE ../rtl/ps2_rxtx.v
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/common.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/top.sv
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name CDF_FILE output/zx_ula.cdf
set_global_assignment -name QIP_FILE ip/pll.qip
set_global_assignment -name QIP_FILE ip/rom2ram.qip
set_global_assignment -name QIP_FILE ip/asmi.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VERILOG_MACRO "REV_B=<None>"

6
fpga/syn/zx_ula.qpf
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@ -18,14 +18,14 @@
# #
# Quartus II 32-bit # Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 20:26:38 November 08, 2021 # Date created = 14:48:32 February 06, 2022
# #
# -------------------------------------------------------------------------- # # -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0" QUARTUS_VERSION = "13.0"
DATE = "20:26:38 November 08, 2021" DATE = "14:48:32 February 06, 2022"
# Revisions # Revisions
PROJECT_REVISION = "rev_A"
PROJECT_REVISION = "rev_B" PROJECT_REVISION = "rev_B"
PROJECT_REVISION = "rev_A"

29969
pcb/rev.B/sizif-xxs.kicad_pcb Normal file
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File diff suppressed because it is too large Load Diff

473
pcb/rev.B/sizif-xxs.kicad_pro Normal file
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@ -0,0 +1,473 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 3.0,
"height": 3.0,
"width": 3.0
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 0.7999999999999999,
"silk_text_size_v": 0.7999999999999999,
"silk_text_thickness": 0.12,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.254
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "warning",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.19999999999999998,
"min_copper_edge_clearance": 0.19999999999999998,
"min_hole_clearance": 0.19999999999999998,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.44999999999999996
},
"track_widths": [
0.0,
0.2,
0.5,
1.0,
2.0,
3.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "sizif-xxs.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.1999,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.5,
"via_drill": 0.3,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.1999,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Hipower",
"nets": [],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 1.0,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.1999,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "power",
"nets": [
"+3V3",
"+5V",
"GND"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 0
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"drawing": {
"default_bus_thickness": 12.0,
"default_junction_size": 40.0,
"default_line_thickness": 6.0,
"default_text_size": 39.0,
"default_wire_thickness": 6.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.3
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 0
},
"net_format_name": "Pcbnew",
"ngspice": {
"meta": {
"version": 0
},
"model_mode": 0
},
"page_layout_descr_file": "${MYLIBPATH}/mykicadws2.kicad_wks",
"plot_directory": "out/",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"1dc075ee-445f-4b49-a326-dd943e04c837",
""
]
],
"text_variables": {}
}

9545
pcb/rev.B/sizif-xxs.kicad_sch Normal file
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