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UzixLS
640
fpga/rtl/top.sv
640
fpga/rtl/top.sv
@ -1,42 +1,42 @@
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import common::*;
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module zx_ula(
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input clk_in,
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input clk_in,
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output reg n_rstcpu,
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output reg clkcpu,
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output reg n_rstcpu,
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output reg clkcpu,
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inout [18:0] va,
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inout [7:0] vd,
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input [15:13] a,
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inout [18:0] va,
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inout [7:0] vd,
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input [15:13] a,
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output n_vrd,
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output n_vwr,
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output n_vrd,
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output n_vwr,
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input n_rd,
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input n_wr,
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input n_mreq,
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input n_iorq,
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input n_m1,
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input n_rfsh,
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output reg n_int,
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output n_nmi,
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input n_rd,
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input n_wr,
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input n_mreq,
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input n_iorq,
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input n_m1,
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input n_rfsh,
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output reg n_int,
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output n_nmi,
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output reg [5:0] luma,
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output reg [2:0] chroma,
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output reg csync,
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output reg [5:0] luma,
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output reg [2:0] chroma,
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output reg csync,
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output snd_l,
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output snd_r,
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output snd_l,
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output snd_r,
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inout reg ps2_clk,
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inout reg ps2_dat,
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inout reg ps2_clk,
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inout reg ps2_dat,
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input sd_cd,
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input sd_miso_tape_in,
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output sd_mosi,
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output reg sd_sck,
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output reg sd_cs
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input sd_cd,
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input sd_miso_tape_in,
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output sd_mosi,
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output reg sd_sck,
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output reg sd_cs
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);
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/* CLOCK */
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@ -58,22 +58,22 @@ wire screen_fetch, screen_fetch_next;
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cpu_bus bus();
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reg bus_memreq, bus_ioreq;
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always @(posedge clk28 or negedge rst_n) begin
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if (!rst_n) begin
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bus_ioreq <= 0;
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bus_memreq <= 0;
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end
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else if (!screen_fetch && !screen_fetch_next) begin
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bus.a_reg <= bus.a;
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bus.d_reg <= bus.d;
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bus_ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1;
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bus_memreq <= n_mreq == 1'b0;
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end
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else begin
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if (n_iorq)
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bus_ioreq <= 0;
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if (n_mreq)
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bus_memreq <= 0;
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end
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if (!rst_n) begin
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bus_ioreq <= 0;
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bus_memreq <= 0;
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end
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else if (!screen_fetch && !screen_fetch_next) begin
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bus.a_reg <= bus.a;
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bus.d_reg <= bus.d;
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bus_ioreq <= n_iorq == 1'b0 && n_m1 == 1'b1;
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bus_memreq <= n_mreq == 1'b0;
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end
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else begin
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if (n_iorq)
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bus_ioreq <= 0;
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if (n_mreq)
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bus_memreq <= 0;
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end
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end
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assign bus.a = {a[15:13], va[12:0]};
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assign bus.d = vd;
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@ -94,22 +94,22 @@ reg key_magic, key_reset, pause;
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wire usrrst_n = ~key_reset;
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reg joy_up, joy_down, joy_left, joy_right, joy_fire;
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ps2 #(.CLK_FREQ(28_000_000)) ps2_0(
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.rst_n(rst_n),
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.clk(clk28),
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.ps2_clk_in(ps2_clk),
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.ps2_dat_in(ps2_dat),
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.ps2_clk_out(ps2_clk_out),
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.ps2_dat_out(ps2_dat_out),
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.zxkb_addr(bus.a_reg[15:8]),
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.zxkb_data(ps2_kd),
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.key_magic(key_magic),
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.key_reset(key_reset),
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.key_pause(pause),
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.joy_up(joy_up),
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.joy_down(joy_down),
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.joy_left(joy_left),
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.joy_right(joy_right),
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.joy_fire(joy_fire)
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.rst_n(rst_n),
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.clk(clk28),
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.ps2_clk_in(ps2_clk),
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.ps2_dat_in(ps2_dat),
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.ps2_clk_out(ps2_clk_out),
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.ps2_dat_out(ps2_dat_out),
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.zxkb_addr(bus.a_reg[15:8]),
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.zxkb_data(ps2_kd),
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.key_magic(key_magic),
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.key_reset(key_reset),
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.key_pause(pause),
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.joy_up(joy_up),
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.joy_down(joy_down),
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.joy_left(joy_left),
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.joy_right(joy_right),
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.joy_fire(joy_fire)
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);
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assign ps2_clk = (ps2_clk_out == 0)? 1'b0 : 1'bz;
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assign ps2_dat = (ps2_dat_out == 0)? 1'b0 : 1'bz;
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@ -131,58 +131,58 @@ wire [7:0] attr_next;
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wire [8:0] vc, hc;
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wire clk14, clk7, clk35, ck14, ck7, ck35;
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screen screen0(
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.rst_n(rst_n),
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.clk28(clk28),
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.rst_n(rst_n),
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.clk28(clk28),
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.bus(bus),
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.addr(screen_addr),
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.bus(bus),
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.addr(screen_addr),
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.clkwait(clkwait),
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.timings(timings),
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.border(screen_border),
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.clkwait(clkwait),
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.timings(timings),
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.border(screen_border),
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.r(r),
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.g(g),
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.b(b),
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.csync(csync),
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.vsync(),
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.hsync(hsync),
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.r(r),
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.g(g),
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.b(b),
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.csync(csync),
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.vsync(),
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.hsync(hsync),
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.blink(blink),
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.fetch(screen_fetch),
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.fetch_next(screen_fetch_next),
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.loading(screen_loading),
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.attr_next(attr_next),
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.blink(blink),
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.fetch(screen_fetch),
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.fetch_next(screen_fetch_next),
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.loading(screen_loading),
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.attr_next(attr_next),
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.up_en(up_en),
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.up_ink_addr(up_ink_addr),
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.up_paper_addr(up_paper_addr),
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.up_ink(up_ink),
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.up_paper(up_paper),
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.up_en(up_en),
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.up_ink_addr(up_ink_addr),
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.up_paper_addr(up_paper_addr),
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.up_ink(up_ink),
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.up_paper(up_paper),
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.vc_out(vc),
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.hc_out(hc),
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.clk14(clk14),
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.clk7(clk7),
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.clk35(clk35),
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.ck14(ck14),
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.ck7(ck7),
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.ck35(ck35)
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.vc_out(vc),
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.hc_out(hc),
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.clk14(clk14),
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.clk7(clk7),
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.clk35(clk35),
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.ck14(ck14),
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.ck7(ck7),
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.ck35(ck35)
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);
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/* VIDEO OUTPUT */
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always @*
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luma <= {g[2], r[2], b[2], g[1], r[1], b[1]};
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luma <= {g[2], r[2], b[2], g[1], r[1], b[1]};
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reg [2:0] chroma0;
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chroma_gen #(.CLK_FREQ(40_000_000)) chroma_gen1(
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.cg_clock(clk40),
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.cg_rgb({g[2],r[2],b[2]}),
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.cg_hsync(hsync),
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.cg_enable(1'b1),
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.cg_pnsel(1'b0),
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.cg_out(chroma0)
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.cg_clock(clk40),
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.cg_rgb({g[2],r[2],b[2]}),
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.cg_hsync(hsync),
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.cg_enable(1'b1),
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.cg_pnsel(1'b0),
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.cg_out(chroma0)
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);
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assign chroma[0] = (chroma0[2]|chroma0[1])? chroma0[0] : 1'bz;
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assign chroma[1] = (chroma0[2]|chroma0[1])? chroma0[0] : 1'bz;
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@ -196,31 +196,31 @@ logic n_int_next;
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wire snow, clkcpu_ck;
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wire init_done;
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cpucontrol cpucontrol0(
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.rst_n(rst_n & usrrst_n),
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.clk28(clk28),
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.clk14(clk14),
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.clk7(clk7),
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.clk35(clk35),
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.rst_n(rst_n & usrrst_n),
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.clk28(clk28),
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.clk14(clk14),
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.clk7(clk7),
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.clk35(clk35),
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.bus(bus),
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.bus(bus),
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.vc(vc),
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.hc(hc),
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.rampage128(rampage128),
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.screen_loading(screen_loading),
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.turbo(turbo),
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.timings(timings),
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.pause(pause),
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.ext_wait_cycle(div_wait || up_en),
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.init_done_in(init_done),
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.vc(vc),
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.hc(hc),
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.rampage128(rampage128),
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.screen_loading(screen_loading),
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.turbo(turbo),
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.timings(timings),
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.pause(pause),
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.ext_wait_cycle(div_wait || up_en),
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.init_done_in(init_done),
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.n_rstcpu(n_rstcpu),
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.clkcpu(clkcpu),
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.clkcpu_ck(clkcpu_ck),
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.clkwait(clkwait),
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.n_int(n_int),
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.n_int_next(n_int_next),
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.snow(snow)
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.n_rstcpu(n_rstcpu),
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.clkcpu(clkcpu),
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.clkcpu_ck(clkcpu_ck),
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.clkwait(clkwait),
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.n_int(n_int),
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.n_int_next(n_int_next),
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.snow(snow)
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);
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@ -230,29 +230,29 @@ wire magic_active_next;
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reg n_nmi0;
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reg extlock, joy_sinclair, rom_plus3, rom_alt48, ay_abc, ay_mono;
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magic magic0(
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.rst_n(rst_n & usrrst_n),
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.clk28(clk28),
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.rst_n(rst_n & usrrst_n),
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.clk28(clk28),
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.bus(bus),
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.n_int(n_int),
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.n_int_next(n_int_next),
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.n_nmi(n_nmi),
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.bus(bus),
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.n_int(n_int),
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.n_int_next(n_int_next),
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.n_nmi(n_nmi),
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.magic_button(key_magic),
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.magic_button(key_magic),
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.magic_mode(magic_mode),
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.magic_map(magic_map),
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.magic_active_next(magic_active_next),
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.magic_mode(magic_mode),
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.magic_map(magic_map),
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.magic_active_next(magic_active_next),
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.extlock(extlock),
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.magic_beeper(magic_beeper),
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.timings(timings),
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.turbo(turbo),
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.joy_sinclair(joy_sinclair),
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.rom_plus3(rom_plus3),
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.rom_alt48(rom_alt48),
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.ay_abc(ay_abc),
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.ay_mono(ay_mono)
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.extlock(extlock),
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.magic_beeper(magic_beeper),
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.timings(timings),
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.turbo(turbo),
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.joy_sinclair(joy_sinclair),
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.rom_plus3(rom_plus3),
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.rom_alt48(rom_alt48),
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.ay_abc(ay_abc),
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.ay_mono(ay_mono)
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);
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@ -267,38 +267,38 @@ reg [2:0] port_1ffd;
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reg port_dffd_d3;
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reg port_dffd_d4;
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ports ports0 (
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.rst_n(rst_n & usrrst_n),
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.clk28(clk28),
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.rst_n(rst_n & usrrst_n),
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.clk28(clk28),
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.bus(bus),
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.d_out(ports_dout),
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.d_out_active(ports_dout_active),
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.bus(bus),
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.d_out(ports_dout),
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.d_out_active(ports_dout_active),
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.en_128k(1'b1),
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.en_plus3(rom_plus3),
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.en_profi(!extlock),
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.en_kempston(!joy_sinclair),
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.en_sinclair(joy_sinclair),
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.en_128k(1'b1),
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.en_plus3(rom_plus3),
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.en_profi(!extlock),
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.en_kempston(!joy_sinclair),
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.en_sinclair(joy_sinclair),
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.clkcpu_ck(clkcpu_ck),
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.timings(timings),
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.screen_loading(screen_loading),
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.attr_next(attr_next),
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.kd(ps2_kd),
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.kempston_data({3'b000, joy_fire, joy_up, joy_down, joy_left, joy_right}),
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.magic_active_next(magic_active_next),
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.tape_in(sd_miso_tape_in),
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.clkcpu_ck(clkcpu_ck),
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.timings(timings),
|
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.screen_loading(screen_loading),
|
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.attr_next(attr_next),
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.kd(ps2_kd),
|
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.kempston_data({3'b000, joy_fire, joy_up, joy_down, joy_left, joy_right}),
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.magic_active_next(magic_active_next),
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.tape_in(sd_miso_tape_in),
|
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|
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.tape_out(tape_out),
|
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.beeper(beeper),
|
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.border(border),
|
||||
.screen_page(screenpage),
|
||||
.rompage128(rompage128),
|
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.rampage128(rampage128),
|
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.rampage_ext(rampage_ext),
|
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.port_1ffd(port_1ffd),
|
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.port_dffd_d3(port_dffd_d3),
|
||||
.port_dffd_d4(port_dffd_d4)
|
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.tape_out(tape_out),
|
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.beeper(beeper),
|
||||
.border(border),
|
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.screen_page(screenpage),
|
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.rompage128(rompage128),
|
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.rampage128(rampage128),
|
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.rampage_ext(rampage_ext),
|
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.port_1ffd(port_1ffd),
|
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.port_dffd_d3(port_dffd_d3),
|
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.port_dffd_d4(port_dffd_d4)
|
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);
|
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|
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|
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@ -307,67 +307,67 @@ wire turbosound_dout_active;
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wire [7:0] turbosound_dout;
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wire [7:0] ay_a0, ay_b0, ay_c0, ay_a1, ay_b1, ay_c1;
|
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turbosound turbosound0(
|
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.rst_n(rst_n & usrrst_n),
|
||||
.clk28(clk28),
|
||||
.ck35(ck35),
|
||||
.en(1'b1),
|
||||
|
||||
.bus(bus),
|
||||
.d_out(turbosound_dout),
|
||||
.d_out_active(turbosound_dout_active),
|
||||
|
||||
.pause(pause),
|
||||
|
||||
.ay_a0(ay_a0),
|
||||
.ay_b0(ay_b0),
|
||||
.ay_c0(ay_c0),
|
||||
.ay_a1(ay_a1),
|
||||
.ay_b1(ay_b1),
|
||||
.ay_c1(ay_c1)
|
||||
.rst_n(rst_n & usrrst_n),
|
||||
.clk28(clk28),
|
||||
.ck35(ck35),
|
||||
.en(1'b1),
|
||||
|
||||
.bus(bus),
|
||||
.d_out(turbosound_dout),
|
||||
.d_out_active(turbosound_dout_active),
|
||||
|
||||
.pause(pause),
|
||||
|
||||
.ay_a0(ay_a0),
|
||||
.ay_b0(ay_b0),
|
||||
.ay_c0(ay_c0),
|
||||
.ay_a1(ay_a1),
|
||||
.ay_b1(ay_b1),
|
||||
.ay_c1(ay_c1)
|
||||
);
|
||||
|
||||
|
||||
/* COVOX & SOUNDRIVE */
|
||||
reg [7:0] soundrive_l0, soundrive_l1, soundrive_r0, soundrive_r1;
|
||||
soundrive soundrive0(
|
||||
.rst_n(rst_n & usrrst_n),
|
||||
.clk28(clk28),
|
||||
.en_covox(!extlock),
|
||||
.en_soundrive(!extlock),
|
||||
.rst_n(rst_n & usrrst_n),
|
||||
.clk28(clk28),
|
||||
.en_covox(!extlock),
|
||||
.en_soundrive(!extlock),
|
||||
|
||||
.bus(bus),
|
||||
.bus(bus),
|
||||
|
||||
.ch_l0(soundrive_l0),
|
||||
.ch_l1(soundrive_l1),
|
||||
.ch_r0(soundrive_r0),
|
||||
.ch_r1(soundrive_r1)
|
||||
.ch_l0(soundrive_l0),
|
||||
.ch_l1(soundrive_l1),
|
||||
.ch_r0(soundrive_r0),
|
||||
.ch_r1(soundrive_r1)
|
||||
);
|
||||
|
||||
|
||||
/* SOUND MIXER */
|
||||
mixer mixer0(
|
||||
.rst_n(rst_n),
|
||||
.clk28(clk28),
|
||||
.rst_n(rst_n),
|
||||
.clk28(clk28),
|
||||
|
||||
.beeper(beeper),
|
||||
.tape_out(tape_out),
|
||||
.tape_in(sd_miso_tape_in),
|
||||
.ay_a0(ay_a0),
|
||||
.ay_b0(ay_b0),
|
||||
.ay_c0(ay_c0),
|
||||
.ay_a1(ay_a1),
|
||||
.ay_b1(ay_b1),
|
||||
.ay_c1(ay_c1),
|
||||
.sd_l0(soundrive_l0),
|
||||
.sd_l1(soundrive_l1),
|
||||
.sd_r0(soundrive_r0),
|
||||
.sd_r1(soundrive_r1),
|
||||
.beeper(beeper),
|
||||
.tape_out(tape_out),
|
||||
.tape_in(sd_miso_tape_in),
|
||||
.ay_a0(ay_a0),
|
||||
.ay_b0(ay_b0),
|
||||
.ay_c0(ay_c0),
|
||||
.ay_a1(ay_a1),
|
||||
.ay_b1(ay_b1),
|
||||
.ay_c1(ay_c1),
|
||||
.sd_l0(soundrive_l0),
|
||||
.sd_l1(soundrive_l1),
|
||||
.sd_r0(soundrive_r0),
|
||||
.sd_r1(soundrive_r1),
|
||||
|
||||
.ay_abc(ay_abc),
|
||||
.ay_mono(ay_mono),
|
||||
.ay_abc(ay_abc),
|
||||
.ay_mono(ay_mono),
|
||||
|
||||
.dac_l(snd_l),
|
||||
.dac_r(snd_r)
|
||||
.dac_l(snd_l),
|
||||
.dac_r(snd_r)
|
||||
);
|
||||
|
||||
|
||||
@ -377,32 +377,32 @@ wire [7:0] div_dout;
|
||||
reg [3:0] div_page;
|
||||
reg sd_mosi0;
|
||||
divmmc divmmc0(
|
||||
.rst_n(rst_n & usrrst_n),
|
||||
.clk28(clk28),
|
||||
.ck14(ck14),
|
||||
.ck7(ck7),
|
||||
.en(!extlock),
|
||||
.rst_n(rst_n & usrrst_n),
|
||||
.clk28(clk28),
|
||||
.ck14(ck14),
|
||||
.ck7(ck7),
|
||||
.en(!extlock),
|
||||
|
||||
.bus(bus),
|
||||
.d_out(div_dout),
|
||||
.d_out_active(div_dout_active),
|
||||
.bus(bus),
|
||||
.d_out(div_dout),
|
||||
.d_out_active(div_dout_active),
|
||||
|
||||
.sd_cd(sd_cd),
|
||||
.sd_miso(sd_miso_tape_in),
|
||||
.sd_mosi(sd_mosi0),
|
||||
.sd_sck(sd_sck),
|
||||
.sd_cs(sd_cs),
|
||||
|
||||
.port_dffd_d4(port_dffd_d4),
|
||||
.port_1ffd_d0(port_1ffd[0]),
|
||||
.magic_mode(magic_mode),
|
||||
.magic_map(magic_map),
|
||||
.sd_cd(sd_cd),
|
||||
.sd_miso(sd_miso_tape_in),
|
||||
.sd_mosi(sd_mosi0),
|
||||
.sd_sck(sd_sck),
|
||||
.sd_cs(sd_cs),
|
||||
|
||||
.div_page(div_page),
|
||||
.div_map(div_map),
|
||||
.div_ram(div_ram),
|
||||
.div_ramwr_mask(div_ramwr_mask),
|
||||
.div_wait(div_wait)
|
||||
.port_dffd_d4(port_dffd_d4),
|
||||
.port_1ffd_d0(port_1ffd[0]),
|
||||
.magic_mode(magic_mode),
|
||||
.magic_map(magic_map),
|
||||
|
||||
.div_page(div_page),
|
||||
.div_map(div_map),
|
||||
.div_ram(div_ram),
|
||||
.div_ramwr_mask(div_ramwr_mask),
|
||||
.div_wait(div_wait)
|
||||
);
|
||||
///assign sd_mosi = (sd_cs == 1'b0)? sd_mosi0 : tape_out;
|
||||
assign sd_mosi = sd_mosi0;
|
||||
@ -412,19 +412,19 @@ assign sd_mosi = sd_mosi0;
|
||||
wire up_dout_active;
|
||||
wire [7:0] up_dout;
|
||||
ulaplus ulaplus0(
|
||||
.rst_n(rst_n & usrrst_n),
|
||||
.clk28(clk28),
|
||||
.en(!extlock),
|
||||
|
||||
.bus(bus),
|
||||
.d_out(up_dout),
|
||||
.d_out_active(up_dout_active),
|
||||
|
||||
.active(up_en),
|
||||
.ink_addr(up_ink_addr),
|
||||
.paper_addr(up_paper_addr),
|
||||
.ink(up_ink),
|
||||
.paper(up_paper)
|
||||
.rst_n(rst_n & usrrst_n),
|
||||
.clk28(clk28),
|
||||
.en(!extlock),
|
||||
|
||||
.bus(bus),
|
||||
.d_out(up_dout),
|
||||
.d_out_active(up_dout_active),
|
||||
|
||||
.active(up_en),
|
||||
.ink_addr(up_ink_addr),
|
||||
.paper_addr(up_paper_addr),
|
||||
.ink(up_ink),
|
||||
.paper(up_paper)
|
||||
);
|
||||
|
||||
|
||||
@ -439,54 +439,54 @@ wire rom2ram_active;
|
||||
assign init_done = !rom2ram_active;
|
||||
reg [1:0] rom2ram_init;
|
||||
always @(posedge rom2ram_clk or negedge rst_n) begin
|
||||
if (!rst_n)
|
||||
rom2ram_init <= 0;
|
||||
else if (rom2ram_init != 3)
|
||||
rom2ram_init <= rom2ram_init + 1'b1;
|
||||
if (!rst_n)
|
||||
rom2ram_init <= 0;
|
||||
else if (rom2ram_init != 3)
|
||||
rom2ram_init <= rom2ram_init + 1'b1;
|
||||
end
|
||||
rom2ram rom2ram0(
|
||||
.clock(rom2ram_clk),
|
||||
.init(rom2ram_init == 2),
|
||||
.datain(rom2ram_datain),
|
||||
.rom_data_ready(rom2ram_rom_data_ready),
|
||||
|
||||
.init_busy(rom2ram_active),
|
||||
.rom_address(rom2ram_rom_address),
|
||||
.rom_rden(rom2ram_rom_rden),
|
||||
.ram_wren(rom2ram_ram_wren),
|
||||
.ram_address(rom2ram_ram_address),
|
||||
.dataout(rom2ram_dataout)
|
||||
.clock(rom2ram_clk),
|
||||
.init(rom2ram_init == 2),
|
||||
.datain(rom2ram_datain),
|
||||
.rom_data_ready(rom2ram_rom_data_ready),
|
||||
|
||||
.init_busy(rom2ram_active),
|
||||
.rom_address(rom2ram_rom_address),
|
||||
.rom_rden(rom2ram_rom_rden),
|
||||
.ram_wren(rom2ram_ram_wren),
|
||||
.ram_address(rom2ram_ram_address),
|
||||
.dataout(rom2ram_dataout)
|
||||
);
|
||||
|
||||
localparam ROM_OFFSET = 24'h13256;
|
||||
wire [23:0] asmi_addr = ROM_OFFSET + rom2ram_rom_address;
|
||||
asmi asmi0(
|
||||
.clkin(rom2ram_clk),
|
||||
.read(rom2ram_rom_rden),
|
||||
.rden(rom2ram_active),
|
||||
.addr(asmi_addr),
|
||||
.reset(!rst_n),
|
||||
|
||||
.dataout(rom2ram_datain),
|
||||
.busy(),
|
||||
.data_valid(rom2ram_rom_data_ready)
|
||||
.clkin(rom2ram_clk),
|
||||
.read(rom2ram_rom_rden),
|
||||
.rden(rom2ram_active),
|
||||
.addr(asmi_addr),
|
||||
.reset(!rst_n),
|
||||
|
||||
.dataout(rom2ram_datain),
|
||||
.busy(),
|
||||
.data_valid(rom2ram_rom_data_ready)
|
||||
);
|
||||
|
||||
|
||||
/* MEMORY CONTROLLER */
|
||||
reg romreq, ramreq, ramreq_wr;
|
||||
always @(posedge clk28 or negedge rst_n) begin
|
||||
if (!rst_n) begin
|
||||
romreq = 1'b0;
|
||||
ramreq = 1'b0;
|
||||
ramreq_wr = 1'b0;
|
||||
end
|
||||
else begin
|
||||
romreq = bus.mreq && !bus.rfsh && bus.a[14] == 0 && bus.a[15] == 0 &&
|
||||
(magic_map || (!div_ram && div_map) || (!div_ram && !port_dffd_d4 && !port_1ffd[0]));
|
||||
ramreq = bus.mreq && !bus.rfsh && !romreq;
|
||||
ramreq_wr = ramreq && bus.wr && div_ramwr_mask == 0;
|
||||
end
|
||||
if (!rst_n) begin
|
||||
romreq = 1'b0;
|
||||
ramreq = 1'b0;
|
||||
ramreq_wr = 1'b0;
|
||||
end
|
||||
else begin
|
||||
romreq = bus.mreq && !bus.rfsh && bus.a[14] == 0 && bus.a[15] == 0 &&
|
||||
(magic_map || (!div_ram && div_map) || (!div_ram && !port_dffd_d4 && !port_1ffd[0]));
|
||||
ramreq = bus.mreq && !bus.rfsh && !romreq;
|
||||
ramreq_wr = ramreq && bus.wr && div_ramwr_mask == 0;
|
||||
end
|
||||
end
|
||||
|
||||
assign n_vrd = ((((ramreq || romreq) && bus.rd) || screen_fetch) && !rom2ram_ram_wren)? 1'b0 : 1'b1;
|
||||
@ -498,53 +498,53 @@ assign n_vwr = ((ramreq_wr && bus.wr && !screen_fetch) || rom2ram_ram_wren)? 1'b
|
||||
* 01xxxx 128Kb of divmmc memory
|
||||
* 10xxxx 128Kb of extended ram (via port dffd)
|
||||
* 11xxxx 128Kb of main ram
|
||||
*/
|
||||
*/
|
||||
|
||||
reg [18:13] ram_a;
|
||||
always @(posedge clk28) begin
|
||||
ram_a <=
|
||||
magic_map & bus.a[15] & bus.a[14]? {2'b00, 3'b111, bus.a[13]} :
|
||||
magic_map? {3'b111, screenpage, bus.a[14:13]} :
|
||||
div_map & ~bus.a[14] & ~bus.a[15] & bus.a[13]? {2'b01, div_page} :
|
||||
div_map & ~bus.a[14] & ~bus.a[15]? {2'b01, 4'b0011} :
|
||||
port_dffd_d3 & bus.a[15]? {2'b11, bus.a[14], bus.a[15], bus.a[14], bus.a[13]} :
|
||||
port_dffd_d3 & bus.a[14]? {1'b1, ~rampage_ext[0], rampage128, bus.a[13]} :
|
||||
(port_1ffd[2] == 1'b0 && port_1ffd[0] == 1'b1)? {2'b11, port_1ffd[1], bus.a[15], bus.a[14], bus.a[13]} :
|
||||
(port_1ffd == 3'b101)? {2'b11, ~(bus.a[15] & bus.a[14]), bus.a[15], bus.a[14]} :
|
||||
(port_1ffd == 3'b111)? {2'b11, ~(bus.a[15] & bus.a[14]), (bus.a[15] | bus.a[14]), bus.a[14]} :
|
||||
bus.a[15] & bus.a[14]? {1'b1, ~rampage_ext[0], rampage128, bus.a[13]} :
|
||||
{2'b11, bus.a[14], bus.a[15], bus.a[14], bus.a[13]} ;
|
||||
ram_a <=
|
||||
magic_map & bus.a[15] & bus.a[14]? {2'b00, 3'b111, bus.a[13]} :
|
||||
magic_map? {3'b111, screenpage, bus.a[14:13]} :
|
||||
div_map & ~bus.a[14] & ~bus.a[15] & bus.a[13]? {2'b01, div_page} :
|
||||
div_map & ~bus.a[14] & ~bus.a[15]? {2'b01, 4'b0011} :
|
||||
port_dffd_d3 & bus.a[15]? {2'b11, bus.a[14], bus.a[15], bus.a[14], bus.a[13]} :
|
||||
port_dffd_d3 & bus.a[14]? {1'b1, ~rampage_ext[0], rampage128, bus.a[13]} :
|
||||
(port_1ffd[2] == 1'b0 && port_1ffd[0] == 1'b1)? {2'b11, port_1ffd[1], bus.a[15], bus.a[14], bus.a[13]} :
|
||||
(port_1ffd == 3'b101)? {2'b11, ~(bus.a[15] & bus.a[14]), bus.a[15], bus.a[14]} :
|
||||
(port_1ffd == 3'b111)? {2'b11, ~(bus.a[15] & bus.a[14]), (bus.a[15] | bus.a[14]), bus.a[14]} :
|
||||
bus.a[15] & bus.a[14]? {1'b1, ~rampage_ext[0], rampage128, bus.a[13]} :
|
||||
{2'b11, bus.a[14], bus.a[15], bus.a[14], bus.a[13]} ;
|
||||
end
|
||||
|
||||
|
||||
reg [16:14] rom_a;
|
||||
always @(posedge clk28) begin
|
||||
rom_a <=
|
||||
magic_map? 3'd2 :
|
||||
div_map? 3'd3 :
|
||||
(rom_plus3 && port_1ffd[2] == 1'b0 && rompage128 == 1'b0)? 3'd4 :
|
||||
(rom_plus3 && port_1ffd[2] == 1'b0 && rompage128 == 1'b1)? 3'd5 :
|
||||
(rom_plus3 && port_1ffd[2] == 1'b1 && rompage128 == 1'b0)? 3'd6 :
|
||||
(rompage128 == 1'b1 && rom_alt48 == 1'b1)? 3'd7 :
|
||||
(rompage128 == 1'b1)? 3'd1 :
|
||||
3'd0;
|
||||
rom_a <=
|
||||
magic_map? 3'd2 :
|
||||
div_map? 3'd3 :
|
||||
(rom_plus3 && port_1ffd[2] == 1'b0 && rompage128 == 1'b0)? 3'd4 :
|
||||
(rom_plus3 && port_1ffd[2] == 1'b0 && rompage128 == 1'b1)? 3'd5 :
|
||||
(rom_plus3 && port_1ffd[2] == 1'b1 && rompage128 == 1'b0)? 3'd6 :
|
||||
(rompage128 == 1'b1 && rom_alt48 == 1'b1)? 3'd7 :
|
||||
(rompage128 == 1'b1)? 3'd1 :
|
||||
3'd0;
|
||||
end
|
||||
|
||||
assign va[18:0] =
|
||||
rom2ram_ram_wren? {2'b00, rom2ram_ram_address} :
|
||||
screen_fetch && snow? {3'b111, screenpage, screen_addr[14:8], {8{1'bz}}} :
|
||||
screen_fetch? {3'b111, screenpage, screen_addr} :
|
||||
romreq? {2'b00, rom_a[16:14], bus.a[13], {13{1'bz}}} :
|
||||
{ram_a[18:13], {13{1'bz}}};
|
||||
rom2ram_ram_wren? {2'b00, rom2ram_ram_address} :
|
||||
screen_fetch && snow? {3'b111, screenpage, screen_addr[14:8], {8{1'bz}}} :
|
||||
screen_fetch? {3'b111, screenpage, screen_addr} :
|
||||
romreq? {2'b00, rom_a[16:14], bus.a[13], {13{1'bz}}} :
|
||||
{ram_a[18:13], {13{1'bz}}};
|
||||
|
||||
assign vd[7:0] =
|
||||
~n_vrd? {8{1'bz}} :
|
||||
rom2ram_ram_wren? rom2ram_dataout :
|
||||
up_dout_active? up_dout :
|
||||
div_dout_active? div_dout :
|
||||
turbosound_dout_active? turbosound_dout :
|
||||
ports_dout_active? ports_dout :
|
||||
~n_wr? {8{1'bz}} :
|
||||
8'hFF;
|
||||
~n_vrd? {8{1'bz}} :
|
||||
rom2ram_ram_wren? rom2ram_dataout :
|
||||
up_dout_active? up_dout :
|
||||
div_dout_active? div_dout :
|
||||
turbosound_dout_active? turbosound_dout :
|
||||
ports_dout_active? ports_dout :
|
||||
~n_wr? {8{1'bz}} :
|
||||
8'hFF;
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
Reference in New Issue
Block a user