add fpga firmware file in bin format

Makefile

@@ -12,11 +12,12 @@ all:
 build_rev:
 	${MAKE} REV=${REV} -C rom_src/ clean all
 	${MAKE} REV=${REV} -C rom/ clean all
-	${MAKE} REV=${REV} -C fpga/syn/ clean build sof2jic
+	${MAKE} REV=${REV} -C fpga/syn/ clean build sof2jic rbf2bin
 	cp fpga/syn/output/rev_${REV}.jic ${OUTDIR}/rev_${REV}.jic
+	cat fpga/syn/output/rev_${REV}.bin rom/sizif.rom > ${OUTDIR}/rev_${REV}.bin
 
 clean:
-	rm -f "${OUTDIR}"
+	rm -rf "${OUTDIR}"
 	${MAKE} -C fpga/syn/ clean
 	${MAKE} -C fpga/tb/ clean
 	${MAKE} -C rom_src/ clean

README.md

@@ -50,6 +50,11 @@ Sizif contains 512K RAM. 128K available via 7FFDh port, 128K via DFFDh (Profi st
 ### SD card
 Sizif have preinstalled esxDOS firmware, which provides ability to load TAP, TRD, SCL, Z80 files and save snapshots. To use this you should format SD cart to FAT32 or FAT16 and unpack latest esxDOS release ([link](http://www.esxdos.org/index.html)) to card. Also it's recommended to install Long Filename Browser ([link](https://spectrumcomputing.co.uk/forums/viewtopic.php?t=2553)) to card.
 
+### How to program
+There is two options:
+1. Program via JTAG connector using USB blaster and Quartus Programmer - use jic file from out folder.
+2. Program flash chip directly using TL866 or similar device - use bin file.
+
 ### Changelog & current status
 * Rev.A - first release. Please note the [errata](pcb/rev.A/ERRATA.txt).
 * Rev.B:

fpga/syn/Makefile

@@ -12,6 +12,9 @@ sof2jic:
 	mv output/zx_ula.jic "output/${REVISION}.jic"
 	rm output/zx_ula.sof
 
+rbf2bin:
+	srec_cat output/rev_${REV}.rbf -binary -Bit_Reverse 2 -Byte_Swap 2 -o output/rev_${REV}.bin -binary
+
 program_sof:
 	quartus_pgm --no_banner --mode=jtag -o "P;output/${REVISION}.sof"
 
@@ -24,6 +27,6 @@ clean:
 report:
 	cat output/${REVISION}.*.smsg output/${REVISION}.*.rpt |grep -e Error -e Critical -e Warning |grep -v -e "Family doesn't support jitter analysis" -e "Force Fitter to Avoid Periphery Placement Warnings"
 
-export PATH:=/opt/quartus13.0sp1/quartus/bin:/cygdrive/c/Hwdev/quartus130sp1/quartus/bin:${PATH}
+export PATH:=/opt/quartus13.0sp1/quartus/bin:/cygdrive/c/Hwdev/quartus130sp1/quartus/bin:/cygdrive/c/Dev/srec/bin/:${PATH}
 
 -include Makefile.local

fpga/syn/rev_A.qsf

@@ -197,4 +197,6 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
 set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/syn/rev_B.qsf

@@ -197,4 +197,6 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
 set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

fpga/syn/rev_zero_A.qsf

@@ -198,4 +198,6 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
 set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
 set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top