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https://github.com/UzixLS/zx-sizif-xxs.git
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202 lines
11 KiB
Plaintext
202 lines
11 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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# Date created = 08:15:12 April 28, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# rev_A_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY Cyclone
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set_global_assignment -name DEVICE EP1C3T100C8
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set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:56:16 NOVEMBER 08, 2021"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz"
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set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14
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set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu
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set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
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set_global_assignment -name AUTO_LCELL_INSERTION OFF
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set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32
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set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8
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set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
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set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
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set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
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set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
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set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
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set_global_assignment -name SAVE_DISK_SPACE OFF
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name POWER_USE_PVA OFF
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rd
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_wr
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_m1
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_mreq
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rfsh
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rstcpu
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_nmi
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE EPCS4
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set_location_assignment PIN_1 -to va[10]
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set_location_assignment PIN_2 -to va[5]
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set_location_assignment PIN_3 -to vd[4]
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set_location_assignment PIN_4 -to va[12]
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set_location_assignment PIN_5 -to va[11]
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set_location_assignment PIN_20 -to ps2_dat
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set_location_assignment PIN_21 -to ps2_clk
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set_location_assignment PIN_22 -to reserv[0]
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set_location_assignment PIN_23 -to reserv[1]
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set_location_assignment PIN_24 -to composite[0]
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set_location_assignment PIN_25 -to composite[7]
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set_location_assignment PIN_26 -to composite[6]
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set_location_assignment PIN_27 -to composite[5]
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set_location_assignment PIN_28 -to composite[4]
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set_location_assignment PIN_29 -to composite[3]
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set_location_assignment PIN_34 -to composite[2]
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set_location_assignment PIN_35 -to composite[1]
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set_location_assignment PIN_36 -to snd_l
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set_location_assignment PIN_37 -to snd_r
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set_location_assignment PIN_38 -to sd_cd
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set_location_assignment PIN_39 -to sd_cs
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set_location_assignment PIN_40 -to sd_miso_tape_in
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set_location_assignment PIN_41 -to sd_sck
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set_location_assignment PIN_42 -to sd_mosi_tape_out
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set_location_assignment PIN_47 -to vd[2]
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set_location_assignment PIN_48 -to vd[0]
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set_location_assignment PIN_49 -to vd[7]
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set_location_assignment PIN_50 -to vd[1]
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set_location_assignment PIN_51 -to vd[6]
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set_location_assignment PIN_52 -to n_mreq
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set_location_assignment PIN_54 -to n_int
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set_location_assignment PIN_55 -to n_nmi
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set_location_assignment PIN_56 -to va[14]
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set_location_assignment PIN_57 -to n_vrd
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set_location_assignment PIN_65 -to va[16]
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set_location_assignment PIN_68 -to va[18]
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set_location_assignment PIN_69 -to va[15]
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set_location_assignment PIN_70 -to va[13]
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set_location_assignment PIN_71 -to n_vwr
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set_location_assignment PIN_72 -to va[17]
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set_location_assignment PIN_73 -to clkcpu
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set_location_assignment PIN_74 -to n_wr
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set_location_assignment PIN_75 -to n_rd
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set_location_assignment PIN_76 -to a[14]
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set_location_assignment PIN_77 -to a[15]
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set_location_assignment PIN_78 -to a[13]
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set_location_assignment PIN_79 -to vd[5]
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set_location_assignment PIN_84 -to n_rstcpu
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set_location_assignment PIN_85 -to n_m1
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set_location_assignment PIN_86 -to n_rfsh
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set_location_assignment PIN_87 -to vd[3]
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set_location_assignment PIN_88 -to va[0]
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set_location_assignment PIN_89 -to va[1]
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set_location_assignment PIN_90 -to va[2]
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set_location_assignment PIN_91 -to va[3]
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set_location_assignment PIN_92 -to va[4]
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set_location_assignment PIN_97 -to va[6]
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set_location_assignment PIN_98 -to va[7]
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set_location_assignment PIN_99 -to va[8]
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set_location_assignment PIN_100 -to va[9]
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
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set_location_assignment PIN_53 -to n_iorq
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output/stp1.stp
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set_global_assignment -name RTLV_GROUP_RELATED_NODES OFF
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_miso_tape_in
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_iorq
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set_location_assignment PIN_10 -to clk_in
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set_global_assignment -name SLD_FILE "/home/uzix/zx-sizif-xxs/fpga/rtl/stp2_auto_stripped.stp"
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[0]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[1]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[2]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[4]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[3]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[5]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[6]
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to vd[7]
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set_global_assignment -name VERILOG_MACRO "REV_A=<None>"
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ym2149.sv
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set_global_assignment -name VERILOG_FILE ../rtl/vencode_sin_cos.v
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set_global_assignment -name VHDL_FILE ../rtl/vencode.vhd
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set_global_assignment -name VERILOG_INCLUDE_FILE ../rtl/ps2_codes.vh
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/mixer.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/soundrive.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/screen.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ports.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/magic.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/divmmc.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/cpucontrol.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/memcontrol.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/turbosound.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/ulaplus.sv
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set_global_assignment -name VERILOG_FILE ../rtl/ps2.v
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set_global_assignment -name VERILOG_FILE ../rtl/ps2_rxtx.v
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/common.sv
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set_global_assignment -name SYSTEMVERILOG_FILE ../rtl/top.sv
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set_global_assignment -name SDC_FILE clocks.sdc
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set_global_assignment -name CDF_FILE output/zx_ula.cdf
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set_global_assignment -name QIP_FILE ip/pll.qip
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set_global_assignment -name QIP_FILE ip/rom2ram.qip
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set_global_assignment -name QIP_FILE ip/asmi.qip
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
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set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
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set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |