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fix io contention

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UzixLS
2022-02-02 20:34:51 +03:00
parent 35d1864d14
commit 664492d8f8
1 changed files with 2 additions and 2 deletions
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4
fpga/rtl/cpucontrol.sv
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@ -30,12 +30,12 @@ module cpucontrol(
/* CONTENTION */ /* CONTENTION */
wire iorq_contended = bus.iorq && (~bus.a[0] || (~bus.a[1] && ~bus.a[15] && bus.wr)) && (machine != MACHINE_S3); wire iorq_contended = bus.iorq && (~bus.a_reg[0] || (~bus.a_reg[1] && ~bus.a[15] && bus.wr)) && (machine != MACHINE_S3);
reg mreq_delayed, iorq_delayed; reg mreq_delayed, iorq_delayed;
always @(posedge clkcpu) always @(posedge clkcpu)
mreq_delayed <= bus.mreq; mreq_delayed <= bus.mreq;
always @(posedge clkcpu) always @(posedge clkcpu)
iorq_delayed <= bus.iorq && ~bus.a[0]; iorq_delayed <= bus.iorq && ~bus.a_reg[0];
wire contention_mem_page = (machine == MACHINE_S3)? rampage128[2] : rampage128[0]; wire contention_mem_page = (machine == MACHINE_S3)? rampage128[2] : rampage128[0];
wire contention_mem_addr = bus.a[14] & (~bus.a[15] | (bus.a[15] & contention_mem_page)); wire contention_mem_addr = bus.a[14] & (~bus.a[15] | (bus.a[15] & contention_mem_page));
wire contention_mem = iorq_delayed == 1'b0 && mreq_delayed == 1'b0 && contention_mem_addr; wire contention_mem = iorq_delayed == 1'b0 && mreq_delayed == 1'b0 && contention_mem_addr;