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LICENSE
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@ -1,21 +1,21 @@
MIT License
Copyright (c) 2020 Eugene Lozovoy
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
MIT License
Copyright (c) 2020 Eugene Lozovoy
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

164
README.md
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## Sizif-512
Another CPLD-based ZX Spectrum clone for 48K rubber case with some sweet features.
[![photo](https://cloud.err200.net/index.php/s/73TR85tYZkMm8Ax/download?path=/&files=sizif-512-c.small.jpg)](https://cloud.err200.net/index.php/apps/files_sharing/publicpreview/73TR85tYZkMm8Ax?fileId=50629&file=/sizif-512-c.png&x=-1&y=-1)
### Features
* Half-sized PCB for 48K rubber case, no case modifications necessary
* Pentagon 128 and Spectrum 128 timings
* Real Z80 in 3.5MHz and 7MHz (no-wait turbo) mode
* 512K RAM
* Real AY with switchable stereo ABC/ACB/mono
* Kempston Joystick
* Integrated DivMMC
* PAL and RGB video out (Sega Mini-DIN/9 connector)
* Digital video out (with EGA header ;))
* ULAplus
* Mono covox (Pentagon standart)
* SounDrive (4-channel stereo covox)
* WiFi
### Demonstration
Running Pentagon 128 and Spectrum 128 demos: [link](https://www.youtube.com/watch?v=_RoLKcfJSTY)
Playing music from SD: [link](https://www.youtube.com/watch?v=TmikKD3yqOU)
Some photos: [link](https://cloud.err200.net/index.php/s/73TR85tYZkMm8Ax?path=%2Fsizif-512)
### Magic button
Sizif have some configurable things which you may change at any moment and that's doesn't require reboot.
To do this there is a Magic button: just hold it and press key on keyboard:
| Key | Function |
| - | - |
| 1 | Switch to Pentagon 128 timings (by default) |
| 2 | Switch to Spectrum 128 timings |
| 3 | Switch to 3.5 MHz (normal) mode (by default) |
| 4 | Switch to 7 MHz (turbo) mode |
| 5 | Switch to ABC stereo (by default) |
| 6 | Switch to ACB stereo |
| 9 | Enable all additional features: DivMMC, 512K RAM, Kempston, Covox (by default) |
| 0 | Disable all additional features |
If you press Magic button and didn't change something, standard NMI handler 'll be called on button release.
### RAM
The board contains 512K RAM. There are two cases how to access it:
1. DivMMC enabled (SD card insert) - 128K available via 7FFDh port, 128K via DFFDh and 256K reserved for DivMMC.
2. No SD card present - 128K available via 7FFDh and 384K via DFFDh
### Strange lines on border and creaky sounds on SD card access
It's not a bug, it's a feature ;)
### WiFi module
It's possible to connect to internet with additional [WiFi module](https://github.com/UzixLS/zx-sizif-512-wifi).
### Changelog & current status
* Rev.A - first release. Please see [errata](pcb/rev.A/ERRATA.ru.txt) (in russian).
* Rev.B - abandoned. Files keep for historical reason.
* Rev.C - BDI has been removed; improved video circuit; more capable CPLD; better power circuit; add mono AY mode. [Errata](pcb/rev.C/ERRATA.txt).
* Rev.C1 - fixed incorrect JTAG pinout; fixed incorrect silkscreen for power connector J3, tuned some circuit values. Everything seems to work. [Errata](pcb/rev.C1/ERRATA.txt).
### Roadmap
PCB rev.D (not soon):
* add zxbus connector for in-case addons
* add support for +3DOS floppy controller
* improve tapein circuit to handle super-turbo loaders
* improve video circuit for ulaplus (?)
Firmware:
* add optional Magic-button's OSD menu
* add support for MegaDrive 6-button gamepad
* add ability to map kempston to any keyboard button
* add ROM banks switching menu
* add +3 ports
* add 48K timings
* improve 128K timings for 100% compatibility
### Acknowledgments
This work is based on a lot of other projects and would hardly have been successful without them.
* Harlequin (no official link?)
* Karabas-128 ([link](https://github.com/andykarpov/karabas-128))
* ZX Evolution ([link](http://nedopc.com/zxevo/zxevo.php))
* zx_ula verilog implementation ([link](https://opencores.org/projects/zx_ula))
* Робик АЛУ ([link](https://zx-pk.ru/threads/19862-robik-alu-modul-rasshireniya.html))
* fbas_encoder ([link](https://opencores.org/projects/fbas_encoder))
## Sizif-512
Another CPLD-based ZX Spectrum clone for 48K rubber case with some sweet features.
[![photo](https://cloud.err200.net/index.php/s/73TR85tYZkMm8Ax/download?path=/&files=sizif-512-c.small.jpg)](https://cloud.err200.net/index.php/apps/files_sharing/publicpreview/73TR85tYZkMm8Ax?fileId=50629&file=/sizif-512-c.png&x=-1&y=-1)
### Features
* Half-sized PCB for 48K rubber case, no case modifications necessary
* Pentagon 128 and Spectrum 128 timings
* Real Z80 in 3.5MHz and 7MHz (no-wait turbo) mode
* 512K RAM
* Real AY with switchable stereo ABC/ACB/mono
* Kempston Joystick
* Integrated DivMMC
* PAL and RGB video out (Sega Mini-DIN/9 connector)
* Digital video out (with EGA header ;))
* ULAplus
* Mono covox (Pentagon standart)
* SounDrive (4-channel stereo covox)
* WiFi
### Demonstration
Running Pentagon 128 and Spectrum 128 demos: [link](https://www.youtube.com/watch?v=_RoLKcfJSTY)
Playing music from SD: [link](https://www.youtube.com/watch?v=TmikKD3yqOU)
Some photos: [link](https://cloud.err200.net/index.php/s/73TR85tYZkMm8Ax?path=%2Fsizif-512)
### Magic button
Sizif have some configurable things which you may change at any moment and that's doesn't require reboot.
To do this there is a Magic button: just hold it and press key on keyboard:
| Key | Function |
| - | - |
| 1 | Switch to Pentagon 128 timings (by default) |
| 2 | Switch to Spectrum 128 timings |
| 3 | Switch to 3.5 MHz (normal) mode (by default) |
| 4 | Switch to 7 MHz (turbo) mode |
| 5 | Switch to ABC stereo (by default) |
| 6 | Switch to ACB stereo |
| 9 | Enable all additional features: DivMMC, 512K RAM, Kempston, Covox (by default) |
| 0 | Disable all additional features |
If you press Magic button and didn't change something, standard NMI handler 'll be called on button release.
### RAM
The board contains 512K RAM. There are two cases how to access it:
1. DivMMC enabled (SD card insert) - 128K available via 7FFDh port, 128K via DFFDh and 256K reserved for DivMMC.
2. No SD card present - 128K available via 7FFDh and 384K via DFFDh
### Strange lines on border and creaky sounds on SD card access
It's not a bug, it's a feature ;)
### WiFi module
It's possible to connect to internet with additional [WiFi module](https://github.com/UzixLS/zx-sizif-512-wifi).
### Changelog & current status
* Rev.A - first release. Please see [errata](pcb/rev.A/ERRATA.ru.txt) (in russian).
* Rev.B - abandoned. Files keep for historical reason.
* Rev.C - BDI has been removed; improved video circuit; more capable CPLD; better power circuit; add mono AY mode. [Errata](pcb/rev.C/ERRATA.txt).
* Rev.C1 - fixed incorrect JTAG pinout; fixed incorrect silkscreen for power connector J3, tuned some circuit values. Everything seems to work. [Errata](pcb/rev.C1/ERRATA.txt).
### Roadmap
PCB rev.D (not soon):
* add zxbus connector for in-case addons
* add support for +3DOS floppy controller
* improve tapein circuit to handle super-turbo loaders
* improve video circuit for ulaplus (?)
Firmware:
* add optional Magic-button's OSD menu
* add support for MegaDrive 6-button gamepad
* add ability to map kempston to any keyboard button
* add ROM banks switching menu
* add +3 ports
* add 48K timings
* improve 128K timings for 100% compatibility
### Acknowledgments
This work is based on a lot of other projects and would hardly have been successful without them.
* Harlequin (no official link?)
* Karabas-128 ([link](https://github.com/andykarpov/karabas-128))
* ZX Evolution ([link](http://nedopc.com/zxevo/zxevo.php))
* zx_ula verilog implementation ([link](https://opencores.org/projects/zx_ula))
* Робик АЛУ ([link](https://zx-pk.ru/threads/19862-robik-alu-modul-rasshireniya.html))
* fbas_encoder ([link](https://opencores.org/projects/fbas_encoder))

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cpld/rev.A/clocks.sdc
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create_clock -period 14.4MHz -name {clk_14mhz} [get_ports {clk14}]
create_clock -period 32MHz -name {clk_32mhz} [get_ports {clk32}]
# clkcpu 3.5 or 7 MHz
create_generated_clock -name {clkcpu} -divide_by 2 -source [get_ports {clk14}] [get_registers {clkcpu~reg0}]
# int len in turbo = 66
create_generated_clock -name {n_int} -divide_by 64 -source [get_ports {clk14}] [get_registers {n_int~reg0}]
# hsync len 4.7uS, 14e6/(1/4.7e-6) ~= 65
create_generated_clock -name {hsync} -divide_by 63 -source [get_ports {clk14}] [get_registers {hsync~reg0}]
# chroma carrier
create_generated_clock -name {chroma_carrier} -divide_by 6 -source [get_ports {clk32}] [get_registers {*:chroma_gen1|carrier[15]}]
set_false_path -from [get_registers {r~reg0}] -to [get_clocks {clk_32mhz}]
set_false_path -from [get_registers {g~reg0}] -to [get_clocks {clk_32mhz}]
set_false_path -from [get_registers {b~reg0}] -to [get_clocks {clk_32mhz}]
derive_clock_uncertainty
derive_clocks -period 7.2MHz
create_clock -period 14.4MHz -name {clk_14mhz} [get_ports {clk14}]
create_clock -period 32MHz -name {clk_32mhz} [get_ports {clk32}]
# clkcpu 3.5 or 7 MHz
create_generated_clock -name {clkcpu} -divide_by 2 -source [get_ports {clk14}] [get_registers {clkcpu~reg0}]
# int len in turbo = 66
create_generated_clock -name {n_int} -divide_by 64 -source [get_ports {clk14}] [get_registers {n_int~reg0}]
# hsync len 4.7uS, 14e6/(1/4.7e-6) ~= 65
create_generated_clock -name {hsync} -divide_by 63 -source [get_ports {clk14}] [get_registers {hsync~reg0}]
# chroma carrier
create_generated_clock -name {chroma_carrier} -divide_by 6 -source [get_ports {clk32}] [get_registers {*:chroma_gen1|carrier[15]}]
set_false_path -from [get_registers {r~reg0}] -to [get_clocks {clk_32mhz}]
set_false_path -from [get_registers {g~reg0}] -to [get_clocks {clk_32mhz}]
set_false_path -from [get_registers {b~reg0}] -to [get_clocks {clk_32mhz}]
derive_clock_uncertainty
derive_clocks -period 7.2MHz

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cpld/rev.A/top.v
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cpld/rev.A/util.vh
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`define MAX(a,b) (a)>(b)?(a):(b)
`define MIN(a,b) (a)<(b)?(a):(b)
`define ISDEF(N) (^(N) >= 0 === 1'b1 || ^(N) < 0 === 1'b1) //"IS DEFined", is an
//integer strictly defined; Xilinx warnings about "===" in synthesable
//code - include in supression rules.
//Why so complicated - I forgot :)
`define TZER(N) (!`ISDEF(N) || (N) <= 0) ? 'hx : \
(~|((N)&'h7fff_ffff)?31:(~|((N)&'h3fff_ffff)?30: \
(~|((N)&'h1fff_ffff)?29:(~|((N)&'hfff_ffff)?28: \
(~|((N)&'h7ff_ffff)?27:(~|((N)&'h3ff_ffff)?26:(~|((N)&'h1ff_ffff)?25:(~|((N)&'hff_ffff)?24: \
(~|((N)&'h7f_ffff)?23:(~|((N)&'h3f_ffff)?22:(~|((N)&'h1f_ffff)?21:(~|((N)&'hf_ffff)?20: \
(~|((N)&'h7_ffff)?19:(~|((N)&'h3_ffff)?18:(~|((N)&'h1_ffff)?17:(~|((N)&'hffff)?16: \
(~|((N)&'h7fff)?15:(~|((N)&'h3fff)?14:(~|((N)&'h1fff)?13:(~|((N)&'hfff)?12: \
(~|((N)&'h7ff)?11:(~|((N)&'h3ff)?10:(~|((N)&'h1ff)?9:(~|((N)&'hff)?8: \
(~|((N)&'h7f)?7:(~|((N)&'h3f)?6:(~|((N)&'h1f)?5:(~|((N)&'hf)?4: \
(~|((N)&'h7)?3:(~|((N)&'h3)?2: \
(~N&'h1))))))))))))))))))))))))))))))) //"Trailong ZERoes". ONLY FOR ARGUMENTS <= 32 BITS!
//Maximum 2's power divider of a number. Both for synthesis and simulation; bit
//selection is not used since N could be an expression.
`define CLOG2_CORE(N) \
((N)&'h8000_0000 ?32:((N)&'h4000_0000 ?31:((N)&'h2000_0000 ?30:((N)&'h1000_0000 ?29: \
((N)&'h800_0000 ?28:((N)&'h400_0000 ?27:((N)&'h200_0000 ?26:((N)&'h100_0000 ?25: \
((N)&'h80_0000 ?24:((N)&'h40_0000 ?23:((N)&'h20_0000 ?22:((N)&'h10_0000 ?21: \
((N)&'h8_0000 ?20:((N)&'h4_0000 ?19:((N)&'h2_0000 ?18:((N)&'h1_0000 ?17: \
((N)&'h8000 ?16:((N)&'h4000 ?15:((N)&'h2000 ?14:((N)&'h1000 ?13: \
((N)&'h800 ?12:((N)&'h400 ?11:((N)&'h200 ?10:((N)&'h100 ?9: \
((N)&'h80 ?8:((N)&'h40 ?7:((N)&'h20 ?6:((N)&'h10 ?5: \
((N)&'h8 ?4:((N)&'h4 ?3:((N)&'h2 ?2: \
((N)&'h1)))))))))))))))))))))))))))))))) //"Core Ceil(LOG2(N+1))" for correctly defined
//values (<= 32 bits). Both for synthesis and not; bit selection is not
//used since N could be an expression.
`define HZ2NS(F) (1.0e9 / (F)) //Convert frequency [Hz] to delay in [ns].
`define ABS(X) ((X >= 0) ? (X) : (-X)) //ABSolute value of X.
`define CLOG2(N) ((!`ISDEF(N) || (N) <= 0) ? 'hx : `CLOG2_CORE((N)-1)) //"Ceil(LOG2(N))"
//ONLY FOR ARGUMENTS <= 32 BITS! Ceil (nearest greater or equal integer) of
//binary logarithm.
`define WIDINPAR(W) ((W) >= 1 ? (W) : ((W) == 0 ? 1'b1 : 1'bx)) //"WIDth INdex from a
//PARameter" ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus from given
//parameter, to avoid index "-1".
//Ex.: bus with width W: "[widinpar(W)-1:0];"
`define WIDC(N) (`ISDEF(N) && (N) == 0 ? 1 : `CLOG2((N) + 1)) //"WIDth Computation"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of it's maximum
//value (from 0).
//Ex.: bus for holding numbers in range [0..N]: "wire [`WIDCF(N)-1:0] bus;"
//Precision width of parameters: "localparam [`WIDCF(<expr>)-1:0] N = <expr>;"
`define WIDCN(N) (`ISDEF(N) && ((N) == 0 || (N) == 1) ? 1 : `CLOG2(N)) //"WIDth Computation from N"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of number of it's
//different values. Handy for computation of high index of a bus.
//Ex.: coder with N inputs output: "output [`WIDCFN(N)-1:0] out;";
//N-words RAM adress input: "input [`WIDCFN(N)-1:0] adr;"
`define URAND(MIN, MAX) ((MAX) < (MIN) ? 1'bx : (((MAX) == (MIN)) ? (MIN) : \
(MIN + {$random} % ((MAX) - (MIN)))) )
//Form an unsigned random value in the range [MIN..MAX-1];
//"{}" makes unsigned.
`define POS_FMOD(A, B) A - B * ($rtoi((A + 0.0) / B) + $signed(A < 0)) //Positive fraction
//modulo. Only for POSITIVE dividers!!!
`define ISHEXD(L) (`ISDEF(L) && ((L) >= "A" && (L) <= "F" || (L) >= "a" && (L) <= "f" || \
(L) >= "0" && (L) <= "9")) //IS byte a HEX Digit. x- and z-
//bits are treated correctly.
`define ISHEXDX(L) (`ISHEXD(L) || \
`ISDEF(L) && ((L) == "X" || (L) == "x")) //IS byte a HEX Digit or X/x.
`define IS_DEC_INT_DIG(L) ((L) >= "0" && (L) <= "9") //Is a byte a valid decimal
//integer digit.
`define HEXD2DEC(L) (!`ISHEXD(L) ? \
0 : \
((L) >= "a" ? (L) - "a" + 10 : \
((L) >= "A" ? (L) - "A" + 10 : \
(L) - "0"))) //Convert
`define MAX(a,b) (a)>(b)?(a):(b)
`define MIN(a,b) (a)<(b)?(a):(b)
`define ISDEF(N) (^(N) >= 0 === 1'b1 || ^(N) < 0 === 1'b1) //"IS DEFined", is an
//integer strictly defined; Xilinx warnings about "===" in synthesable
//code - include in supression rules.
//Why so complicated - I forgot :)
`define TZER(N) (!`ISDEF(N) || (N) <= 0) ? 'hx : \
(~|((N)&'h7fff_ffff)?31:(~|((N)&'h3fff_ffff)?30: \
(~|((N)&'h1fff_ffff)?29:(~|((N)&'hfff_ffff)?28: \
(~|((N)&'h7ff_ffff)?27:(~|((N)&'h3ff_ffff)?26:(~|((N)&'h1ff_ffff)?25:(~|((N)&'hff_ffff)?24: \
(~|((N)&'h7f_ffff)?23:(~|((N)&'h3f_ffff)?22:(~|((N)&'h1f_ffff)?21:(~|((N)&'hf_ffff)?20: \
(~|((N)&'h7_ffff)?19:(~|((N)&'h3_ffff)?18:(~|((N)&'h1_ffff)?17:(~|((N)&'hffff)?16: \
(~|((N)&'h7fff)?15:(~|((N)&'h3fff)?14:(~|((N)&'h1fff)?13:(~|((N)&'hfff)?12: \
(~|((N)&'h7ff)?11:(~|((N)&'h3ff)?10:(~|((N)&'h1ff)?9:(~|((N)&'hff)?8: \
(~|((N)&'h7f)?7:(~|((N)&'h3f)?6:(~|((N)&'h1f)?5:(~|((N)&'hf)?4: \
(~|((N)&'h7)?3:(~|((N)&'h3)?2: \
(~N&'h1))))))))))))))))))))))))))))))) //"Trailong ZERoes". ONLY FOR ARGUMENTS <= 32 BITS!
//Maximum 2's power divider of a number. Both for synthesis and simulation; bit
//selection is not used since N could be an expression.
`define CLOG2_CORE(N) \
((N)&'h8000_0000 ?32:((N)&'h4000_0000 ?31:((N)&'h2000_0000 ?30:((N)&'h1000_0000 ?29: \
((N)&'h800_0000 ?28:((N)&'h400_0000 ?27:((N)&'h200_0000 ?26:((N)&'h100_0000 ?25: \
((N)&'h80_0000 ?24:((N)&'h40_0000 ?23:((N)&'h20_0000 ?22:((N)&'h10_0000 ?21: \
((N)&'h8_0000 ?20:((N)&'h4_0000 ?19:((N)&'h2_0000 ?18:((N)&'h1_0000 ?17: \
((N)&'h8000 ?16:((N)&'h4000 ?15:((N)&'h2000 ?14:((N)&'h1000 ?13: \
((N)&'h800 ?12:((N)&'h400 ?11:((N)&'h200 ?10:((N)&'h100 ?9: \
((N)&'h80 ?8:((N)&'h40 ?7:((N)&'h20 ?6:((N)&'h10 ?5: \
((N)&'h8 ?4:((N)&'h4 ?3:((N)&'h2 ?2: \
((N)&'h1)))))))))))))))))))))))))))))))) //"Core Ceil(LOG2(N+1))" for correctly defined
//values (<= 32 bits). Both for synthesis and not; bit selection is not
//used since N could be an expression.
`define HZ2NS(F) (1.0e9 / (F)) //Convert frequency [Hz] to delay in [ns].
`define ABS(X) ((X >= 0) ? (X) : (-X)) //ABSolute value of X.
`define CLOG2(N) ((!`ISDEF(N) || (N) <= 0) ? 'hx : `CLOG2_CORE((N)-1)) //"Ceil(LOG2(N))"
//ONLY FOR ARGUMENTS <= 32 BITS! Ceil (nearest greater or equal integer) of
//binary logarithm.
`define WIDINPAR(W) ((W) >= 1 ? (W) : ((W) == 0 ? 1'b1 : 1'bx)) //"WIDth INdex from a
//PARameter" ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus from given
//parameter, to avoid index "-1".
//Ex.: bus with width W: "[widinpar(W)-1:0];"
`define WIDC(N) (`ISDEF(N) && (N) == 0 ? 1 : `CLOG2((N) + 1)) //"WIDth Computation"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of it's maximum
//value (from 0).
//Ex.: bus for holding numbers in range [0..N]: "wire [`WIDCF(N)-1:0] bus;"
//Precision width of parameters: "localparam [`WIDCF(<expr>)-1:0] N = <expr>;"
`define WIDCN(N) (`ISDEF(N) && ((N) == 0 || (N) == 1) ? 1 : `CLOG2(N)) //"WIDth Computation from N"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of number of it's
//different values. Handy for computation of high index of a bus.
//Ex.: coder with N inputs output: "output [`WIDCFN(N)-1:0] out;";
//N-words RAM adress input: "input [`WIDCFN(N)-1:0] adr;"
`define URAND(MIN, MAX) ((MAX) < (MIN) ? 1'bx : (((MAX) == (MIN)) ? (MIN) : \
(MIN + {$random} % ((MAX) - (MIN)))) )
//Form an unsigned random value in the range [MIN..MAX-1];
//"{}" makes unsigned.
`define POS_FMOD(A, B) A - B * ($rtoi((A + 0.0) / B) + $signed(A < 0)) //Positive fraction
//modulo. Only for POSITIVE dividers!!!
`define ISHEXD(L) (`ISDEF(L) && ((L) >= "A" && (L) <= "F" || (L) >= "a" && (L) <= "f" || \
(L) >= "0" && (L) <= "9")) //IS byte a HEX Digit. x- and z-
//bits are treated correctly.
`define ISHEXDX(L) (`ISHEXD(L) || \
`ISDEF(L) && ((L) == "X" || (L) == "x")) //IS byte a HEX Digit or X/x.
`define IS_DEC_INT_DIG(L) ((L) >= "0" && (L) <= "9") //Is a byte a valid decimal
//integer digit.
`define HEXD2DEC(L) (!`ISHEXD(L) ? \
0 : \
((L) >= "a" ? (L) - "a" + 10 : \
((L) >= "A" ? (L) - "A" + 10 : \
(L) - "0"))) //Convert
//HEXadecimal Digit to decimal number, on all incorrect inputs returns 0.

60
cpld/rev.A/zx_ula.qpf
View File

@ -1,30 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:15:12 April 28, 2019"
# Revisions
PROJECT_REVISION = "zx_ula"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:15:12 April 28, 2019"
# Revisions
PROJECT_REVISION = "zx_ula"

384
cpld/rev.A/zx_ula.qsf
View File

@ -1,193 +1,193 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_ula_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3256ATC144-10"
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_36 -to n_int
set_location_assignment PIN_29 -to n_iorq
set_location_assignment PIN_34 -to n_m1
set_location_assignment PIN_28 -to n_mreq
set_location_assignment PIN_27 -to n_rfsh
set_location_assignment PIN_6 -to n_vwr
set_location_assignment PIN_72 -to r
set_location_assignment PIN_127 -to rst_n
set_location_assignment PIN_60 -to tape_out
set_location_assignment PIN_25 -to va[16]
set_location_assignment PIN_30 -to va[15]
set_location_assignment PIN_31 -to va[14]
set_location_assignment PIN_11 -to va[13]
set_location_assignment PIN_12 -to va[12]
set_location_assignment PIN_14 -to va[11]
set_location_assignment PIN_15 -to va[10]
set_location_assignment PIN_16 -to va[9]
set_location_assignment PIN_18 -to va[8]
set_location_assignment PIN_8 -to va[7]
set_location_assignment PIN_5 -to va[6]
set_location_assignment PIN_2 -to va[5]
set_location_assignment PIN_1 -to va[4]
set_location_assignment PIN_10 -to va[1]
set_location_assignment PIN_9 -to va[0]
set_location_assignment PIN_39 -to vd[7]
set_location_assignment PIN_40 -to vd[6]
set_location_assignment PIN_38 -to vd[4]
set_location_assignment PIN_37 -to vd[2]
set_location_assignment PIN_32 -to vd[0]
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14
set_location_assignment PIN_7 -to va[18]
set_location_assignment PIN_23 -to va[17]
set_location_assignment PIN_54 -to n_iorqge_i
set_location_assignment PIN_53 -to n_iorqge_o
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_location_assignment PIN_45 -to a1
set_location_assignment PIN_35 -to n_nmi
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_location_assignment PIN_47 -to n_rstcpu
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_location_assignment PIN_63 -to n_joy_b1
set_location_assignment PIN_69 -to n_joy_b2
set_location_assignment PIN_68 -to n_joy_b3
set_location_assignment PIN_65 -to n_joy_down
set_location_assignment PIN_66 -to n_joy_left
set_location_assignment PIN_67 -to n_joy_right
set_location_assignment PIN_62 -to n_joy_up
set_location_assignment PIN_116 -to kd[0]
set_location_assignment PIN_113 -to kd[1]
set_location_assignment PIN_121 -to kd[2]
set_location_assignment PIN_120 -to kd[3]
set_location_assignment PIN_119 -to kd[4]
set_location_assignment PIN_55 -to tape_in
set_location_assignment PIN_78 -to vg_cs
set_location_assignment PIN_106 -to vg_dden
set_location_assignment PIN_92 -to fd_disk0
set_location_assignment PIN_86 -to fd_disk1
set_location_assignment PIN_103 -to vg_drq
set_location_assignment PIN_90 -to vg_hlt
set_location_assignment PIN_102 -to vg_intr
set_location_assignment PIN_97 -to vg_rawr
set_location_assignment PIN_98 -to fd_motor
set_location_assignment PIN_96 -to vg_rclk
set_location_assignment PIN_84 -to fd_rdat
set_location_assignment PIN_83 -to vg_rst
set_location_assignment PIN_88 -to fd_side1
set_location_assignment PIN_81 -to vg_sl
set_location_assignment PIN_82 -to vg_sr
set_location_assignment PIN_99 -to vg_tr43
set_location_assignment PIN_19 -to ra[14]
set_location_assignment PIN_21 -to ra[15]
set_location_assignment PIN_22 -to ra[16]
set_location_assignment PIN_91 -to fd_index
set_location_assignment PIN_79 -to vsync
set_location_assignment PIN_80 -to hsync
set_location_assignment PIN_125 -to clk32
set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32
set_instance_assignment -name CLOCK_SETTINGS clk32 -to clk32
set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8
set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
set_location_assignment PIN_41 -to ay_bc1
set_location_assignment PIN_42 -to ay_bdir
set_location_assignment PIN_43 -to ay_abc
set_location_assignment PIN_44 -to a0
set_location_assignment PIN_46 -to a14
set_location_assignment PIN_48 -to a15
set_location_assignment PIN_49 -to ay_clk
set_location_assignment PIN_56 -to beeper
set_location_assignment PIN_61 -to snd
set_location_assignment PIN_70 -to i
set_location_assignment PIN_71 -to g
set_location_assignment PIN_74 -to b
set_location_assignment PIN_75 -to csync
set_location_assignment PIN_87 -to fd_wdat
set_location_assignment PIN_93 -to vg_clk
set_location_assignment PIN_100 -to vg_wd
set_location_assignment PIN_101 -to vg_wf_de
set_location_assignment PIN_108 -to sd_cd
set_location_assignment PIN_109 -to sd_miso
set_location_assignment PIN_110 -to sd_sck
set_location_assignment PIN_111 -to sd_cs
set_location_assignment PIN_112 -to sd_mosi
set_location_assignment PIN_117 -to chroma[0]
set_location_assignment PIN_118 -to chroma[1]
set_location_assignment PIN_122 -to n_romcs
set_location_assignment PIN_134 -to clkcpu
set_location_assignment PIN_136 -to n_wr
set_location_assignment PIN_137 -to n_rd
set_location_assignment PIN_138 -to vd[5]
set_location_assignment PIN_139 -to vd[3]
set_location_assignment PIN_140 -to vd[1]
set_location_assignment PIN_141 -to va[2]
set_location_assignment PIN_142 -to n_vrd
set_location_assignment PIN_143 -to va[3]
set_location_assignment PIN_126 -to n_magic
set_location_assignment PIN_107 -to vg_index
set_location_assignment PIN_128 -to clk14
set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
set_location_assignment PIN_132 -to a13
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name POWER_USE_PVA OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name VHDL_FILE chroma_gen32.vhd
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_INCLUDE_FILE util.vh
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_ula_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3256ATC144-10"
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_36 -to n_int
set_location_assignment PIN_29 -to n_iorq
set_location_assignment PIN_34 -to n_m1
set_location_assignment PIN_28 -to n_mreq
set_location_assignment PIN_27 -to n_rfsh
set_location_assignment PIN_6 -to n_vwr
set_location_assignment PIN_72 -to r
set_location_assignment PIN_127 -to rst_n
set_location_assignment PIN_60 -to tape_out
set_location_assignment PIN_25 -to va[16]
set_location_assignment PIN_30 -to va[15]
set_location_assignment PIN_31 -to va[14]
set_location_assignment PIN_11 -to va[13]
set_location_assignment PIN_12 -to va[12]
set_location_assignment PIN_14 -to va[11]
set_location_assignment PIN_15 -to va[10]
set_location_assignment PIN_16 -to va[9]
set_location_assignment PIN_18 -to va[8]
set_location_assignment PIN_8 -to va[7]
set_location_assignment PIN_5 -to va[6]
set_location_assignment PIN_2 -to va[5]
set_location_assignment PIN_1 -to va[4]
set_location_assignment PIN_10 -to va[1]
set_location_assignment PIN_9 -to va[0]
set_location_assignment PIN_39 -to vd[7]
set_location_assignment PIN_40 -to vd[6]
set_location_assignment PIN_38 -to vd[4]
set_location_assignment PIN_37 -to vd[2]
set_location_assignment PIN_32 -to vd[0]
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14
set_location_assignment PIN_7 -to va[18]
set_location_assignment PIN_23 -to va[17]
set_location_assignment PIN_54 -to n_iorqge_i
set_location_assignment PIN_53 -to n_iorqge_o
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_location_assignment PIN_45 -to a1
set_location_assignment PIN_35 -to n_nmi
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_location_assignment PIN_47 -to n_rstcpu
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_location_assignment PIN_63 -to n_joy_b1
set_location_assignment PIN_69 -to n_joy_b2
set_location_assignment PIN_68 -to n_joy_b3
set_location_assignment PIN_65 -to n_joy_down
set_location_assignment PIN_66 -to n_joy_left
set_location_assignment PIN_67 -to n_joy_right
set_location_assignment PIN_62 -to n_joy_up
set_location_assignment PIN_116 -to kd[0]
set_location_assignment PIN_113 -to kd[1]
set_location_assignment PIN_121 -to kd[2]
set_location_assignment PIN_120 -to kd[3]
set_location_assignment PIN_119 -to kd[4]
set_location_assignment PIN_55 -to tape_in
set_location_assignment PIN_78 -to vg_cs
set_location_assignment PIN_106 -to vg_dden
set_location_assignment PIN_92 -to fd_disk0
set_location_assignment PIN_86 -to fd_disk1
set_location_assignment PIN_103 -to vg_drq
set_location_assignment PIN_90 -to vg_hlt
set_location_assignment PIN_102 -to vg_intr
set_location_assignment PIN_97 -to vg_rawr
set_location_assignment PIN_98 -to fd_motor
set_location_assignment PIN_96 -to vg_rclk
set_location_assignment PIN_84 -to fd_rdat
set_location_assignment PIN_83 -to vg_rst
set_location_assignment PIN_88 -to fd_side1
set_location_assignment PIN_81 -to vg_sl
set_location_assignment PIN_82 -to vg_sr
set_location_assignment PIN_99 -to vg_tr43
set_location_assignment PIN_19 -to ra[14]
set_location_assignment PIN_21 -to ra[15]
set_location_assignment PIN_22 -to ra[16]
set_location_assignment PIN_91 -to fd_index
set_location_assignment PIN_79 -to vsync
set_location_assignment PIN_80 -to hsync
set_location_assignment PIN_125 -to clk32
set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32
set_instance_assignment -name CLOCK_SETTINGS clk32 -to clk32
set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8
set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
set_location_assignment PIN_41 -to ay_bc1
set_location_assignment PIN_42 -to ay_bdir
set_location_assignment PIN_43 -to ay_abc
set_location_assignment PIN_44 -to a0
set_location_assignment PIN_46 -to a14
set_location_assignment PIN_48 -to a15
set_location_assignment PIN_49 -to ay_clk
set_location_assignment PIN_56 -to beeper
set_location_assignment PIN_61 -to snd
set_location_assignment PIN_70 -to i
set_location_assignment PIN_71 -to g
set_location_assignment PIN_74 -to b
set_location_assignment PIN_75 -to csync
set_location_assignment PIN_87 -to fd_wdat
set_location_assignment PIN_93 -to vg_clk
set_location_assignment PIN_100 -to vg_wd
set_location_assignment PIN_101 -to vg_wf_de
set_location_assignment PIN_108 -to sd_cd
set_location_assignment PIN_109 -to sd_miso
set_location_assignment PIN_110 -to sd_sck
set_location_assignment PIN_111 -to sd_cs
set_location_assignment PIN_112 -to sd_mosi
set_location_assignment PIN_117 -to chroma[0]
set_location_assignment PIN_118 -to chroma[1]
set_location_assignment PIN_122 -to n_romcs
set_location_assignment PIN_134 -to clkcpu
set_location_assignment PIN_136 -to n_wr
set_location_assignment PIN_137 -to n_rd
set_location_assignment PIN_138 -to vd[5]
set_location_assignment PIN_139 -to vd[3]
set_location_assignment PIN_140 -to vd[1]
set_location_assignment PIN_141 -to va[2]
set_location_assignment PIN_142 -to n_vrd
set_location_assignment PIN_143 -to va[3]
set_location_assignment PIN_126 -to n_magic
set_location_assignment PIN_107 -to vg_index
set_location_assignment PIN_128 -to clk14
set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
set_location_assignment PIN_132 -to a13
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
set_instance_assignment -name CLOCK_SETTINGS clk14 -to clk14
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name POWER_USE_PVA OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name VHDL_FILE chroma_gen32.vhd
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_INCLUDE_FILE util.vh
set_global_assignment -name CDF_FILE output/zx_ula.cdf

26
cpld/rev.C/clocks.sdc
View File

@ -1,13 +1,13 @@
create_clock -period 28.8MHz -name {clk_28mhz} [get_ports {clk28}]
# clkcpu 3.5 or 7 MHz
create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk28}] [get_registers {clkcpu~reg0}]
# int len in turbo = 66
create_generated_clock -name {n_int} -divide_by 128 -source [get_ports {clk28}] [get_registers {n_int~reg0}]
# hsync len 4.7uS, 14e6/(1/4.7e-6) ~= 65
create_generated_clock -name {hsync} -divide_by 126 -source [get_ports {clk28}] [get_registers {hsync~reg0}]
derive_clock_uncertainty
derive_clocks -period 7.2MHz
create_clock -period 28.8MHz -name {clk_28mhz} [get_ports {clk28}]
# clkcpu 3.5 or 7 MHz
create_generated_clock -name {clkcpu} -divide_by 4 -source [get_ports {clk28}] [get_registers {clkcpu~reg0}]
# int len in turbo = 66
create_generated_clock -name {n_int} -divide_by 128 -source [get_ports {clk28}] [get_registers {n_int~reg0}]
# hsync len 4.7uS, 14e6/(1/4.7e-6) ~= 65
create_generated_clock -name {hsync} -divide_by 126 -source [get_ports {clk28}] [get_registers {hsync~reg0}]
derive_clock_uncertainty
derive_clocks -period 7.2MHz

1590
cpld/rev.C/top.v
View File

File diff suppressed because it is too large Load Diff

166
cpld/rev.C/util.vh
View File

@ -1,84 +1,84 @@
`define MAX(a,b) (a)>(b)?(a):(b)
`define MIN(a,b) (a)<(b)?(a):(b)
`define ISDEF(N) (^(N) >= 0 === 1'b1 || ^(N) < 0 === 1'b1) //"IS DEFined", is an
//integer strictly defined; Xilinx warnings about "===" in synthesable
//code - include in supression rules.
//Why so complicated - I forgot :)
`define TZER(N) (!`ISDEF(N) || (N) <= 0) ? 'hx : \
(~|((N)&'h7fff_ffff)?31:(~|((N)&'h3fff_ffff)?30: \
(~|((N)&'h1fff_ffff)?29:(~|((N)&'hfff_ffff)?28: \
(~|((N)&'h7ff_ffff)?27:(~|((N)&'h3ff_ffff)?26:(~|((N)&'h1ff_ffff)?25:(~|((N)&'hff_ffff)?24: \
(~|((N)&'h7f_ffff)?23:(~|((N)&'h3f_ffff)?22:(~|((N)&'h1f_ffff)?21:(~|((N)&'hf_ffff)?20: \
(~|((N)&'h7_ffff)?19:(~|((N)&'h3_ffff)?18:(~|((N)&'h1_ffff)?17:(~|((N)&'hffff)?16: \
(~|((N)&'h7fff)?15:(~|((N)&'h3fff)?14:(~|((N)&'h1fff)?13:(~|((N)&'hfff)?12: \
(~|((N)&'h7ff)?11:(~|((N)&'h3ff)?10:(~|((N)&'h1ff)?9:(~|((N)&'hff)?8: \
(~|((N)&'h7f)?7:(~|((N)&'h3f)?6:(~|((N)&'h1f)?5:(~|((N)&'hf)?4: \
(~|((N)&'h7)?3:(~|((N)&'h3)?2: \
(~N&'h1))))))))))))))))))))))))))))))) //"Trailong ZERoes". ONLY FOR ARGUMENTS <= 32 BITS!
//Maximum 2's power divider of a number. Both for synthesis and simulation; bit
//selection is not used since N could be an expression.
`define CLOG2_CORE(N) \
((N)&'h8000_0000 ?32:((N)&'h4000_0000 ?31:((N)&'h2000_0000 ?30:((N)&'h1000_0000 ?29: \
((N)&'h800_0000 ?28:((N)&'h400_0000 ?27:((N)&'h200_0000 ?26:((N)&'h100_0000 ?25: \
((N)&'h80_0000 ?24:((N)&'h40_0000 ?23:((N)&'h20_0000 ?22:((N)&'h10_0000 ?21: \
((N)&'h8_0000 ?20:((N)&'h4_0000 ?19:((N)&'h2_0000 ?18:((N)&'h1_0000 ?17: \
((N)&'h8000 ?16:((N)&'h4000 ?15:((N)&'h2000 ?14:((N)&'h1000 ?13: \
((N)&'h800 ?12:((N)&'h400 ?11:((N)&'h200 ?10:((N)&'h100 ?9: \
((N)&'h80 ?8:((N)&'h40 ?7:((N)&'h20 ?6:((N)&'h10 ?5: \
((N)&'h8 ?4:((N)&'h4 ?3:((N)&'h2 ?2: \
((N)&'h1)))))))))))))))))))))))))))))))) //"Core Ceil(LOG2(N+1))" for correctly defined
//values (<= 32 bits). Both for synthesis and not; bit selection is not
//used since N could be an expression.
`define HZ2NS(F) (1.0e9 / (F)) //Convert frequency [Hz] to delay in [ns].
`define ABS(X) ((X >= 0) ? (X) : (-X)) //ABSolute value of X.
`define CLOG2(N) ((!`ISDEF(N) || (N) <= 0) ? 'hx : `CLOG2_CORE((N)-1)) //"Ceil(LOG2(N))"
//ONLY FOR ARGUMENTS <= 32 BITS! Ceil (nearest greater or equal integer) of
//binary logarithm.
`define WIDINPAR(W) ((W) >= 1 ? (W) : ((W) == 0 ? 1'b1 : 1'bx)) //"WIDth INdex from a
//PARameter" ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus from given
//parameter, to avoid index "-1".
//Ex.: bus with width W: "[widinpar(W)-1:0];"
`define WIDC(N) (`ISDEF(N) && (N) == 0 ? 1 : `CLOG2((N) + 1)) //"WIDth Computation"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of it's maximum
//value (from 0).
//Ex.: bus for holding numbers in range [0..N]: "wire [`WIDCF(N)-1:0] bus;"
//Precision width of parameters: "localparam [`WIDCF(<expr>)-1:0] N = <expr>;"
`define WIDCN(N) (`ISDEF(N) && ((N) == 0 || (N) == 1) ? 1 : `CLOG2(N)) //"WIDth Computation from N"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of number of it's
//different values. Handy for computation of high index of a bus.
//Ex.: coder with N inputs output: "output [`WIDCFN(N)-1:0] out;";
//N-words RAM adress input: "input [`WIDCFN(N)-1:0] adr;"
`define URAND(MIN, MAX) ((MAX) < (MIN) ? 1'bx : (((MAX) == (MIN)) ? (MIN) : \
(MIN + {$random} % ((MAX) - (MIN)))) )
//Form an unsigned random value in the range [MIN..MAX-1];
//"{}" makes unsigned.
`define POS_FMOD(A, B) A - B * ($rtoi((A + 0.0) / B) + $signed(A < 0)) //Positive fraction
//modulo. Only for POSITIVE dividers!!!
`define ISHEXD(L) (`ISDEF(L) && ((L) >= "A" && (L) <= "F" || (L) >= "a" && (L) <= "f" || \
(L) >= "0" && (L) <= "9")) //IS byte a HEX Digit. x- and z-
//bits are treated correctly.
`define ISHEXDX(L) (`ISHEXD(L) || \
`ISDEF(L) && ((L) == "X" || (L) == "x")) //IS byte a HEX Digit or X/x.
`define IS_DEC_INT_DIG(L) ((L) >= "0" && (L) <= "9") //Is a byte a valid decimal
//integer digit.
`define HEXD2DEC(L) (!`ISHEXD(L) ? \
0 : \
((L) >= "a" ? (L) - "a" + 10 : \
((L) >= "A" ? (L) - "A" + 10 : \
(L) - "0"))) //Convert
`define MAX(a,b) (a)>(b)?(a):(b)
`define MIN(a,b) (a)<(b)?(a):(b)
`define ISDEF(N) (^(N) >= 0 === 1'b1 || ^(N) < 0 === 1'b1) //"IS DEFined", is an
//integer strictly defined; Xilinx warnings about "===" in synthesable
//code - include in supression rules.
//Why so complicated - I forgot :)
`define TZER(N) (!`ISDEF(N) || (N) <= 0) ? 'hx : \
(~|((N)&'h7fff_ffff)?31:(~|((N)&'h3fff_ffff)?30: \
(~|((N)&'h1fff_ffff)?29:(~|((N)&'hfff_ffff)?28: \
(~|((N)&'h7ff_ffff)?27:(~|((N)&'h3ff_ffff)?26:(~|((N)&'h1ff_ffff)?25:(~|((N)&'hff_ffff)?24: \
(~|((N)&'h7f_ffff)?23:(~|((N)&'h3f_ffff)?22:(~|((N)&'h1f_ffff)?21:(~|((N)&'hf_ffff)?20: \
(~|((N)&'h7_ffff)?19:(~|((N)&'h3_ffff)?18:(~|((N)&'h1_ffff)?17:(~|((N)&'hffff)?16: \
(~|((N)&'h7fff)?15:(~|((N)&'h3fff)?14:(~|((N)&'h1fff)?13:(~|((N)&'hfff)?12: \
(~|((N)&'h7ff)?11:(~|((N)&'h3ff)?10:(~|((N)&'h1ff)?9:(~|((N)&'hff)?8: \
(~|((N)&'h7f)?7:(~|((N)&'h3f)?6:(~|((N)&'h1f)?5:(~|((N)&'hf)?4: \
(~|((N)&'h7)?3:(~|((N)&'h3)?2: \
(~N&'h1))))))))))))))))))))))))))))))) //"Trailong ZERoes". ONLY FOR ARGUMENTS <= 32 BITS!
//Maximum 2's power divider of a number. Both for synthesis and simulation; bit
//selection is not used since N could be an expression.
`define CLOG2_CORE(N) \
((N)&'h8000_0000 ?32:((N)&'h4000_0000 ?31:((N)&'h2000_0000 ?30:((N)&'h1000_0000 ?29: \
((N)&'h800_0000 ?28:((N)&'h400_0000 ?27:((N)&'h200_0000 ?26:((N)&'h100_0000 ?25: \
((N)&'h80_0000 ?24:((N)&'h40_0000 ?23:((N)&'h20_0000 ?22:((N)&'h10_0000 ?21: \
((N)&'h8_0000 ?20:((N)&'h4_0000 ?19:((N)&'h2_0000 ?18:((N)&'h1_0000 ?17: \
((N)&'h8000 ?16:((N)&'h4000 ?15:((N)&'h2000 ?14:((N)&'h1000 ?13: \
((N)&'h800 ?12:((N)&'h400 ?11:((N)&'h200 ?10:((N)&'h100 ?9: \
((N)&'h80 ?8:((N)&'h40 ?7:((N)&'h20 ?6:((N)&'h10 ?5: \
((N)&'h8 ?4:((N)&'h4 ?3:((N)&'h2 ?2: \
((N)&'h1)))))))))))))))))))))))))))))))) //"Core Ceil(LOG2(N+1))" for correctly defined
//values (<= 32 bits). Both for synthesis and not; bit selection is not
//used since N could be an expression.
`define HZ2NS(F) (1.0e9 / (F)) //Convert frequency [Hz] to delay in [ns].
`define ABS(X) ((X >= 0) ? (X) : (-X)) //ABSolute value of X.
`define CLOG2(N) ((!`ISDEF(N) || (N) <= 0) ? 'hx : `CLOG2_CORE((N)-1)) //"Ceil(LOG2(N))"
//ONLY FOR ARGUMENTS <= 32 BITS! Ceil (nearest greater or equal integer) of
//binary logarithm.
`define WIDINPAR(W) ((W) >= 1 ? (W) : ((W) == 0 ? 1'b1 : 1'bx)) //"WIDth INdex from a
//PARameter" ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus from given
//parameter, to avoid index "-1".
//Ex.: bus with width W: "[widinpar(W)-1:0];"
`define WIDC(N) (`ISDEF(N) && (N) == 0 ? 1 : `CLOG2((N) + 1)) //"WIDth Computation"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of it's maximum
//value (from 0).
//Ex.: bus for holding numbers in range [0..N]: "wire [`WIDCF(N)-1:0] bus;"
//Precision width of parameters: "localparam [`WIDCF(<expr>)-1:0] N = <expr>;"
`define WIDCN(N) (`ISDEF(N) && ((N) == 0 || (N) == 1) ? 1 : `CLOG2(N)) //"WIDth Computation from N"
//ONLY FOR ARGUMENTS <= 32 BITS! High index of a bus out of number of it's
//different values. Handy for computation of high index of a bus.
//Ex.: coder with N inputs output: "output [`WIDCFN(N)-1:0] out;";
//N-words RAM adress input: "input [`WIDCFN(N)-1:0] adr;"
`define URAND(MIN, MAX) ((MAX) < (MIN) ? 1'bx : (((MAX) == (MIN)) ? (MIN) : \
(MIN + {$random} % ((MAX) - (MIN)))) )
//Form an unsigned random value in the range [MIN..MAX-1];
//"{}" makes unsigned.
`define POS_FMOD(A, B) A - B * ($rtoi((A + 0.0) / B) + $signed(A < 0)) //Positive fraction
//modulo. Only for POSITIVE dividers!!!
`define ISHEXD(L) (`ISDEF(L) && ((L) >= "A" && (L) <= "F" || (L) >= "a" && (L) <= "f" || \
(L) >= "0" && (L) <= "9")) //IS byte a HEX Digit. x- and z-
//bits are treated correctly.
`define ISHEXDX(L) (`ISHEXD(L) || \
`ISDEF(L) && ((L) == "X" || (L) == "x")) //IS byte a HEX Digit or X/x.
`define IS_DEC_INT_DIG(L) ((L) >= "0" && (L) <= "9") //Is a byte a valid decimal
//integer digit.
`define HEXD2DEC(L) (!`ISHEXD(L) ? \
0 : \
((L) >= "a" ? (L) - "a" + 10 : \
((L) >= "A" ? (L) - "A" + 10 : \
(L) - "0"))) //Convert
//HEXadecimal Digit to decimal number, on all incorrect inputs returns 0.

60
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View File

@ -1,30 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:15:12 April 28, 2019"
# Revisions
PROJECT_REVISION = "zx_ula"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "08:15:12 April 28, 2019"
# Revisions
PROJECT_REVISION = "zx_ula"

444
cpld/rev.C/zx_ula.qsf
View File

@ -1,223 +1,223 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_ula_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM1270T144C5
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32
set_instance_assignment -name CLOCK_SETTINGS clk32 -to clk32
set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8
set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name POWER_USE_PVA OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_49 -to n_rd
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_INCLUDE_FILE util.vh
set_global_assignment -name CDF_FILE output/zx_ula.cdf
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_location_assignment PIN_1 -to vd[1]
set_location_assignment PIN_2 -to vd[2]
set_location_assignment PIN_3 -to sd_cs
set_location_assignment PIN_4 -to kd[0]
set_location_assignment PIN_5 -to kd[1]
set_location_assignment PIN_6 -to n_magic
set_location_assignment PIN_7 -to kd[4]
set_location_assignment PIN_8 -to kd[3]
set_location_assignment PIN_11 -to kd[2]
set_location_assignment PIN_12 -to sd_cd
set_location_assignment PIN_27 -to n_romcs
set_location_assignment PIN_28 -to ra[16]
set_location_assignment PIN_29 -to ra[15]
set_location_assignment PIN_30 -to ra[14]
set_location_assignment PIN_31 -to xa[14]
set_location_assignment PIN_32 -to xd[3]
set_location_assignment PIN_37 -to xa[15]
set_location_assignment PIN_38 -to xd[4]
set_location_assignment PIN_39 -to xd[5]
set_location_assignment PIN_40 -to xd[6]
set_location_assignment PIN_41 -to xd[7]
set_location_assignment PIN_42 -to xa[10]
set_location_assignment PIN_43 -to xa[11]
set_location_assignment PIN_44 -to xa[9]
set_location_assignment PIN_45 -to xa[8]
set_location_assignment PIN_48 -to n_m1
set_location_assignment PIN_50 -to n_wr
set_location_assignment PIN_51 -to n_rfsh
set_location_assignment PIN_52 -to n_mreq
set_location_assignment PIN_53 -to xa[12]
set_location_assignment PIN_55 -to xa[7]
set_location_assignment PIN_57 -to xa[6]
set_location_assignment PIN_58 -to xa[4]
set_location_assignment PIN_59 -to xa[3]
set_location_assignment PIN_60 -to xa[2]
set_location_assignment PIN_61 -to rst_n
set_location_assignment PIN_62 -to xa[1]
set_location_assignment PIN_63 -to xa[0]
set_location_assignment PIN_66 -to n_iorqge
set_location_assignment PIN_67 -to xa[5]
set_location_assignment PIN_68 -to xd[0]
set_location_assignment PIN_69 -to xd[1]
set_location_assignment PIN_70 -to xd[2]
set_location_assignment PIN_71 -to clkcpu
set_location_assignment PIN_72 -to xa[13]
set_location_assignment PIN_73 -to n_clkcpu
set_location_assignment PIN_75 -to n_rstcpu
set_location_assignment PIN_76 -to n_nmi
set_location_assignment PIN_77 -to n_int
set_location_assignment PIN_78 -to ay_abc
set_location_assignment PIN_79 -to ay_mono
set_location_assignment PIN_80 -to tape_in
set_location_assignment PIN_84 -to snd_l
set_location_assignment PIN_85 -to snd_r
set_location_assignment PIN_86 -to ay_bc1
set_location_assignment PIN_87 -to n_joy_up
set_location_assignment PIN_88 -to ay_clk
set_location_assignment PIN_89 -to ay_bdir
set_location_assignment PIN_91 -to n_joy_b1
set_location_assignment PIN_93 -to n_joy_down
set_location_assignment PIN_94 -to n_joy_left
set_location_assignment PIN_95 -to n_joy_right
set_location_assignment PIN_96 -to n_joy_b2
set_location_assignment PIN_97 -to n_joy_b3
set_location_assignment PIN_98 -to csync
set_location_assignment PIN_101 -to g[0]
set_location_assignment PIN_102 -to b[0]
set_location_assignment PIN_103 -to hsync
set_location_assignment PIN_104 -to vsync
set_location_assignment PIN_105 -to r[0]
set_location_assignment PIN_106 -to r[1]
set_location_assignment PIN_107 -to g[1]
set_location_assignment PIN_108 -to b[1]
set_location_assignment PIN_109 -to vd[3]
set_location_assignment PIN_110 -to vd[4]
set_location_assignment PIN_111 -to vd[5]
set_location_assignment PIN_112 -to vd[6]
set_location_assignment PIN_113 -to vd[7]
set_location_assignment PIN_114 -to va[10]
set_location_assignment PIN_117 -to n_vrd
set_location_assignment PIN_118 -to va[11]
set_location_assignment PIN_119 -to va[9]
set_location_assignment PIN_120 -to va[8]
set_location_assignment PIN_121 -to va[13]
set_location_assignment PIN_122 -to n_vwr
set_location_assignment PIN_123 -to va[18]
set_location_assignment PIN_124 -to va[15]
set_location_assignment PIN_125 -to sd_miso
set_location_assignment PIN_127 -to sd_sck
set_location_assignment PIN_129 -to sd_mosi
set_location_assignment PIN_130 -to va[17]
set_location_assignment PIN_131 -to va[16]
set_location_assignment PIN_132 -to va[14]
set_location_assignment PIN_133 -to va[12]
set_location_assignment PIN_134 -to va[7]
set_location_assignment PIN_137 -to va[6]
set_location_assignment PIN_138 -to va[5]
set_location_assignment PIN_139 -to va[4]
set_location_assignment PIN_140 -to va[3]
set_location_assignment PIN_141 -to va[2]
set_location_assignment PIN_142 -to va[1]
set_location_assignment PIN_143 -to va[0]
set_location_assignment PIN_144 -to vd[0]
set_location_assignment PIN_18 -to clk28
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rd
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_wr
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_miso
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_magic
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_b1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_b2
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_b3
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_down
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_left
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_right
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_up
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tape_in
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_iorqge
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_m1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_mreq
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rfsh
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rstcpu
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_nmi
set_location_assignment PIN_23 -to plus3_drd
set_location_assignment PIN_21 -to plus3_mtr
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 08:15:12 April 28, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# zx_ula_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM1270T144C5
set_global_assignment -name TOP_LEVEL_ENTITY zx_ula
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:15:12 APRIL 28, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz"
set_global_assignment -name FMAX_REQUIREMENT "14.4 MHz" -section_id clk14
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clkcpu
set_instance_assignment -name CLOCK_SETTINGS clkcpu -to clkcpu
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name AUTO_LCELL_INSERTION OFF
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_global_assignment -name FMAX_REQUIREMENT "32 MHz" -section_id clk32
set_instance_assignment -name CLOCK_SETTINGS clk32 -to clk32
set_global_assignment -name FMAX_REQUIREMENT "8 MHz" -section_id clk8
set_global_assignment -name FMAX_REQUIREMENT "4 MHz" -section_id clk4
set_instance_assignment -name CLOCK_SETTINGS clk8 -to "lpm_counter:wgcnt_rtl_1|dffs[1]"
set_instance_assignment -name CLOCK_SETTINGS clk4 -to "lpm_counter:wgcnt_rtl_1|dffs[2]"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output/
set_global_assignment -name FMAX_REQUIREMENT "7.156 MHz" -section_id clk7
set_global_assignment -name DUTY_CYCLE 40 -section_id clk7
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name POWER_USE_PVA OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name SLOW_SLEW_RATE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_49 -to n_rd
set_global_assignment -name SDC_FILE clocks.sdc
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_INCLUDE_FILE util.vh
set_global_assignment -name CDF_FILE output/zx_ula.cdf
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_location_assignment PIN_1 -to vd[1]
set_location_assignment PIN_2 -to vd[2]
set_location_assignment PIN_3 -to sd_cs
set_location_assignment PIN_4 -to kd[0]
set_location_assignment PIN_5 -to kd[1]
set_location_assignment PIN_6 -to n_magic
set_location_assignment PIN_7 -to kd[4]
set_location_assignment PIN_8 -to kd[3]
set_location_assignment PIN_11 -to kd[2]
set_location_assignment PIN_12 -to sd_cd
set_location_assignment PIN_27 -to n_romcs
set_location_assignment PIN_28 -to ra[16]
set_location_assignment PIN_29 -to ra[15]
set_location_assignment PIN_30 -to ra[14]
set_location_assignment PIN_31 -to xa[14]
set_location_assignment PIN_32 -to xd[3]
set_location_assignment PIN_37 -to xa[15]
set_location_assignment PIN_38 -to xd[4]
set_location_assignment PIN_39 -to xd[5]
set_location_assignment PIN_40 -to xd[6]
set_location_assignment PIN_41 -to xd[7]
set_location_assignment PIN_42 -to xa[10]
set_location_assignment PIN_43 -to xa[11]
set_location_assignment PIN_44 -to xa[9]
set_location_assignment PIN_45 -to xa[8]
set_location_assignment PIN_48 -to n_m1
set_location_assignment PIN_50 -to n_wr
set_location_assignment PIN_51 -to n_rfsh
set_location_assignment PIN_52 -to n_mreq
set_location_assignment PIN_53 -to xa[12]
set_location_assignment PIN_55 -to xa[7]
set_location_assignment PIN_57 -to xa[6]
set_location_assignment PIN_58 -to xa[4]
set_location_assignment PIN_59 -to xa[3]
set_location_assignment PIN_60 -to xa[2]
set_location_assignment PIN_61 -to rst_n
set_location_assignment PIN_62 -to xa[1]
set_location_assignment PIN_63 -to xa[0]
set_location_assignment PIN_66 -to n_iorqge
set_location_assignment PIN_67 -to xa[5]
set_location_assignment PIN_68 -to xd[0]
set_location_assignment PIN_69 -to xd[1]
set_location_assignment PIN_70 -to xd[2]
set_location_assignment PIN_71 -to clkcpu
set_location_assignment PIN_72 -to xa[13]
set_location_assignment PIN_73 -to n_clkcpu
set_location_assignment PIN_75 -to n_rstcpu
set_location_assignment PIN_76 -to n_nmi
set_location_assignment PIN_77 -to n_int
set_location_assignment PIN_78 -to ay_abc
set_location_assignment PIN_79 -to ay_mono
set_location_assignment PIN_80 -to tape_in
set_location_assignment PIN_84 -to snd_l
set_location_assignment PIN_85 -to snd_r
set_location_assignment PIN_86 -to ay_bc1
set_location_assignment PIN_87 -to n_joy_up
set_location_assignment PIN_88 -to ay_clk
set_location_assignment PIN_89 -to ay_bdir
set_location_assignment PIN_91 -to n_joy_b1
set_location_assignment PIN_93 -to n_joy_down
set_location_assignment PIN_94 -to n_joy_left
set_location_assignment PIN_95 -to n_joy_right
set_location_assignment PIN_96 -to n_joy_b2
set_location_assignment PIN_97 -to n_joy_b3
set_location_assignment PIN_98 -to csync
set_location_assignment PIN_101 -to g[0]
set_location_assignment PIN_102 -to b[0]
set_location_assignment PIN_103 -to hsync
set_location_assignment PIN_104 -to vsync
set_location_assignment PIN_105 -to r[0]
set_location_assignment PIN_106 -to r[1]
set_location_assignment PIN_107 -to g[1]
set_location_assignment PIN_108 -to b[1]
set_location_assignment PIN_109 -to vd[3]
set_location_assignment PIN_110 -to vd[4]
set_location_assignment PIN_111 -to vd[5]
set_location_assignment PIN_112 -to vd[6]
set_location_assignment PIN_113 -to vd[7]
set_location_assignment PIN_114 -to va[10]
set_location_assignment PIN_117 -to n_vrd
set_location_assignment PIN_118 -to va[11]
set_location_assignment PIN_119 -to va[9]
set_location_assignment PIN_120 -to va[8]
set_location_assignment PIN_121 -to va[13]
set_location_assignment PIN_122 -to n_vwr
set_location_assignment PIN_123 -to va[18]
set_location_assignment PIN_124 -to va[15]
set_location_assignment PIN_125 -to sd_miso
set_location_assignment PIN_127 -to sd_sck
set_location_assignment PIN_129 -to sd_mosi
set_location_assignment PIN_130 -to va[17]
set_location_assignment PIN_131 -to va[16]
set_location_assignment PIN_132 -to va[14]
set_location_assignment PIN_133 -to va[12]
set_location_assignment PIN_134 -to va[7]
set_location_assignment PIN_137 -to va[6]
set_location_assignment PIN_138 -to va[5]
set_location_assignment PIN_139 -to va[4]
set_location_assignment PIN_140 -to va[3]
set_location_assignment PIN_141 -to va[2]
set_location_assignment PIN_142 -to va[1]
set_location_assignment PIN_143 -to va[0]
set_location_assignment PIN_144 -to vd[0]
set_location_assignment PIN_18 -to clk28
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[7]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[4]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to xd[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rd
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_wr
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_cd
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to sd_miso
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_magic
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_b1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_b2
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_b3
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_down
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_left
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_right
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_joy_up
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to tape_in
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_iorqge
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_m1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_mreq
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rfsh
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_rstcpu
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_nmi
set_location_assignment PIN_23 -to plus3_drd
set_location_assignment PIN_21 -to plus3_mtr
set_location_assignment PIN_24 -to plus3_dwr

72
cpld_tb/Makefile
View File

@ -1,36 +1,36 @@
export PATH:=/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:/cygdrive/c/Hwdev/sjasmplus/:/cygdrive/c/Dev/srec/:${PATH}
V_T80=./t80/t80n_pack.vhd ./t80/t80n.vhd ./t80/t80n_alu.vhd ./t80/t80n_mcode.vhd ./t80/t80na.vhd
V_AZ80=$(wildcard ./az80/*.v)
all: testbench_zx_ula
testbench_zx_ula: IVFLAGS+=-I./az80/ -I./t80/ -I../cpld
testbench_zx_ula: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017
testbench_zx_ula: V=testbench_zx_ula.v zx_ula.v ${V_T80}
testbench_zx_ula: rom.mem zero64.mem
testbench_memcontroller: V=testbench_memcontroller.v
# testbench_%:
# iverilog -g2005-sv ${IVFLAGS} -o $@.vvp $@.v ${V}
# vvp $@.vvp
# @rm $@.vvp
testbench_%:
test ! -d work || rm -rf work
vlib work
test ! -n "$(filter %.v,${V})" || vlog -quiet -sv $(filter %.v,${V})
test ! -n "$(filter %.vhd %.vhdl,${V})" || vcom -quiet $(filter %.vhd %.vhdl,${V})
vsim ${VSIMFLAGS} -quiet -do 'run -all' $@
rm transcript
%.bin: %.asm
sjasmplus $<
%.mem: %.bin
srec_cat $< -binary -o $@ -vmem 8
zero64.bin:
dd if=/dev/zero count=65536 bs=1 >$@
clean:
rm -rf ivl_vhdl_work/ work/ *.bin *.mem *.vcd
export PATH:=/cygdrive/c/Hwdev/modelsim181/modelsim_ase/win32aloem:/cygdrive/c/Hwdev/iverilog/bin/:/cygdrive/c/Hwdev/sjasmplus/:/cygdrive/c/Dev/srec/:${PATH}
V_T80=./t80/t80n_pack.vhd ./t80/t80n.vhd ./t80/t80n_alu.vhd ./t80/t80n_mcode.vhd ./t80/t80na.vhd
V_AZ80=$(wildcard ./az80/*.v)
all: testbench_zx_ula
testbench_zx_ula: IVFLAGS+=-I./az80/ -I./t80/ -I../cpld
testbench_zx_ula: VSIMFLAGS+=+nowarn3722 +nowarn8822 +nowarn3017
testbench_zx_ula: V=testbench_zx_ula.v zx_ula.v ${V_T80}
testbench_zx_ula: rom.mem zero64.mem
testbench_memcontroller: V=testbench_memcontroller.v
# testbench_%:
# iverilog -g2005-sv ${IVFLAGS} -o $@.vvp $@.v ${V}
# vvp $@.vvp
# @rm $@.vvp
testbench_%:
test ! -d work || rm -rf work
vlib work
test ! -n "$(filter %.v,${V})" || vlog -quiet -sv $(filter %.v,${V})
test ! -n "$(filter %.vhd %.vhdl,${V})" || vcom -quiet $(filter %.vhd %.vhdl,${V})
vsim ${VSIMFLAGS} -quiet -do 'run -all' $@
rm transcript
%.bin: %.asm
sjasmplus $<
%.mem: %.bin
srec_cat $< -binary -o $@ -vmem 8
zero64.bin:
dd if=/dev/zero count=65536 bs=1 >$@
clean:
rm -rf ivl_vhdl_work/ work/ *.bin *.mem *.vcd

138
cpld_tb/testbench_memcontroller.v
View File

@ -1,69 +1,69 @@
`timescale 1ns/1ps
module testbench_memcontroller();
reg clk;
reg val;
reg rst_n;
always begin
clk = 0;
#1 clk = 1;
#1;
end
initial begin
rst_n = 0;
#2 rst_n = 1;
end
wire n_mreq = 0;
wire n_rfsh = 1;
reg [7:0] inputs;
wire a15 = inputs[0];
wire a14 = inputs[1];
wire a13 = inputs[2];
wire conmem = inputs[3];
wire mapram = inputs[4];
wire automap = inputs[5];
wire dffd_cpm = inputs[6];
wire tb_end = inputs[7];
wire divmap = automap | conmem;
wire div_ram = (conmem == 1 && a13 == 1) || (automap == 1 && a13 == 1) || (conmem == 0 && automap == 1 && mapram == 1);
wire
n_romcs0 = (n_mreq == 0 && n_rfsh == 1 && a14 == 0 && a15 == 0 && !div_ram && !(dffd_cpm && !divmap))? 1'b0 : 1'b1;
wire
n_ramcs = (n_mreq == 0 && n_rfsh == 1 && (a14 == 1'b1 || a15 == 1'b1 || div_ram || (dffd_cpm && !divmap)))? 1'b0 : 1'b1;
wire
xn_romcs0 = (n_mreq == 0 && n_rfsh == 1 && a14 == 0 && a15 == 0 &&
((conmem == 0 && automap == 0) || (a13 == 0 && conmem == 1) || (a13 == 0 && mapram == 0)))? 1'b0 : 1'b1;
wire
xn_ramcs = (n_mreq == 0 && n_rfsh == 1 && (a14 == 1'b1 || a15 == 1'b1 ||
(conmem == 0 && automap == 1 && mapram == 1) ||
(a13 == 1 && conmem == 1) ||
(a13 == 1 && automap == 1)
) )? 1'b0 : 1'b1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
inputs <= 0;
end
else begin
if( n_romcs0 != xn_romcs0 || n_ramcs != xn_ramcs )
$display("xn_romcs=%x xn_ramcs=%x n_romcs=%x n_ramcs=%x a15=%x a14=%x a13=%x conmem=%x mapram=%x automap=%x dffd_cpm=%x",
xn_romcs0, xn_ramcs, n_romcs0, n_ramcs, a15, a14, a13, conmem, mapram, automap, dffd_cpm);
if( tb_end )
$finish;
inputs <= inputs + 1'b1;
end
end
endmodule
`timescale 1ns/1ps
module testbench_memcontroller();
reg clk;
reg val;
reg rst_n;
always begin
clk = 0;
#1 clk = 1;
#1;
end
initial begin
rst_n = 0;
#2 rst_n = 1;
end
wire n_mreq = 0;
wire n_rfsh = 1;
reg [7:0] inputs;
wire a15 = inputs[0];
wire a14 = inputs[1];
wire a13 = inputs[2];
wire conmem = inputs[3];
wire mapram = inputs[4];
wire automap = inputs[5];
wire dffd_cpm = inputs[6];
wire tb_end = inputs[7];
wire divmap = automap | conmem;
wire div_ram = (conmem == 1 && a13 == 1) || (automap == 1 && a13 == 1) || (conmem == 0 && automap == 1 && mapram == 1);
wire
n_romcs0 = (n_mreq == 0 && n_rfsh == 1 && a14 == 0 && a15 == 0 && !div_ram && !(dffd_cpm && !divmap))? 1'b0 : 1'b1;
wire
n_ramcs = (n_mreq == 0 && n_rfsh == 1 && (a14 == 1'b1 || a15 == 1'b1 || div_ram || (dffd_cpm && !divmap)))? 1'b0 : 1'b1;
wire
xn_romcs0 = (n_mreq == 0 && n_rfsh == 1 && a14 == 0 && a15 == 0 &&
((conmem == 0 && automap == 0) || (a13 == 0 && conmem == 1) || (a13 == 0 && mapram == 0)))? 1'b0 : 1'b1;
wire
xn_ramcs = (n_mreq == 0 && n_rfsh == 1 && (a14 == 1'b1 || a15 == 1'b1 ||
(conmem == 0 && automap == 1 && mapram == 1) ||
(a13 == 1 && conmem == 1) ||
(a13 == 1 && automap == 1)
) )? 1'b0 : 1'b1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
inputs <= 0;
end
else begin
if( n_romcs0 != xn_romcs0 || n_ramcs != xn_ramcs )
$display("xn_romcs=%x xn_ramcs=%x n_romcs=%x n_ramcs=%x a15=%x a14=%x a13=%x conmem=%x mapram=%x automap=%x dffd_cpm=%x",
xn_romcs0, xn_ramcs, n_romcs0, n_ramcs, a15, a14, a13, conmem, mapram, automap, dffd_cpm);
if( tb_end )
$finish;
inputs <= inputs + 1'b1;
end
end
endmodule

548
cpld_tb/testbench_zx_ula.rev.A.v
View File

@ -1,274 +1,274 @@
`define USE_FPGA
`include "../cpld/rev.A/top.v"
`timescale 100ps/10ps
module testbench_zx_ula();
reg rst_n;
reg clk32;
reg clk28;
reg clk14;
/* CPU */
wire clkcpu;
wire [15:0] a_cpu, a_cpu_cpu;
wire [7:0] d_cpu_o, d_cpu_i;
wire n_rd, n_rd_cpu;
wire n_wr, n_wr_cpu;
wire n_iorq, n_iorq_cpu;
wire n_mreq, n_mreq_cpu;
wire n_m1, n_m1_cpu;
wire n_rfsh, n_rfsh_cpu;
wire n_int;
wire n_nmi;
T80na cpu1(
.RESET_n(rst_n),
.CLK_n(clkcpu),
.WAIT_n(1'b1),
.INT_n(n_int),
.NMI_n(n_nmi),
.BUSRQ_n(1'b1),
.M1_n(n_m1_cpu),
.MREQ_n(n_mreq_cpu),
.IORQ_n(n_iorq_cpu),
.RD_n(n_rd_cpu),
.WR_n(n_wr_cpu),
.RFSH_n(n_rfsh_cpu),
.A(a_cpu_cpu),
.D_i(d_cpu_i),
.D_o(d_cpu_o)
);
/* ULA */
wire [7:0] vd;
wire [18:0] va;
wire [16:14] ra;
wire m_romcs;
wire n_vrd;
wire n_vwr;
wire vaout;
wire vaout_7;
wire vdout;
wire n_iorqge;
reg n_magic;
reg fd_rdat;
reg vg_wd;
reg vg_tr43;
reg vg_sl;
reg vg_sr;
zx_ula zx_ula1(
.rst_n(rst_n),
.clk14(clk14),
// .clk28(clk28),
// .clk32(clk32),
.clkcpu(clkcpu),
.vd(vd),
.va(va),
.ra(ra),
.a13(a_cpu[13]),
.a14(a_cpu[14]),
.a15(a_cpu[15]),
.n_rd(n_rd),
.n_wr(n_wr),
.n_iorq(n_iorq),
.n_mreq(n_mreq),
.n_m1(n_m1),
.n_rfsh(n_rfsh),
.n_romcs(n_romcs),
.n_vrd(n_vrd),
.n_vwr(n_vwr),
.n_int(n_int),
.n_nmi(n_nmi),
.n_iorqge_o(n_iorqge),
.n_iorqge_i(n_iorqge),
.n_magic(n_magic),
.tape_in(1'b1),
.kd(5'b0),
.sd_cd(1'b0),
.sd_miso(1'b0),
.fd_rdat(fd_rdat),
.vg_drq(1'b0),
.vg_wf_de(1'b0),
.vg_wd(vg_wd),
.vg_tr43(vg_tr43),
.vg_sl(vg_sl),
.vg_sr(vg_sr),
.vaout(vaout),
.vaout_8(vaout_8),
.vdout(vdout)
);
/* MEMORY */
reg [7:0] rom [0:16383];
wire [13:0] rom_addr;
reg [13:0] rom_addr0;
wire [7:0] rom_q = rom[rom_addr0];
always @(posedge clk14) begin
rom_addr0 <= rom_addr;
end
initial begin
$readmemh("rom.mem", rom);
end
reg [7:0] ram [0:65535];
wire [15:0] ram_addr_a;
reg [15:0] ram_addr_a0;
wire [7:0] ram_q_a = ram[ram_addr_a0];
always @(posedge clk14) begin
if (n_vwr == 0) begin
ram[ram_addr_a] <= vd;
end
ram_addr_a0 <= ram_addr_a;
end
initial begin
$readmemh("zero64.mem", ram);
end
/* BUS ARBITER */
assign rom_addr = {ra[14],a_cpu[13:0]};
assign ram_addr_a = va[15:0];
assign va =
vaout_8? {{11{1'bz}}, a_cpu[7:0]} :
vaout? {19{1'bz}} :
{{6{1'bz}}, a_cpu[12:0]};
assign vd =
~n_vrd? ram_q_a :
vdout? {8{1'bz}} :
~n_wr? d_cpu_o :
~n_romcs? rom_q :
{8{1'bz}};
assign d_cpu_i =
~n_wr? d_cpu_o :
~n_romcs? rom_q :
vd;
/* CPU SIGNALS (ideal timings) */
// assign n_rd = n_rd_cpu;
// assign n_wr = n_wr_cpu;
// assign n_iorq = n_iorq_cpu;
// assign n_mreq = n_mreq_cpu;
// assign n_m1 = n_m1_cpu;
// assign n_rfsh = n_rfsh_cpu;
// assign a_cpu = a_cpu_cpu;
/* CPU SIGNALS (Z84C0008 timings) */
assign #600 n_rd = n_rd_cpu; //TdCf(RDf)
assign #600 n_wr = n_wr_cpu; //TdCf(WRf)
assign #550 n_iorq = n_iorq_cpu; //TdCr(IORQf)
assign #600 n_mreq = n_mreq_cpu; //TdCf(MREQf)
assign #700 n_m1 = n_m1_cpu; //TdCr(M1f)
assign #950 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
assign #800 a_cpu = a_cpu_cpu; //TdCr(A)
/* CPU SIGNALS (Z84C0004 timings) */
// assign #850 n_rd = n_rd_cpu; //TdCf(RDf)
// assign #800 n_wr = n_wr_cpu; //TdCf(WRf)
// assign #750 n_iorq = n_iorq_cpu; //TdCr(IORQf)
// assign #850 n_mreq = n_mreq_cpu; //TdCf(MREQf)
// assign #1000 n_m1 = n_m1_cpu; //TdCr(M1f)
// assign #1300 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
// assign #1100 a_cpu = a_cpu_cpu; //TdCr(A)
/* SIMULATION SIGNALS */
initial begin
n_magic = 1;
#500000
n_magic = 0;
#500000
n_magic = 1;
end
always begin
fd_rdat = 1;
#303000 fd_rdat = 0;
#5000;
end
always begin
vg_wd = 0;
vg_tr43 = 0;
vg_sl = 0;
vg_sr = 0;
#303000
vg_wd = 1;
#4000
vg_wd = 0;
#300750
vg_tr43 = 1;
vg_sl = 1;
#1250
vg_wd = 1;
#3500
vg_sl = 0;
vg_tr43 = 0;
#500
vg_wd = 0;
#300750
vg_tr43 = 1;
vg_sr = 1;
#1250
vg_wd = 1;
#3500
vg_sr = 0;
vg_tr43 = 0;
#500
vg_wd = 0;
end
/* CLOCKS & RESET */
initial begin
rst_n = 0;
#3000 rst_n = 1;
end
always begin
clk14 = 0;
#357 clk14 = 1;
#358;
end
always begin
clk28 = 0;
#178 clk28 = 1;
#179;
end
always begin
clk32 = 0;
#156 clk32 = 1;
#156;
end
/* TESTBENCH CONTROL */
initial begin
$dumpfile("testbench_zx_ula.vcd");
$dumpvars();
#5000000 $finish;
//#21000000 $finish;
end
always @(clk14) begin
// if (v > 100) $dumpoff;
// if (~n_iorq) $dumpon;
// if (v == 1 && ovf == 1) $finish;
end
endmodule
`define USE_FPGA
`include "../cpld/rev.A/top.v"
`timescale 100ps/10ps
module testbench_zx_ula();
reg rst_n;
reg clk32;
reg clk28;
reg clk14;
/* CPU */
wire clkcpu;
wire [15:0] a_cpu, a_cpu_cpu;
wire [7:0] d_cpu_o, d_cpu_i;
wire n_rd, n_rd_cpu;
wire n_wr, n_wr_cpu;
wire n_iorq, n_iorq_cpu;
wire n_mreq, n_mreq_cpu;
wire n_m1, n_m1_cpu;
wire n_rfsh, n_rfsh_cpu;
wire n_int;
wire n_nmi;
T80na cpu1(
.RESET_n(rst_n),
.CLK_n(clkcpu),
.WAIT_n(1'b1),
.INT_n(n_int),
.NMI_n(n_nmi),
.BUSRQ_n(1'b1),
.M1_n(n_m1_cpu),
.MREQ_n(n_mreq_cpu),
.IORQ_n(n_iorq_cpu),
.RD_n(n_rd_cpu),
.WR_n(n_wr_cpu),
.RFSH_n(n_rfsh_cpu),
.A(a_cpu_cpu),
.D_i(d_cpu_i),
.D_o(d_cpu_o)
);
/* ULA */
wire [7:0] vd;
wire [18:0] va;
wire [16:14] ra;
wire m_romcs;
wire n_vrd;
wire n_vwr;
wire vaout;
wire vaout_7;
wire vdout;
wire n_iorqge;
reg n_magic;
reg fd_rdat;
reg vg_wd;
reg vg_tr43;
reg vg_sl;
reg vg_sr;
zx_ula zx_ula1(
.rst_n(rst_n),
.clk14(clk14),
// .clk28(clk28),
// .clk32(clk32),
.clkcpu(clkcpu),
.vd(vd),
.va(va),
.ra(ra),
.a13(a_cpu[13]),
.a14(a_cpu[14]),
.a15(a_cpu[15]),
.n_rd(n_rd),
.n_wr(n_wr),
.n_iorq(n_iorq),
.n_mreq(n_mreq),
.n_m1(n_m1),
.n_rfsh(n_rfsh),
.n_romcs(n_romcs),
.n_vrd(n_vrd),
.n_vwr(n_vwr),
.n_int(n_int),
.n_nmi(n_nmi),
.n_iorqge_o(n_iorqge),
.n_iorqge_i(n_iorqge),
.n_magic(n_magic),
.tape_in(1'b1),
.kd(5'b0),
.sd_cd(1'b0),
.sd_miso(1'b0),
.fd_rdat(fd_rdat),
.vg_drq(1'b0),
.vg_wf_de(1'b0),
.vg_wd(vg_wd),
.vg_tr43(vg_tr43),
.vg_sl(vg_sl),
.vg_sr(vg_sr),
.vaout(vaout),
.vaout_8(vaout_8),
.vdout(vdout)
);
/* MEMORY */
reg [7:0] rom [0:16383];
wire [13:0] rom_addr;
reg [13:0] rom_addr0;
wire [7:0] rom_q = rom[rom_addr0];
always @(posedge clk14) begin
rom_addr0 <= rom_addr;
end
initial begin
$readmemh("rom.mem", rom);
end
reg [7:0] ram [0:65535];
wire [15:0] ram_addr_a;
reg [15:0] ram_addr_a0;
wire [7:0] ram_q_a = ram[ram_addr_a0];
always @(posedge clk14) begin
if (n_vwr == 0) begin
ram[ram_addr_a] <= vd;
end
ram_addr_a0 <= ram_addr_a;
end
initial begin
$readmemh("zero64.mem", ram);
end
/* BUS ARBITER */
assign rom_addr = {ra[14],a_cpu[13:0]};
assign ram_addr_a = va[15:0];
assign va =
vaout_8? {{11{1'bz}}, a_cpu[7:0]} :
vaout? {19{1'bz}} :
{{6{1'bz}}, a_cpu[12:0]};
assign vd =
~n_vrd? ram_q_a :
vdout? {8{1'bz}} :
~n_wr? d_cpu_o :
~n_romcs? rom_q :
{8{1'bz}};
assign d_cpu_i =
~n_wr? d_cpu_o :
~n_romcs? rom_q :
vd;
/* CPU SIGNALS (ideal timings) */
// assign n_rd = n_rd_cpu;
// assign n_wr = n_wr_cpu;
// assign n_iorq = n_iorq_cpu;
// assign n_mreq = n_mreq_cpu;
// assign n_m1 = n_m1_cpu;
// assign n_rfsh = n_rfsh_cpu;
// assign a_cpu = a_cpu_cpu;
/* CPU SIGNALS (Z84C0008 timings) */
assign #600 n_rd = n_rd_cpu; //TdCf(RDf)
assign #600 n_wr = n_wr_cpu; //TdCf(WRf)
assign #550 n_iorq = n_iorq_cpu; //TdCr(IORQf)
assign #600 n_mreq = n_mreq_cpu; //TdCf(MREQf)
assign #700 n_m1 = n_m1_cpu; //TdCr(M1f)
assign #950 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
assign #800 a_cpu = a_cpu_cpu; //TdCr(A)
/* CPU SIGNALS (Z84C0004 timings) */
// assign #850 n_rd = n_rd_cpu; //TdCf(RDf)
// assign #800 n_wr = n_wr_cpu; //TdCf(WRf)
// assign #750 n_iorq = n_iorq_cpu; //TdCr(IORQf)
// assign #850 n_mreq = n_mreq_cpu; //TdCf(MREQf)
// assign #1000 n_m1 = n_m1_cpu; //TdCr(M1f)
// assign #1300 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
// assign #1100 a_cpu = a_cpu_cpu; //TdCr(A)
/* SIMULATION SIGNALS */
initial begin
n_magic = 1;
#500000
n_magic = 0;
#500000
n_magic = 1;
end
always begin
fd_rdat = 1;
#303000 fd_rdat = 0;
#5000;
end
always begin
vg_wd = 0;
vg_tr43 = 0;
vg_sl = 0;
vg_sr = 0;
#303000
vg_wd = 1;
#4000
vg_wd = 0;
#300750
vg_tr43 = 1;
vg_sl = 1;
#1250
vg_wd = 1;
#3500
vg_sl = 0;
vg_tr43 = 0;
#500
vg_wd = 0;
#300750
vg_tr43 = 1;
vg_sr = 1;
#1250
vg_wd = 1;
#3500
vg_sr = 0;
vg_tr43 = 0;
#500
vg_wd = 0;
end
/* CLOCKS & RESET */
initial begin
rst_n = 0;
#3000 rst_n = 1;
end
always begin
clk14 = 0;
#357 clk14 = 1;
#358;
end
always begin
clk28 = 0;
#178 clk28 = 1;
#179;
end
always begin
clk32 = 0;
#156 clk32 = 1;
#156;
end
/* TESTBENCH CONTROL */
initial begin
$dumpfile("testbench_zx_ula.vcd");
$dumpvars();
#5000000 $finish;
//#21000000 $finish;
end
always @(clk14) begin
// if (v > 100) $dumpoff;
// if (~n_iorq) $dumpon;
// if (v == 1 && ovf == 1) $finish;
end
endmodule

396
cpld_tb/testbench_zx_ula.v
View File

@ -1,198 +1,198 @@
`timescale 100ps/10ps
module testbench_zx_ula();
reg rst_n;
reg clk28;
/* CPU */
wire clkcpu;
wire [15:0] a_cpu, a_cpu_cpu;
wire [7:0] d_cpu_o, d_cpu_i;
wire n_rd, n_rd_cpu;
wire n_wr, n_wr_cpu;
wire n_iorq, n_iorq_cpu;
wire n_mreq, n_mreq_cpu;
wire n_m1, n_m1_cpu;
wire n_rfsh, n_rfsh_cpu;
wire n_int;
wire n_nmi;
T80na cpu1(
.RESET_n(rst_n),
.CLK_n(clkcpu),
.WAIT_n(1'b1),
.INT_n(n_int),
.NMI_n(n_nmi),
.BUSRQ_n(1'b1),
.M1_n(n_m1_cpu),
.MREQ_n(n_mreq_cpu),
.IORQ_n(n_iorq_cpu),
.RD_n(n_rd_cpu),
.WR_n(n_wr_cpu),
.RFSH_n(n_rfsh_cpu),
.A(a_cpu_cpu),
.D_i(d_cpu_i),
.D_o(d_cpu_o)
);
/* ULA */
wire [7:0] vd;
wire [7:0] d_ula;
wire [18:0] va;
wire [16:14] ra;
wire m_romcs;
wire n_vrd;
wire n_vwr;
wire dout;
wire vdout;
wire n_iorqge;
reg n_magic;
zx_ula zx_ula1(
.rst_n(rst_n),
.clk28(clk28),
.clkcpu(clkcpu),
.vd(vd),
.va(va),
.ra(ra),
.xa(a_cpu),
.xd(d_ula),
.n_rd(n_rd),
.n_wr(n_wr),
.n_iorqge(n_iorq),
.n_mreq(n_mreq),
.n_m1(n_m1),
.n_rfsh(n_rfsh),
.n_romcs(n_romcs),
.n_vrd(n_vrd),
.n_vwr(n_vwr),
.n_int(n_int),
.n_nmi(n_nmi),
.n_magic(n_magic),
.tape_in(1'b1),
.kd(5'b0),
.sd_cd(1'b0),
.sd_miso(1'b0),
.dout(dout),
.vdout(vdout)
);
/* MEMORY */
reg [7:0] rom [0:16383];
wire [13:0] rom_addr;
reg [13:0] rom_addr0;
wire [7:0] rom_q = rom[rom_addr0];
always @(posedge clk28) begin
rom_addr0 <= rom_addr;
end
initial begin
$readmemh("rom.mem", rom);
end
reg [7:0] ram [0:65535];
wire [15:0] ram_addr_a;
reg [15:0] ram_addr_a0;
wire [7:0] ram_q_a = ram[ram_addr_a0];
always @(posedge clk28) begin
if (n_vwr == 0) begin
ram[ram_addr_a] <= vd;
end
ram_addr_a0 <= ram_addr_a;
end
initial begin
$readmemh("zero64.mem", ram);
end
/* BUS ARBITER */
assign rom_addr = {ra[14],a_cpu[13:0]};
assign ram_addr_a = va[15:0];
assign vd =
~n_vrd? ram_q_a :
{8{1'bz}};
assign d_ula =
dout? {8{1'bz}} :
~n_wr? d_cpu_o :
~n_romcs? rom_q :
{8{1'bz}};
assign d_cpu_i =
~n_wr? d_cpu_o :
~n_romcs? rom_q :
d_ula;
/* CPU SIGNALS (ideal timings) */
// assign n_rd = n_rd_cpu;
// assign n_wr = n_wr_cpu;
// assign n_iorq = n_iorq_cpu;
// assign n_mreq = n_mreq_cpu;
// assign n_m1 = n_m1_cpu;
// assign n_rfsh = n_rfsh_cpu;
// assign a_cpu = a_cpu_cpu;
/* CPU SIGNALS (Z84C0008 timings) */
assign #600 n_rd = n_rd_cpu; //TdCf(RDf)
assign #600 n_wr = n_wr_cpu; //TdCf(WRf)
assign #550 n_iorq = n_iorq_cpu; //TdCr(IORQf)
assign #600 n_mreq = n_mreq_cpu; //TdCf(MREQf)
assign #700 n_m1 = n_m1_cpu; //TdCr(M1f)
assign #950 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
assign #800 a_cpu = a_cpu_cpu; //TdCr(A)
/* CPU SIGNALS (Z84C0004 timings) */
// assign #850 n_rd = n_rd_cpu; //TdCf(RDf)
// assign #800 n_wr = n_wr_cpu; //TdCf(WRf)
// assign #750 n_iorq = n_iorq_cpu; //TdCr(IORQf)
// assign #850 n_mreq = n_mreq_cpu; //TdCf(MREQf)
// assign #1000 n_m1 = n_m1_cpu; //TdCr(M1f)
// assign #1300 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
// assign #1100 a_cpu = a_cpu_cpu; //TdCr(A)
/* SIMULATION SIGNALS */
initial begin
n_magic = 1;
#500000
n_magic = 0;
#500000
n_magic = 1;
end
/* CLOCKS & RESET */
initial begin
rst_n = 0;
#3000 rst_n = 1;
end
always begin
clk28 = 0;
#178 clk28 = 1;
#179;
end
/* TESTBENCH CONTROL */
initial begin
$dumpfile("testbench_zx_ula.vcd");
$dumpvars();
#5000000 $finish;
//#21000000 $finish;
end
always @(clk28) begin
// if (v > 100) $dumpoff;
// if (~n_iorq) $dumpon;
// if (v == 1 && ovf == 1) $finish;
end
endmodule
`timescale 100ps/10ps
module testbench_zx_ula();
reg rst_n;
reg clk28;
/* CPU */
wire clkcpu;
wire [15:0] a_cpu, a_cpu_cpu;
wire [7:0] d_cpu_o, d_cpu_i;
wire n_rd, n_rd_cpu;
wire n_wr, n_wr_cpu;
wire n_iorq, n_iorq_cpu;
wire n_mreq, n_mreq_cpu;
wire n_m1, n_m1_cpu;
wire n_rfsh, n_rfsh_cpu;
wire n_int;
wire n_nmi;
T80na cpu1(
.RESET_n(rst_n),
.CLK_n(clkcpu),
.WAIT_n(1'b1),
.INT_n(n_int),
.NMI_n(n_nmi),
.BUSRQ_n(1'b1),
.M1_n(n_m1_cpu),
.MREQ_n(n_mreq_cpu),
.IORQ_n(n_iorq_cpu),
.RD_n(n_rd_cpu),
.WR_n(n_wr_cpu),
.RFSH_n(n_rfsh_cpu),
.A(a_cpu_cpu),
.D_i(d_cpu_i),
.D_o(d_cpu_o)
);
/* ULA */
wire [7:0] vd;
wire [7:0] d_ula;
wire [18:0] va;
wire [16:14] ra;
wire m_romcs;
wire n_vrd;
wire n_vwr;
wire dout;
wire vdout;
wire n_iorqge;
reg n_magic;
zx_ula zx_ula1(
.rst_n(rst_n),
.clk28(clk28),
.clkcpu(clkcpu),
.vd(vd),
.va(va),
.ra(ra),
.xa(a_cpu),
.xd(d_ula),
.n_rd(n_rd),
.n_wr(n_wr),
.n_iorqge(n_iorq),
.n_mreq(n_mreq),
.n_m1(n_m1),
.n_rfsh(n_rfsh),
.n_romcs(n_romcs),
.n_vrd(n_vrd),
.n_vwr(n_vwr),
.n_int(n_int),
.n_nmi(n_nmi),
.n_magic(n_magic),
.tape_in(1'b1),
.kd(5'b0),
.sd_cd(1'b0),
.sd_miso(1'b0),
.dout(dout),
.vdout(vdout)
);
/* MEMORY */
reg [7:0] rom [0:16383];
wire [13:0] rom_addr;
reg [13:0] rom_addr0;
wire [7:0] rom_q = rom[rom_addr0];
always @(posedge clk28) begin
rom_addr0 <= rom_addr;
end
initial begin
$readmemh("rom.mem", rom);
end
reg [7:0] ram [0:65535];
wire [15:0] ram_addr_a;
reg [15:0] ram_addr_a0;
wire [7:0] ram_q_a = ram[ram_addr_a0];
always @(posedge clk28) begin
if (n_vwr == 0) begin
ram[ram_addr_a] <= vd;
end
ram_addr_a0 <= ram_addr_a;
end
initial begin
$readmemh("zero64.mem", ram);
end
/* BUS ARBITER */
assign rom_addr = {ra[14],a_cpu[13:0]};
assign ram_addr_a = va[15:0];
assign vd =
~n_vrd? ram_q_a :
{8{1'bz}};
assign d_ula =
dout? {8{1'bz}} :
~n_wr? d_cpu_o :
~n_romcs? rom_q :
{8{1'bz}};
assign d_cpu_i =
~n_wr? d_cpu_o :
~n_romcs? rom_q :
d_ula;
/* CPU SIGNALS (ideal timings) */
// assign n_rd = n_rd_cpu;
// assign n_wr = n_wr_cpu;
// assign n_iorq = n_iorq_cpu;
// assign n_mreq = n_mreq_cpu;
// assign n_m1 = n_m1_cpu;
// assign n_rfsh = n_rfsh_cpu;
// assign a_cpu = a_cpu_cpu;
/* CPU SIGNALS (Z84C0008 timings) */
assign #600 n_rd = n_rd_cpu; //TdCf(RDf)
assign #600 n_wr = n_wr_cpu; //TdCf(WRf)
assign #550 n_iorq = n_iorq_cpu; //TdCr(IORQf)
assign #600 n_mreq = n_mreq_cpu; //TdCf(MREQf)
assign #700 n_m1 = n_m1_cpu; //TdCr(M1f)
assign #950 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
assign #800 a_cpu = a_cpu_cpu; //TdCr(A)
/* CPU SIGNALS (Z84C0004 timings) */
// assign #850 n_rd = n_rd_cpu; //TdCf(RDf)
// assign #800 n_wr = n_wr_cpu; //TdCf(WRf)
// assign #750 n_iorq = n_iorq_cpu; //TdCr(IORQf)
// assign #850 n_mreq = n_mreq_cpu; //TdCf(MREQf)
// assign #1000 n_m1 = n_m1_cpu; //TdCr(M1f)
// assign #1300 n_rfsh = n_rfsh_cpu; //TdCr(RFSHf)
// assign #1100 a_cpu = a_cpu_cpu; //TdCr(A)
/* SIMULATION SIGNALS */
initial begin
n_magic = 1;
#500000
n_magic = 0;
#500000
n_magic = 1;
end
/* CLOCKS & RESET */
initial begin
rst_n = 0;
#3000 rst_n = 1;
end
always begin
clk28 = 0;
#178 clk28 = 1;
#179;
end
/* TESTBENCH CONTROL */
initial begin
$dumpfile("testbench_zx_ula.vcd");
$dumpvars();
#5000000 $finish;
//#21000000 $finish;
end
always @(clk28) begin
// if (v > 100) $dumpoff;
// if (~n_iorq) $dumpon;
// if (v == 1 && ovf == 1) $finish;
end
endmodule

4
cpld_tb/zx_ula.v
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@ -1,2 +1,2 @@
`define USE_FPGA
`include "../cpld/rev.C/top.v"
`define USE_FPGA
`include "../cpld/rev.C/top.v"

38
pcb/rev.A/ERRATA.ru.txt
View File

@ -1,19 +1,19 @@
- К ножке 22 микросхемы SRAM (U11) подключен VCC, должен быть GND
- К ножке 6 микросхемы ВГ93 (U12) подключен A8, должен быть A6
- CPUCLK нужно подтянуть к VCC через резистор 2.2k
- RSTCPU нужно подтянуть к VCC через резистор 10k
- Параллельно R71/C41, R72/C42 добавить резисторы 1k на землю, R80, R89 можно не впаивать
- Нерабочая схема подключения динамика, не впаивать Q4, R65, R55, RV1, LS1
- К ножке 132 CPLD (U11) нужно припаять сигнал A13, R41 не впаивать
- Вход магнитофона ловит шумы из космоса, ножку 3 LM311 (U5) нужно притянуть к GND через резистор 3M
- Неверная цоколёвка посадочного места у всех транзисторов - БЭК, должно быть КБЭ
- Разъём клавиатуры J1 не влезает если подключен шлейф флоппи
- Разъём джойстика J7 не влезает в корпус резинки без модификации корпуса
- Резистор R20 мешает установке разъёма клавиатуры J3, нужно припаивать резистор снизу
- Неверная распиновка разъёма J6 (Kempston)
- Неверная распиновка разъёма J8 (EGA)
- Схема сброса: R21 заменить на перемычку, R22 не впаивать
- Разъёмы SW2, SW3 не влезают по высоте, нужно впаивать угловые
- Перепутаны каналы A и B в цоколёвке AY (U13)
- В U4 нет необходимости, можно не запаивать. Ножки 7-6, 11-12, 5-4, 3-2, 9-10, 14-15 соединить перемычками
- C30, C32 не влезают по высоте, нужно устанавливать лёжа
- К ножке 22 микросхемы SRAM (U11) подключен VCC, должен быть GND
- К ножке 6 микросхемы ВГ93 (U12) подключен A8, должен быть A6
- CPUCLK нужно подтянуть к VCC через резистор 2.2k
- RSTCPU нужно подтянуть к VCC через резистор 10k
- Параллельно R71/C41, R72/C42 добавить резисторы 1k на землю, R80, R89 можно не впаивать
- Нерабочая схема подключения динамика, не впаивать Q4, R65, R55, RV1, LS1
- К ножке 132 CPLD (U11) нужно припаять сигнал A13, R41 не впаивать
- Вход магнитофона ловит шумы из космоса, ножку 3 LM311 (U5) нужно притянуть к GND через резистор 3M
- Неверная цоколёвка посадочного места у всех транзисторов - БЭК, должно быть КБЭ
- Разъём клавиатуры J1 не влезает если подключен шлейф флоппи
- Разъём джойстика J7 не влезает в корпус резинки без модификации корпуса
- Резистор R20 мешает установке разъёма клавиатуры J3, нужно припаивать резистор снизу
- Неверная распиновка разъёма J6 (Kempston)
- Неверная распиновка разъёма J8 (EGA)
- Схема сброса: R21 заменить на перемычку, R22 не впаивать
- Разъёмы SW2, SW3 не влезают по высоте, нужно впаивать угловые
- Перепутаны каналы A и B в цоколёвке AY (U13)
- В U4 нет необходимости, можно не запаивать. Ножки 7-6, 11-12, 5-4, 3-2, 9-10, 14-15 соединить перемычками
- C30, C32 не влезают по высоте, нужно устанавливать лёжа

3236
pcb/rev.A/sizif512-cache.lib
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33474
pcb/rev.A/sizif512.kicad_pcb
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File diff suppressed because it is too large Load Diff

546
pcb/rev.A/sizif512.pro
View File

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15860
pcb/rev.A/sizif512.sch
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3618
pcb/rev.B/sizif512-cache.lib
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File diff suppressed because it is too large Load Diff

33476
pcb/rev.B/sizif512.kicad_pcb
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File diff suppressed because it is too large Load Diff

546
pcb/rev.B/sizif512.pro
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@ -1,273 +1,273 @@
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[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.5
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Hipower
Clearance=0.2
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.2
TrackWidth=0.5
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=${MYLIBPATH}/mykicadws.kicad_wks
PlotDirectoryName=out/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=39
ERC_TestSimilarLabels=1
update=06/07/2020 22:31:45
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.45
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
TrackWidth2=0.2
TrackWidth3=0.5
TrackWidth4=1
ViaDiameter1=0.5
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.5
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Hipower
Clearance=0.2
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.2
TrackWidth=0.5
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=${MYLIBPATH}/mykicadws.kicad_wks
PlotDirectoryName=out/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=39
ERC_TestSimilarLabels=1

16114
pcb/rev.B/sizif512.sch
View File

File diff suppressed because it is too large Load Diff

6
pcb/rev.C/ERRATA.txt
View File

@ -1,3 +1,3 @@
- JTAG pinout differs from Altera standard
- Incorrect silkscreen for J3 header
- R5 should not be installed (this improves compatibility with some addons like Dandanator mini)
- JTAG pinout differs from Altera standard
- Incorrect silkscreen for J3 header
- R5 should not be installed (this improves compatibility with some addons like Dandanator mini)

3390
pcb/rev.C/sizif512-cache.lib
View File

File diff suppressed because it is too large Load Diff

43176
pcb/rev.C/sizif512.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

550
pcb/rev.C/sizif512.pro
View File

@ -1,275 +1,275 @@
update=05/07/2020 10:25:14
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.45
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
TrackWidth2=0.2
TrackWidth3=0.5
TrackWidth4=1
TrackWidth5=2
TrackWidth6=3
ViaDiameter1=0.5
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.5
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Hipower
Clearance=0.2
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.2
TrackWidth=0.5
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=${MYLIBPATH}/mykicadws.kicad_wks
PlotDirectoryName=out/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=39
ERC_TestSimilarLabels=1
update=05/07/2020 10:25:14
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.45
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
TrackWidth2=0.2
TrackWidth3=0.5
TrackWidth4=1
TrackWidth5=2
TrackWidth6=3
ViaDiameter1=0.5
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.5
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Hipower
Clearance=0.2
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.2
TrackWidth=0.5
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=${MYLIBPATH}/mykicadws.kicad_wks
PlotDirectoryName=out/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=39
ERC_TestSimilarLabels=1

14648
pcb/rev.C/sizif512.sch
View File

File diff suppressed because it is too large Load Diff

2
pcb/rev.C1/ERRATA.txt
View File

@ -1 +1 @@
- R5 should not be installed (this improves compatibility with some addons like Dandanator mini)
- R5 should not be installed (this improves compatibility with some addons like Dandanator mini)

3390
pcb/rev.C1/sizif512-cache.lib
View File

File diff suppressed because it is too large Load Diff

43356
pcb/rev.C1/sizif512.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

550
pcb/rev.C1/sizif512.pro
View File

@ -1,275 +1,275 @@
update=21/07/2020 21:16:33
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.45
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
TrackWidth2=0.2
TrackWidth3=0.5
TrackWidth4=1
TrackWidth5=2
TrackWidth6=3
ViaDiameter1=0.5
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.5
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Hipower
Clearance=0.2
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.2
TrackWidth=0.5
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=${MYLIBPATH}/mykicadws.kicad_wks
PlotDirectoryName=out/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=39
ERC_TestSimilarLabels=1
update=21/07/2020 21:16:33
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.45
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.2
TrackWidth2=0.2
TrackWidth3=0.5
TrackWidth4=1
TrackWidth5=2
TrackWidth6=3
ViaDiameter1=0.5
ViaDrill1=0.3
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.2
ViaDiameter=0.5
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Hipower
Clearance=0.2
TrackWidth=1
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=power
Clearance=0.2
TrackWidth=0.5
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=${MYLIBPATH}/mykicadws.kicad_wks
PlotDirectoryName=out/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=39
ERC_TestSimilarLabels=1

14652
pcb/rev.C1/sizif512.sch
View File

File diff suppressed because it is too large Load Diff

16
rom_src/Makefile
View File

@ -1,8 +1,8 @@
export PATH:=/cygdrive/c/Hwdev/sjasmplus/:/cygdrive/c/Dev/srec/:${PATH}
all: main.bin
%.bin: %.asm
sjasmplus $<
%.mem: %.bin
srec_cat $< -binary -o $@ -vmem 8
export PATH:=/cygdrive/c/Hwdev/sjasmplus/:/cygdrive/c/Dev/srec/:${PATH}
all: main.bin
%.bin: %.asm
sjasmplus $<
%.mem: %.bin
srec_cat $< -binary -o $@ -vmem 8