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12 lines
496 B
Plaintext
12 lines
496 B
Plaintext
1. Missing MREQ signal. You should wire MREQ from edge connector to TP1
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2. R2, R33 - 10K
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3. R6, R12, R30, R31 - 47k
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UPD. 2023-08-21:
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4. R20 and R34 labels on silkscreen are misplaced
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5. Incorrect 3.5mm jack footprint - left-right signals are swapped
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UPD. 2025-01-28:
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6. U21 should be 74AHCT1G125DB
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7. Missing Z80 clock buffering. CPLD produce only up to 3.3V clock, while Z80 require 5V amplitude, and that may lead to unstable GS work. It's possible to use U14 for clock buffering.
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