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https://github.com/UzixLS/ncomputing-l230.git
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84 lines
3.9 KiB
Plaintext
84 lines
3.9 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II
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# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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# Date created = 15:56:22 December 26, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# max_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY MAX3000A
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set_global_assignment -name DEVICE "EPM3128ATC100-10"
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set_global_assignment -name TOP_LEVEL_ENTITY top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:56:22 DECEMBER 26, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_87 -to clk
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set_location_assignment PIN_50 -to cy[0]
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set_location_assignment PIN_49 -to cy[1]
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set_location_assignment PIN_47 -to cy[2]
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set_location_assignment PIN_46 -to cy[3]
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set_location_assignment PIN_45 -to cy[4]
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set_location_assignment PIN_44 -to cy[5]
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set_location_assignment PIN_42 -to cy[6]
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set_location_assignment PIN_41 -to cy[7]
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set_location_assignment PIN_40 -to cy[8]
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set_location_assignment PIN_32 -to cy[9]
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set_location_assignment PIN_31 -to cy[10]
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set_location_assignment PIN_30 -to cy[11]
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set_location_assignment PIN_29 -to cy[12]
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set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
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set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id clk_50mhz
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set_instance_assignment -name CLOCK_SETTINGS clk_50mhz -to clk
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set_global_assignment -name SDC_FILE clocks.sdc
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set_global_assignment -name VERILOG_FILE top.v
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output
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set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
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set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_location_assignment PIN_22 -to flash_si
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set_location_assignment PIN_27 -to flash_reset
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set_location_assignment PIN_28 -to flash_wp
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set_location_assignment PIN_24 -to flash_cs
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set_location_assignment PIN_23 -to flash_sck
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set_location_assignment PIN_68 -to cy_data0
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set_location_assignment PIN_63 -to cy_dclk
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set_location_assignment PIN_67 -to cy_nconfig
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set_location_assignment PIN_21 -to flash_so
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set_location_assignment PIN_16 -to cy_conf_done |