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https://github.com/UzixLS/TSConf_MiST.git
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fix left-right sound channels intermodulation
This commit is contained in:
Eugene Lozovoy
@ -20,9 +20,9 @@
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module compressor
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(
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input clk,
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input [11:0] in1, in2,
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output [15:0] out1, out2
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input clk,
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input [11:0] in1, in2,
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output reg [15:0] out1, out2
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);
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reg [10:0] a1;
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255
rtl/sound/hybrid_pwm_sd_2ndorder.v
Normal file
255
rtl/sound/hybrid_pwm_sd_2ndorder.v
Normal file
@ -0,0 +1,255 @@
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// Hybrid PWM / Sigma Delta DAC
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//
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// 16-bit Sigma Delta with 5-bit output, feeding a PWM.
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// If rising and falling edges aren't perfectly symmetrical, a significant
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// amount of noise can be introduced into a sigma-delta DAC, since the number
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// of rising- and falling-edges within a given time period is either directly
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// dependent upon the code, or pseudo-random.
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// The PWM output stage, on the other hand, results results in a constant
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// number of rising- and falling-edges in a given time period, so any edge imbalance
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// will result in a DC offset rather than audible noise.
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// 2nd order variant with low-pass input filter and high-pass feedback filter.
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// Copyright 2021 by Alastair M. Robinson
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that they will
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// be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>
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//
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module hybrid_pwm_sd_2ndorder #(parameter signalwidth=16, parameter filtersize=4)
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(
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input clk,
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input reset_n,
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input [signalwidth-1:0] d_l,
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output q_l,
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input [signalwidth-1:0] d_r,
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output q_r
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);
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reg q_l_reg;
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reg q_r_reg;
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assign q_l=q_l_reg;
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assign q_r=q_r_reg;
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reg [12:0] initctr;
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reg init = 1'b1;
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reg initfilterena;
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always @(posedge clk)
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begin
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initfilterena<=1'b0;
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if(init)
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begin
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if(infilterena)
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begin
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initctr<=initctr+1'b1;
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if(initctr==0)
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initfilterena<=1'b1;
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end
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if(infiltered_l[signalwidth-1:3]==d_l[signalwidth-1:3])
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init<=1'b0;
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end
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end
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// Input filtering - a simple single-pole IIR low-pass filter.
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// configurable number of bits.
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wire [signalwidth-1:0] infiltered_l;
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wire [signalwidth-1:0] infiltered_r;
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reg infilterena;
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iirfilter_stereo # (.signalwidth(signalwidth),.cbits(filtersize),.immediate(0)) inputfilter
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(
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.clk(clk),
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.reset_n(reset_n),
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.ena(init ? initfilterena : infilterena),
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.d_l(d_l),
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.d_r(d_r),
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.q_l(infiltered_l),
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.q_r(infiltered_r)
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);
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// Approximation of reconstruction filter,
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// subtracted from the incoming signal to
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// steer the first stage of the sigma delta.
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// 9 bits for the coefficient (1/512)
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wire [signalwidth-1:0] outfiltered_l;
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wire [signalwidth-1:0] outfiltered_r;
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iirfilter_stereo # (.signalwidth(signalwidth),.cbits(9),.immediate(1)) outputfilter
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(
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.clk(clk),
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.reset_n(reset_n),
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.ena(1'b1),
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.d_l(q_l_reg ? {signalwidth{1'b1}} : {signalwidth{1'b0}}),
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.d_r(q_r_reg ? {signalwidth{1'b1}} : {signalwidth{1'b0}}),
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.q_l(outfiltered_l),
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.q_r(outfiltered_r)
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);
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reg [6:0] pwmcounter;
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wire [6:0] pwmthreshold_l;
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wire [6:0] pwmthreshold_r;
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reg [33:0] scaledin;
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reg [signalwidth+1:0] sigma_l;
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reg [signalwidth+1:0] sigma2_l;
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reg [signalwidth+1:0] sigma_r;
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reg [signalwidth+1:0] sigma2_r;
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wire [signalwidth+1:0] sigmanext_l;
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wire [signalwidth+1:0] sigmanext_r;
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assign sigmanext_l = sigma_l+{2'b0,infiltered_l}-{2'b0,outfiltered_l};
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assign sigmanext_r = sigma_r+{2'b0,infiltered_r}-{2'b0,outfiltered_r};
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assign pwmthreshold_l = sigma2_l[signalwidth+1:signalwidth-5];
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assign pwmthreshold_r = sigma2_r[signalwidth+1:signalwidth-5];
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always @(posedge clk,negedge reset_n)
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begin
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if(!reset_n) begin
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sigma_l<={signalwidth+2{1'b0}};
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sigma_r<={signalwidth+2{1'b0}};
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sigma2_l={signalwidth+2{1'b0}};
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sigma2_r={signalwidth+2{1'b0}};
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pwmcounter<=7'b111110;
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end else begin
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infilterena<=1'b0;
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if(pwmcounter==pwmthreshold_l)
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q_l_reg<=1'b0;
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if(pwmcounter==pwmthreshold_r)
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q_r_reg<=1'b0;
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if(pwmcounter==7'b11111) // Update threshold just before pwmcounter wraps around
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begin
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infilterena<=1'b1;
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// PWM
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sigma_l<=sigmanext_l;
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sigma2_l=sigmanext_l+{7'b0010000,sigma2_l[signalwidth-6:0]};
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sigma_r<=sigmanext_r;
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sigma2_r=sigmanext_r+{7'b0010000,sigma2_r[signalwidth-6:0]};
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if(sigma2_l[signalwidth+1]==1'b1)
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q_l_reg<=1'b0;
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else
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q_l_reg<=1'b1;
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if(sigma2_r[signalwidth+1]==1'b1)
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q_r_reg<=1'b0;
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else
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q_r_reg<=1'b1;
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end
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pwmcounter[6:5]<=2'b0;
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pwmcounter[4:0]<=pwmcounter[4:0]+5'b1;
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end
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end
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endmodule
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module iirfilter_stereo #
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(
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parameter signalwidth = 16,
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parameter cbits = 5,
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parameter immediate
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)
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(
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input clk,
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input reset_n,
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input ena,
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input [signalwidth-1:0] d_l,
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input [signalwidth-1:0] d_r,
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output [signalwidth-1:0] q_l,
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output [signalwidth-1:0] q_r
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);
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iirfilter_mono # (.signalwidth(signalwidth),.cbits(cbits),.immediate(immediate)) left
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(
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.clk(clk),
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.reset_n(reset_n),
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.ena(ena),
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.d(d_l),
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.q(q_l)
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);
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iirfilter_mono # (.signalwidth(signalwidth),.cbits(cbits),.immediate(immediate)) right
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(
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.clk(clk),
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.reset_n(reset_n),
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.ena(ena),
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.d(d_r),
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.q(q_r)
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);
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endmodule
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// Simplistic IIR low-pass filter.
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// function is simply y += b * (x - y)
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// where b=1/(1<<cbits)
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module iirfilter_mono #
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(
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parameter signalwidth = 16,
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parameter cbits = 5, // Bits for coefficient (default 1/32)
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parameter immediate = 0,
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parameter powerup = 1
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)
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(
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input clk,
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input reset_n,
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input ena,
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input [signalwidth-1:0] d,
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output [signalwidth-1:0] q
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);
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reg [signalwidth+cbits-1:0] acc = {powerup ? {signalwidth{1'b1}} : {signalwidth{1'b0}} , {cbits{1'b0}}};
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wire [signalwidth+cbits-1:0] acc_new;
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wire [signalwidth+cbits:0] delta = {d,{cbits{1'b0}}} - acc;
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assign acc_new = acc + {{cbits{delta[signalwidth+cbits]}},delta[signalwidth+cbits-1:cbits]};
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always @(posedge clk, negedge reset_n)
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begin
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if(!reset_n)
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begin
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acc[signalwidth+cbits-1:0]<={powerup ? {signalwidth{1'b1}} : {signalwidth{1'b0}} , {cbits{1'b0}}};
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end
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else if(ena)
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acc <= acc_new;
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end
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// Based on the immediate signal, q is either combinational or registered.
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assign q=immediate ? acc_new[signalwidth+cbits-1:cbits] : acc[signalwidth+cbits-1:cbits];
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endmodule
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