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54 lines
1.6 KiB
Verilog
54 lines
1.6 KiB
Verilog
//============================================================================
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// Audio compressor (signed samples)
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//
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// Copyright (C) 2018 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module compressor
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(
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input clk,
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input [11:0] in1, in2,
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output reg [15:0] out1, out2
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);
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reg [10:0] a1;
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reg [10:0] a2;
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reg in1_11;
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reg in2_11;
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always @(posedge clk) begin
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in1_11 <= in1[11];
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in2_11 <= in2[11];
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a1 <= {11{in1[11]}} ^ in1[10:0];
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a2 <= {11{in2[11]}} ^ in2[10:0];
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out1 <= {in1_11, {15{in1_11}} ^ q1};
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out2 <= {in2_11, {15{in2_11}} ^ q2};
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end
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//sin(x)
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wire [14:0] q1;
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wire [14:0] q2;
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dpram #(.DATAWIDTH(15), .ADDRWIDTH(11), .MEM_INIT_FILE("rtl/sound/compressor.mif")) tbl
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(
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.clock (clk),
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.address_a (a1),
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.q_a (q1),
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.address_b (a2),
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.q_b (q2)
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);
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endmodule
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